Lines Matching +full:0 +full:x64e00000
25 * base+0 data
33 * base+0x400 ECP config A
34 * base+0x401 ECP config B
35 * base+0x402 ECP control
42 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
85 #define ECR_MODE_MASK 0xe0
86 #define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
95 } superios[NR_SUPERIOS] = { {0,},};
109 unsigned char ectr = 0; in frob_econtrol()
111 if (m != 0xff) in frob_econtrol()
128 0 : Success
138 pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m); in change_mode()
142 return 0; in change_mode()
147 mode = (oecr >> 5) & 0x7; in change_mode()
149 return 0; in change_mode()
151 if (mode >= 2 && !(priv->ctr & 0x20)) { in change_mode()
160 for (counter = 0; counter < 40; counter++) { in change_mode()
161 if (inb(ECONTROL(p)) & 0x01) in change_mode()
169 while (!(inb(ECONTROL(p)) & 0x01)) { in change_mode()
192 return 0; in change_mode()
205 if (!(parport_pc_read_status(pb) & 0x01)) in clear_epp_timeout()
211 outb(r | 0x01, STATUS(pb)); /* Some reset by writing 1 */ in clear_epp_timeout()
212 outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */ in clear_epp_timeout()
215 return !(r & 0x01); in clear_epp_timeout()
229 s->u.pc.ctr = 0xc; in parport_pc_init_state()
233 s->u.pc.ctr |= 0x10; in parport_pc_init_state()
235 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24; in parport_pc_init_state()
262 size_t got = 0; in parport_pc_epp_read_data()
269 * nFault is 0 if there is at least 1 byte in the Warp's FIFO in parport_pc_epp_read_data()
274 while (!(status & 0x08) && got < length) { in parport_pc_epp_read_data()
275 if (left >= 16 && (status & 0x20) && !(status & 0x08)) { in parport_pc_epp_read_data()
277 if (!((long)buf & 0x03)) in parport_pc_epp_read_data()
292 if (status & 0x01) { in parport_pc_epp_read_data()
302 if (!(((long)buf | length) & 0x03)) in parport_pc_epp_read_data()
306 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_read_data()
315 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_read_data()
328 size_t written = 0; in parport_pc_epp_write_data()
331 if (!(((long)buf | length) & 0x03)) in parport_pc_epp_write_data()
335 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_write_data()
344 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_write_data()
356 size_t got = 0; in parport_pc_epp_read_addr()
360 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_read_addr()
369 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_read_addr()
382 size_t written = 0; in parport_pc_epp_write_addr()
386 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_write_addr()
395 if (inb(STATUS(port)) & 0x01) { in parport_pc_epp_write_addr()
411 parport_pc_write_control(port, 0x4); in parport_pc_ecpepp_read_data()
425 parport_pc_write_control(port, 0x4); in parport_pc_ecpepp_write_data()
440 parport_pc_write_control(port, 0x4); in parport_pc_ecpepp_read_addr()
454 parport_pc_write_control(port, 0x4); in parport_pc_ecpepp_write_addr()
467 int ret = 0; in parport_pc_fifo_write_block_pio()
489 int i = 0; in parport_pc_fifo_write_block_pio()
501 if (ecrval & 0x02) { in parport_pc_fifo_write_block_pio()
508 if (ret < 0) in parport_pc_fifo_write_block_pio()
510 ret = 0; in parport_pc_fifo_write_block_pio()
535 if (ecrval & 0x01) { in parport_pc_fifo_write_block_pio()
565 int ret = 0; in parport_pc_fifo_write_block_dma()
571 size_t maxlen = 0x10000; /* max 64k per DMA transfer */ in parport_pc_fifo_write_block_dma()
578 if ((start ^ end) & ~0xffffUL) in parport_pc_fifo_write_block_dma()
579 maxlen = 0x10000 - (start & 0xffff); in parport_pc_fifo_write_block_dma()
588 dma_handle = 0; in parport_pc_fifo_write_block_dma()
623 frob_econtrol(port, 1<<2, 0); in parport_pc_fifo_write_block_dma()
637 if (ret < 0) in parport_pc_fifo_write_block_dma()
639 ret = 0; in parport_pc_fifo_write_block_dma()
681 frob_econtrol(port, 1<<3, 0); in parport_pc_fifo_write_block_dma()
719 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0); in parport_pc_compat_write_block_pio()
751 if (inb(ECONTROL(port)) & 0x2) { in parport_pc_compat_write_block_pio()
755 outb(0, FIFO(port)); in parport_pc_compat_write_block_pio()
815 0); in parport_pc_ecp_write_block_pio()
846 if (inb(ECONTROL(port)) & 0x2) { in parport_pc_ecp_write_block_pio()
850 outb(0, FIFO(port)); in parport_pc_ecp_write_block_pio()
859 parport_frob_control(port, PARPORT_CONTROL_INIT, 0); in parport_pc_ecp_write_block_pio()
860 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); in parport_pc_ecp_write_block_pio()
940 for (i = 0; i < NR_SUPERIOS; i++) in find_free_superio()
941 if (superios[i].io == 0) in find_free_superio()
965 outb(0x0a, io); in show_parconfig_smsc37c669()
967 outb(0x23, io); in show_parconfig_smsc37c669()
969 outb(0x26, io); in show_parconfig_smsc37c669()
971 outb(0x27, io); in show_parconfig_smsc37c669()
973 outb(0xaa, io); in show_parconfig_smsc37c669()
976 …pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n… in show_parconfig_smsc37c669()
982 pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", in show_parconfig_smsc37c669()
984 (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', in show_parconfig_smsc37c669()
985 (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', in show_parconfig_smsc37c669()
986 cra & 0x0f); in show_parconfig_smsc37c669()
988 (cr23 * 4 >= 0x100) ? "yes" : "no", in show_parconfig_smsc37c669()
991 (cr1 & 0x08) ? "Standard mode only (SPP)" in show_parconfig_smsc37c669()
992 : modes[cr4 & 0x03], in show_parconfig_smsc37c669()
993 (cr4 & 0x40) ? "1.7" : "1.9"); in show_parconfig_smsc37c669()
1000 if (cr23 * 4 >= 0x100) { /* if active */ in show_parconfig_smsc37c669()
1007 case 0x3bc: in show_parconfig_smsc37c669()
1008 s->io = 0x3bc; in show_parconfig_smsc37c669()
1011 case 0x378: in show_parconfig_smsc37c669()
1012 s->io = 0x378; in show_parconfig_smsc37c669()
1015 case 0x278: in show_parconfig_smsc37c669()
1016 s->io = 0x278; in show_parconfig_smsc37c669()
1019 d = (cr26 & 0x0f); in show_parconfig_smsc37c669()
1034 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */ in show_parconfig_winbond()
1051 outb(0x07, io); /* Register 7: Select Logical Device */ in show_parconfig_winbond()
1052 outb(0x01, io + 1); /* LD1 is Parallel Port */ in show_parconfig_winbond()
1053 outb(0x30, io); in show_parconfig_winbond()
1055 outb(0x60, io); in show_parconfig_winbond()
1057 outb(0x61, io); in show_parconfig_winbond()
1059 outb(0x70, io); in show_parconfig_winbond()
1061 outb(0x74, io); in show_parconfig_winbond()
1063 outb(0xf0, io); in show_parconfig_winbond()
1065 outb(0xaa, io); in show_parconfig_winbond()
1070 pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", in show_parconfig_winbond()
1071 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); in show_parconfig_winbond()
1072 if ((cr74 & 0x07) > 3) in show_parconfig_winbond()
1075 pr_cont("dma=%d\n", cr74 & 0x07); in show_parconfig_winbond()
1077 irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f); in show_parconfig_winbond()
1079 modes[crf0 & 0x07]); in show_parconfig_winbond()
1082 if (cr30 & 0x01) { /* the settings can be interrogated later ... */ in show_parconfig_winbond()
1088 s->irq = cr70 & 0x0f; in show_parconfig_winbond()
1089 s->dma = (((cr74 & 0x07) > 3) ? in show_parconfig_winbond()
1090 PARPORT_DMA_NONE : (cr74 & 0x07)); in show_parconfig_winbond()
1109 if (id == 0x9771) in decode_winbond()
1111 else if (id == 0x9773) in decode_winbond()
1113 else if (id == 0x9774) in decode_winbond()
1115 else if ((id & ~0x0f) == 0x5270) in decode_winbond()
1117 else if ((id & ~0x0f) == 0x52f0) in decode_winbond()
1119 else if ((id & ~0x0f) == 0x5210) in decode_winbond()
1121 else if ((id & ~0x0f) == 0x6010) in decode_winbond()
1123 else if ((oldid & 0x0f) == 0x0a) { in decode_winbond()
1126 } else if ((oldid & 0x0f) == 0x0b) { in decode_winbond()
1129 } else if ((oldid & 0x0f) == 0x0c) { in decode_winbond()
1132 } else if ((oldid & 0x0f) == 0x0d) { in decode_winbond()
1136 progif = 0; in decode_winbond()
1139 pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n", in decode_winbond()
1160 if (id == 0x0302) { in decode_smsc()
1163 } else if (id == 0x6582) in decode_smsc()
1165 else if (devid == 0x65) in decode_smsc()
1167 else if (devid == 0x66) in decode_smsc()
1171 pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n", in decode_smsc()
1189 outb(0x20, io); in winbond_check()
1191 outb(0x21, io); in winbond_check()
1193 outb(0x09, io); in winbond_check()
1199 outb(0x20, io); /* Write EFIR, extended function index register */ in winbond_check()
1201 outb(0x21, io); in winbond_check()
1203 outb(0x09, io); in winbond_check()
1205 outb(0xaa, io); /* Magic Seal */ in winbond_check()
1224 origval[0] = inb(io); /* Save original values */ in winbond_check2()
1229 outb(0x20, io + 2); in winbond_check2()
1231 outb(0x21, io + 1); in winbond_check2()
1233 outb(0x09, io + 1); in winbond_check2()
1238 outb(0x20, io + 2); /* Write EFIR, extended function index register */ in winbond_check2()
1240 outb(0x21, io + 1); in winbond_check2()
1242 outb(0x09, io + 1); in winbond_check2()
1244 outb(0xaa, io); /* Magic Seal */ in winbond_check2()
1246 outb(origval[0], io); /* in case we poked some entirely different hardware */ in winbond_check2()
1268 outb(0x0d, io); in smsc_check()
1270 outb(0x0e, io); in smsc_check()
1272 outb(0x20, io); in smsc_check()
1274 outb(0x21, io); in smsc_check()
1280 outb(0x0d, io); /* Write EFIR, extended function index register */ in smsc_check()
1282 outb(0x0e, io); in smsc_check()
1284 outb(0x20, io); in smsc_check()
1286 outb(0x21, io); in smsc_check()
1288 outb(0xaa, io); /* Magic Seal */ in smsc_check()
1306 winbond_check(0x3f0, 0x87); in detect_and_report_winbond()
1307 winbond_check(0x370, 0x87); in detect_and_report_winbond()
1308 winbond_check(0x2e , 0x87); in detect_and_report_winbond()
1309 winbond_check(0x4e , 0x87); in detect_and_report_winbond()
1310 winbond_check(0x3f0, 0x86); in detect_and_report_winbond()
1311 winbond_check2(0x250, 0x88); in detect_and_report_winbond()
1312 winbond_check2(0x250, 0x89); in detect_and_report_winbond()
1319 smsc_check(0x3f0, 0x55); in detect_and_report_smsc()
1320 smsc_check(0x370, 0x55); in detect_and_report_smsc()
1321 smsc_check(0x3f0, 0x44); in detect_and_report_smsc()
1322 smsc_check(0x370, 0x44); in detect_and_report_smsc()
1331 if (!request_muxed_region(0x2e, 2, __func__)) in detect_and_report_it87()
1333 origval = inb(0x2e); /* Save original value */ in detect_and_report_it87()
1334 outb(0x87, 0x2e); in detect_and_report_it87()
1335 outb(0x01, 0x2e); in detect_and_report_it87()
1336 outb(0x55, 0x2e); in detect_and_report_it87()
1337 outb(0x55, 0x2e); in detect_and_report_it87()
1338 outb(0x20, 0x2e); in detect_and_report_it87()
1339 dev = inb(0x2f) << 8; in detect_and_report_it87()
1340 outb(0x21, 0x2e); in detect_and_report_it87()
1341 dev |= inb(0x2f); in detect_and_report_it87()
1342 if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || in detect_and_report_it87()
1343 dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { in detect_and_report_it87()
1345 outb(0x07, 0x2E); /* Parallel Port */ in detect_and_report_it87()
1346 outb(0x03, 0x2F); in detect_and_report_it87()
1347 outb(0xF0, 0x2E); /* BOOT 0x80 off */ in detect_and_report_it87()
1348 r = inb(0x2f); in detect_and_report_it87()
1349 outb(0xF0, 0x2E); in detect_and_report_it87()
1350 outb(r | 8, 0x2F); in detect_and_report_it87()
1351 outb(0x02, 0x2E); /* Lock */ in detect_and_report_it87()
1352 outb(0x02, 0x2F); in detect_and_report_it87()
1354 outb(origval, 0x2e); /* Oops, sorry to disturb */ in detect_and_report_it87()
1356 release_region(0x2e, 2); in detect_and_report_it87()
1363 for (i = 0; i < NR_SUPERIOS; i++) in find_superio()
1391 * 0 : No parallel port at this address
1410 w = 0xc; in parport_SPP_supported()
1419 if ((r & 0xf) == w) { in parport_SPP_supported()
1420 w = 0xe; in parport_SPP_supported()
1423 outb(0xc, CONTROL(pb)); in parport_SPP_supported()
1424 if ((r & 0xf) == w) in parport_SPP_supported()
1431 pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n", in parport_SPP_supported()
1436 w = 0xaa; in parport_SPP_supported()
1440 w = 0x55; in parport_SPP_supported()
1450 pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n", in parport_SPP_supported()
1452 pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n", in parport_SPP_supported()
1461 return 0; in parport_SPP_supported()
1466 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1469 * Modern cards don't do this but reading from ECR will return 0xff
1480 unsigned char r = 0xc; in parport_ECR_present()
1483 if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { in parport_ECR_present()
1484 outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ in parport_ECR_present()
1487 if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) in parport_ECR_present()
1491 if ((inb(ECONTROL(pb)) & 0x3) != 0x1) in parport_ECR_present()
1494 ECR_WRITE(pb, 0x34); in parport_ECR_present()
1495 if (inb(ECONTROL(pb)) != 0x35) in parport_ECR_present()
1499 outb(0xc, CONTROL(pb)); in parport_ECR_present()
1507 outb(0xc, CONTROL(pb)); in parport_ECR_present()
1508 return 0; in parport_ECR_present()
1514 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1516 * 0xff but any peripheral attached to the port may drag some or all of the
1531 int ok = 0; in parport_PS2_supported()
1538 parport_pc_write_data(pb, 0x55); in parport_PS2_supported()
1539 if (parport_pc_read_data(pb) != 0x55) in parport_PS2_supported()
1542 parport_pc_write_data(pb, 0xaa); in parport_PS2_supported()
1543 if (parport_pc_read_data(pb) != 0xaa) in parport_PS2_supported()
1553 priv->ctr_writable &= ~0x20; in parport_PS2_supported()
1567 static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 }; in parport_ECP_supported()
1571 return 0; in parport_ECP_supported()
1576 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++) in parport_ECP_supported()
1577 outb(0xaa, FIFO(pb)); in parport_ECP_supported()
1585 return 0; in parport_ECP_supported()
1590 printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i); in parport_ECP_supported()
1594 frob_econtrol(pb, 1<<2, 0); in parport_ECP_supported()
1604 printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", in parport_ECP_supported()
1609 i = 0; in parport_ECP_supported()
1618 frob_econtrol(pb, 1<<2, 0); in parport_ECP_supported()
1620 outb(0xaa, FIFO(pb)); in parport_ECP_supported()
1627 pr_info("0x%lx: readIntrThreshold is %d\n", in parport_ECP_supported()
1631 i = 0; in parport_ECP_supported()
1636 ECR_WRITE(pb, 0xf4); /* Configuration mode */ in parport_ECP_supported()
1638 pword = (config >> 4) & 0x7; in parport_ECP_supported()
1640 case 0: in parport_ECP_supported()
1642 pr_warn("0x%lx: Unsupported pword size!\n", pb->base); in parport_ECP_supported()
1646 pr_warn("0x%lx: Unsupported pword size!\n", pb->base); in parport_ECP_supported()
1649 pr_warn("0x%lx: Unknown implementation ID\n", pb->base); in parport_ECP_supported()
1657 printk(KERN_DEBUG "0x%lx: PWord is %d bits\n", in parport_ECP_supported()
1660 printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", in parport_ECP_supported()
1661 pb->base, config & 0x80 ? "Level" : "Pulses"); in parport_ECP_supported()
1664 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", in parport_ECP_supported()
1666 printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); in parport_ECP_supported()
1667 if ((configb >> 3) & 0x07) in parport_ECP_supported()
1668 pr_cont("%d", intrline[(configb >> 3) & 0x07]); in parport_ECP_supported()
1672 if ((configb & 0x03) == 0x00) in parport_ECP_supported()
1675 pr_cont("%d\n", configb & 0x07); in parport_ECP_supported()
1689 int bug_present = 0; in intel_bug_present_check_epp()
1695 for (i = 0x00; i < 0x80; i += 0x20) { in intel_bug_present_check_epp()
1713 return 0; in intel_bug_present()
1721 return 0; in intel_bug_present()
1732 return 0; in parport_ECPPS2_supported()
1747 * Bit 0 of STR is the EPP timeout bit, this bit is 0 in parport_EPP_supported()
1760 return 0; /* No way to clear timeout */ in parport_EPP_supported()
1764 return 0; in parport_EPP_supported()
1784 return 0; in parport_ECPEPP_supported()
1788 ECR_WRITE(pb, 0x80); in parport_ECPEPP_supported()
1789 outb(0x04, CONTROL(pb)); in parport_ECPEPP_supported()
1808 static int parport_PS2_supported(struct parport *pb) { return 0; } in parport_PS2_supported()
1812 return 0; in parport_ECP_supported()
1817 return 0; in parport_EPP_supported()
1822 return 0; in parport_ECPEPP_supported()
1827 return 0; in parport_ECPPS2_supported()
1845 intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07; in programmable_irq_support()
1860 ECR_WRITE(pb, (ECR_TST << 5) | 0x04); in irq_probe_ECP()
1864 for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++) in irq_probe_ECP()
1865 outb(0xaa, FIFO(pb)); in irq_probe_ECP()
1870 if (pb->irq <= 0) in irq_probe_ECP()
1894 frob_econtrol(pb, 0x10, 0x10); in irq_probe_EPP()
1897 parport_pc_frob_control(pb, 0x20, 0x20); in irq_probe_EPP()
1898 parport_pc_frob_control(pb, 0x10, 0x10); in irq_probe_EPP()
1910 parport_pc_write_control(pb, 0xc); in irq_probe_EPP()
1912 if (pb->irq <= 0) in irq_probe_EPP()
1973 dma = inb(CONFIGB(p)) & 0x07; in programmable_dma_support()
1976 if ((dma & 0x03) == 0) in programmable_dma_support()
2023 base, NULL, 0); in parport_pc_probe_port()
2053 priv->ctr = 0xc; in parport_pc_probe_port()
2054 priv->ctr_writable = ~0x10; in parport_pc_probe_port()
2055 priv->ecr = 0; in parport_pc_probe_port()
2056 priv->fifo_depth = 0; in parport_pc_probe_port()
2058 priv->dma_handle = 0; in parport_pc_probe_port()
2073 if (base != 0x3bc) { in parport_pc_probe_port()
2074 EPP_res = request_region(base+0x3, 5, p->name); in parport_pc_probe_port()
2089 pr_info("%s: PC-style at 0x%lx", p->name, p->base); in parport_pc_probe_port()
2091 pr_cont(" (0x%lx)", p->base_hi); in parport_pc_probe_port()
2103 priv->ctr_writable |= 0x10; in parport_pc_probe_port()
2117 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { in parport_pc_probe_port()
2141 } while (0) in parport_pc_probe_port()
2144 int f = 0; in parport_pc_probe_port()
2161 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { in parport_pc_probe_port()
2166 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) { in parport_pc_probe_port()
2210 ECR_WRITE(p, 0x34); in parport_pc_probe_port()
2212 parport_pc_write_data(p, 0); in parport_pc_probe_port()
2229 release_region(base+0x3, 5); in parport_pc_probe_port()
2282 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 }; in sio_ite_8872_probe()
2292 for (i = 0; i < 5; i++) { in sio_ite_8872_probe()
2295 pci_write_config_dword(pdev, 0x60, in sio_ite_8872_probe()
2296 0xe5000000 | inta_addr[i]); in sio_ite_8872_probe()
2297 pci_write_config_dword(pdev, 0x78, in sio_ite_8872_probe()
2298 0x00000000 | inta_addr[i]); in sio_ite_8872_probe()
2300 if (test != 0xff) in sio_ite_8872_probe()
2307 return 0; in sio_ite_8872_probe()
2310 type = inb(inta_addr[i] + 0x18); in sio_ite_8872_probe()
2311 type &= 0x0f; in sio_ite_8872_probe()
2314 case 0x2: in sio_ite_8872_probe()
2316 ite8872set = 0x64200000; in sio_ite_8872_probe()
2318 case 0xa: in sio_ite_8872_probe()
2320 ite8872set = 0x64200000; in sio_ite_8872_probe()
2322 case 0xe: in sio_ite_8872_probe()
2324 ite8872set = 0x64e00000; in sio_ite_8872_probe()
2326 case 0x6: in sio_ite_8872_probe()
2329 return 0; in sio_ite_8872_probe()
2330 case 0x8: in sio_ite_8872_probe()
2333 return 0; in sio_ite_8872_probe()
2338 return 0; in sio_ite_8872_probe()
2341 pci_read_config_byte(pdev, 0x3c, &ite8872_irq); in sio_ite_8872_probe()
2342 pci_read_config_dword(pdev, 0x1c, &ite8872_lpt); in sio_ite_8872_probe()
2343 ite8872_lpt &= 0x0000ff00; in sio_ite_8872_probe()
2344 pci_read_config_dword(pdev, 0x20, &ite8872_lpthi); in sio_ite_8872_probe()
2345 ite8872_lpthi &= 0x0000ff00; in sio_ite_8872_probe()
2346 pci_write_config_dword(pdev, 0x6c, 0xe3000000 | ite8872_lpt); in sio_ite_8872_probe()
2347 pci_write_config_dword(pdev, 0x70, 0xe3000000 | ite8872_lpthi); in sio_ite_8872_probe()
2348 pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt); in sio_ite_8872_probe()
2351 pci_write_config_dword(pdev, 0x9c, in sio_ite_8872_probe()
2352 ite8872set | (ite8872_irq * 0x11111)); in sio_ite_8872_probe()
2355 pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt); in sio_ite_8872_probe()
2356 pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi); in sio_ite_8872_probe()
2368 irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { in sio_ite_8872_probe()
2369 pr_info("parport_pc: ITE 8872 parallel port: io=0x%X", in sio_ite_8872_probe()
2377 return 0; in sio_ite_8872_probe()
2386 0x51,
2387 0x50,
2388 0x85,
2389 0x02,
2390 0xE2,
2391 0xF0,
2392 0xE6
2395 0x45,
2396 0x44,
2397 0x50,
2398 0x04,
2399 0xF2,
2400 0xFA,
2401 0xF6
2408 u8 ppcontrol = 0; in sio_via_probe()
2411 unsigned have_epp = 0; in sio_via_probe()
2454 /* Bits 1-0: Parallel Port Mode / Enable */ in sio_via_probe()
2478 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n", in sio_via_probe()
2480 if (port1 == 0x3BC && have_epp) { in sio_via_probe()
2482 outb((0x378 >> 2), VIA_CONFIG_DATA); in sio_via_probe()
2483 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); in sio_via_probe()
2484 port1 = 0x378; in sio_via_probe()
2496 return 0; in sio_via_probe()
2521 case 0x3bc: in sio_via_probe()
2522 port2 = 0x7bc; break; in sio_via_probe()
2523 case 0x378: in sio_via_probe()
2524 port2 = 0x778; break; in sio_via_probe()
2525 case 0x278: in sio_via_probe()
2526 port2 = 0x678; break; in sio_via_probe()
2528 pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n", in sio_via_probe()
2530 return 0; in sio_via_probe()
2535 case 0: in sio_via_probe()
2547 if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) { in sio_via_probe()
2548 pr_info("parport_pc: VIA parallel port: io=0x%X", port1); in sio_via_probe()
2557 pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", in sio_via_probe()
2559 return 0; in sio_via_probe()
2564 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2641 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2642 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2643 /* lava_parallel */ { 1, { { 0, -1 }, } },
2644 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2645 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2646 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2648 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2649 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2650 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2651 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2652 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2655 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2656 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2658 /* avlab_1p */ { 1, { { 0, 1}, } },
2659 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2662 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2663 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2664 /* oxsemi_840 */ { 1, { { 0, 1 }, } },
2665 /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2666 /* aks_0100 */ { 1, { { 0, -1 }, } },
2667 /* mobility_pp */ { 1, { { 0, 1 }, } },
2670 /* netmos_9705 */ { 1, { { 0, -1 }, } },
2671 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2672 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2673 /* netmos_9805 */ { 1, { { 0, 1 }, } },
2674 /* netmos_9815 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2675 /* netmos_9901 */ { 1, { { 0, -1 }, } },
2676 /* netmos_9865 */ { 1, { { 0, -1 }, } },
2677 /* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2683 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2684 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2686 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2706 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2708 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2709 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2710 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2711 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2712 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2721 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2722 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2738 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2747 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2760 0xA000, 0x2000, 0, 0, netmos_9901 },
2762 0xA000, 0x1000, 0, 0, netmos_9865 },
2764 0xA000, 0x2000, 0, 0, netmos_9865 },
2767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2769 { 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382l },
2770 { 0, } /* terminate list */
2787 return 0; in parport_pc_pci_probe()
2791 count = 0; in parport_pc_pci_probe()
2806 for (n = 0; n < cards[i].numports; n++) { in parport_pc_pci_probe()
2812 io_hi = 0; in parport_pc_pci_probe()
2813 if ((hi >= 0) && (hi <= 6)) in parport_pc_pci_probe()
2840 cards[i].postinit_hook(dev, count == 0); in parport_pc_pci_probe()
2844 return 0; in parport_pc_pci_probe()
2858 for (i = data->num - 1; i >= 0; i--) in parport_pc_pci_remove()
2876 int ret = 0; in parport_pc_init_superio()
2896 return 0; in parport_pc_init_superio()
2904 {.id = "PNP0400", .driver_data = 0},
2906 {.id = "PNP0401", .driver_data = 0},
2919 if (pnp_port_valid(dev, 0) && in parport_pc_pnp_probe()
2920 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) { in parport_pc_pnp_probe()
2921 io_lo = pnp_port_start(dev, 0); in parport_pc_pnp_probe()
2929 io_hi = 0; in parport_pc_pnp_probe()
2931 if (pnp_irq_valid(dev, 0) && in parport_pc_pnp_probe()
2932 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) { in parport_pc_pnp_probe()
2933 irq = pnp_irq(dev, 0); in parport_pc_pnp_probe()
2937 if (pnp_dma_valid(dev, 0) && in parport_pc_pnp_probe()
2938 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) { in parport_pc_pnp_probe()
2939 dma = pnp_dma(dev, 0); in parport_pc_pnp_probe()
2944 pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0); in parport_pc_pnp_probe()
2949 return 0; in parport_pc_pnp_probe()
2977 return 0; in parport_pc_platform_probe()
2991 int count = 0; in parport_pc_find_isa_ports()
2993 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0)) in parport_pc_find_isa_ports()
2995 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0)) in parport_pc_find_isa_ports()
2997 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0)) in parport_pc_find_isa_ports()
3015 int count = 0, err; in parport_pc_find_ports()
3048 [0 ... PARPORT_PC_MAX_PORTS] = 0
3051 [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3054 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3057 [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3064 return 0; in parport_parse_param()
3073 unsigned long r = simple_strtoul(s, &ep, 0); in parport_parse_param()
3081 return 0; in parport_parse_param()
3087 PARPORT_IRQ_NONE, 0); in parport_parse_irq()
3121 module_param_hw_array(io, int, ioport, NULL, 0);
3123 module_param_hw_array(io_hi, int, ioport, NULL, 0);
3125 module_param_hw_array(irq, charp, irq, NULL, 0);
3127 module_param_hw_array(dma, charp, dma, NULL, 0);
3137 module_param(init_mode, charp, 0);
3150 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) { in parse_parport_params()
3158 if (!io[0]) { in parse_parport_params()
3160 if (irq[0] && !parport_parse_irq(irq[0], &val)) in parse_parport_params()
3164 irqval[0] = val; in parse_parport_params()
3170 if (dma[0] && !parport_parse_dma(dma[0], &val)) in parse_parport_params()
3174 dmaval[0] = val; in parse_parport_params()
3180 return 0; in parse_parport_params()
3190 * parport=0
3192 * parport=0xBASE[,IRQ[,DMA]]
3202 if (!str || !*str || (*str == '0' && !*(str+1))) { in parport_setup()
3203 /* Disable parport if "parport=0" in cmdline */ in parport_setup()
3204 io[0] = PARPORT_DISABLE; in parport_setup()
3209 irqval[0] = PARPORT_IRQ_AUTO; in parport_setup()
3210 dmaval[0] = PARPORT_DMA_AUTO; in parport_setup()
3214 val = simple_strtoul(str, &endptr, 0); in parport_setup()
3247 return io[0] == PARPORT_DISABLE; in parse_parport_params()
3275 if (io[0]) { in parport_pc_init()
3279 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) { in parport_pc_init()
3283 io_hi[i] = 0x400 + io[i]; in parport_pc_init()
3285 irqval[i], dmaval[i], NULL, 0); in parport_pc_init()
3288 parport_pc_find_ports(irqval[0], dmaval[0]); in parport_pc_init()
3290 return 0; in parport_pc_init()