1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019  Realtek Corporation
18 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
19 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
20 					-20, -24, -28, -31, -34, -37, -40, -44};
25 	ether_addr_copy(efuse->addr, map->e.mac_addr);  in rtw8821ce_efuse_parsing()
37 	struct rtw_efuse *efuse = &rtwdev->efuse;  in rtw8821c_read_efuse()
43 	efuse->rfe_option = map->rfe_option;  in rtw8821c_read_efuse()
44 	efuse->rf_board_option = map->rf_board_option;  in rtw8821c_read_efuse()
45 	efuse->crystal_cap = map->xtal_k;  in rtw8821c_read_efuse()
46 	efuse->pa_type_2g = map->pa_type;  in rtw8821c_read_efuse()
47 	efuse->pa_type_5g = map->pa_type;  in rtw8821c_read_efuse()
48 	efuse->lna_type_2g = map->lna_type_2g[0];  in rtw8821c_read_efuse()
49 	efuse->lna_type_5g = map->lna_type_5g[0];  in rtw8821c_read_efuse()
50 	efuse->channel_plan = map->channel_plan;  in rtw8821c_read_efuse()
51 	efuse->country_code[0] = map->country_code[0];  in rtw8821c_read_efuse()
52 	efuse->country_code[1] = map->country_code[1];  in rtw8821c_read_efuse()
53 	efuse->bt_setting = map->rf_bt_setting;  in rtw8821c_read_efuse()
54 	efuse->regd = map->rf_board_option & 0x7;  in rtw8821c_read_efuse()
55 	efuse->thermal_meter[0] = map->thermal_meter;  in rtw8821c_read_efuse()
56 	efuse->thermal_meter_k = map->thermal_meter;  in rtw8821c_read_efuse()
57 	efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;  in rtw8821c_read_efuse()
58 	efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;  in rtw8821c_read_efuse()
61 		efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];  in rtw8821c_read_efuse()
69 		return -ENOTSUPP;  in rtw8821c_read_efuse()
99 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;  in rtw8821c_pwrtrack_init()
103 		dm_info->default_ofdm_index = 24;  in rtw8821c_pwrtrack_init()
105 		dm_info->default_ofdm_index = swing_idx;  in rtw8821c_pwrtrack_init()
107 	ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);  in rtw8821c_pwrtrack_init()
108 	dm_info->delta_power_index[RF_PATH_A] = 0;  in rtw8821c_pwrtrack_init()
109 	dm_info->delta_power_index_last[RF_PATH_A] = 0;  in rtw8821c_pwrtrack_init()
110 	dm_info->pwr_trk_triggered = false;  in rtw8821c_pwrtrack_init()
111 	dm_info->pwr_trk_init_trigger = true;  in rtw8821c_pwrtrack_init()
112 	dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;  in rtw8821c_pwrtrack_init()
151 	crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;  in rtw8821c_phy_set_param()
154 	rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);  in rtw8821c_phy_set_param()
158 	rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);  in rtw8821c_phy_set_param()
159 	rtwdev->chip->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);  in rtw8821c_phy_set_param()
160 	rtwdev->chip->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);  in rtw8821c_phy_set_param()
163 	rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;  in rtw8821c_phy_set_param()
191 	rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));  in rtw8821c_mac_init()
204 	/* Set beacon cotnrol - enable TSF and other related functions */  in rtw8821c_mac_init()
221 	rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));  in rtw8821c_mac_init()
222 	rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, BIT(6));  in rtw8821c_mac_init()
234 	ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);  in rtw8821c_cfg_ldo25()
305 		if (rtwdev->efuse.rfe_option == 0)  in rtw8821c_set_channel_rf()
307 		else if (rtwdev->efuse.rfe_option == 2)  in rtw8821c_set_channel_rf()
309 		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);  in rtw8821c_set_channel_rf()
313 		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);  in rtw8821c_set_channel_rf()
318 	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);  in rtw8821c_set_channel_rf()
319 	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);  in rtw8821c_set_channel_rf()
326 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
327 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
328 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);  in rtw8821c_set_channel_rxdfir()
329 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);  in rtw8821c_set_channel_rxdfir()
332 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
333 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);  in rtw8821c_set_channel_rxdfir()
334 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);  in rtw8821c_set_channel_rxdfir()
335 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);  in rtw8821c_set_channel_rxdfir()
338 		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
339 		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);  in rtw8821c_set_channel_rxdfir()
340 		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);  in rtw8821c_set_channel_rxdfir()
341 		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);  in rtw8821c_set_channel_rxdfir()
351 		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);  in rtw8821c_set_channel_bb()
352 		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);  in rtw8821c_set_channel_bb()
353 		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);  in rtw8821c_set_channel_bb()
364 					 rtwdev->chip->ch_param[0]);  in rtw8821c_set_channel_bb()
366 					 rtwdev->chip->ch_param[1] & MASKLWORD);  in rtw8821c_set_channel_bb()
368 					 rtwdev->chip->ch_param[2]);  in rtw8821c_set_channel_bb()
371 		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);  in rtw8821c_set_channel_bb()
372 		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);  in rtw8821c_set_channel_bb()
373 		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);  in rtw8821c_set_channel_bb()
401 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);  in rtw8821c_set_channel_bb()
405 			rtw_write32_set(rtwdev, REG_RXSB, BIT(4));  in rtw8821c_set_channel_bb()
407 			rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));  in rtw8821c_set_channel_bb()
415 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);  in rtw8821c_set_channel_bb()
424 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);  in rtw8821c_set_channel_bb()
432 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);  in rtw8821c_set_channel_bb()
433 		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);  in rtw8821c_set_channel_bb()
441 		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);  in rtw8821c_set_channel_bb()
442 		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);  in rtw8821c_set_channel_bb()
449 	struct rtw_efuse efuse = rtwdev->efuse;  in rtw8821c_get_bb_swing()
481 	struct rtw_efuse *efuse = &rtwdev->efuse;  in get_cck_rx_pwr()
487 	if (efuse->rfe_option == 0) {  in get_cck_rx_pwr()
497 		return -120;  in get_cck_rx_pwr()
501 	rx_pwr_all = lna_gain - 2 * vga_idx;  in get_cck_rx_pwr()
518 	pkt_stat->rx_power[RF_PATH_A] = rx_power;  in query_phy_status_page0()
519 	pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);  in query_phy_status_page0()
520 	pkt_stat->bw = RTW_CHANNEL_WIDTH_20;  in query_phy_status_page0()
521 	pkt_stat->signal_power = rx_power;  in query_phy_status_page0()
528 	s8 min_rx_power = -120;  in query_phy_status_page1()
530 	if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)  in query_phy_status_page1()
537 	else if (rxsc >= 9 && rxsc <= 12)  in query_phy_status_page1()
544 	pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;  in query_phy_status_page1()
545 	pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);  in query_phy_status_page1()
546 	pkt_stat->bw = bw;  in query_phy_status_page1()
547 	pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],  in query_phy_status_page1()
576 	u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;  in rtw8821c_query_rx_desc()
581 	pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);  in rtw8821c_query_rx_desc()
582 	pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);  in rtw8821c_query_rx_desc()
583 	pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);  in rtw8821c_query_rx_desc()
584 	pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&  in rtw8821c_query_rx_desc()
586 	pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);  in rtw8821c_query_rx_desc()
587 	pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);  in rtw8821c_query_rx_desc()
588 	pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);  in rtw8821c_query_rx_desc()
589 	pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);  in rtw8821c_query_rx_desc()
590 	pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);  in rtw8821c_query_rx_desc()
591 	pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);  in rtw8821c_query_rx_desc()
592 	pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);  in rtw8821c_query_rx_desc()
593 	pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);  in rtw8821c_query_rx_desc()
595 	/* drv_info_sz is in unit of 8-bytes */  in rtw8821c_query_rx_desc()
596 	pkt_stat->drv_info_sz *= 8;  in rtw8821c_query_rx_desc()
599 	if (pkt_stat->is_c2h)  in rtw8821c_query_rx_desc()
602 	hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +  in rtw8821c_query_rx_desc()
603 				       pkt_stat->drv_info_sz);  in rtw8821c_query_rx_desc()
604 	if (pkt_stat->phy_status) {  in rtw8821c_query_rx_desc()
605 		phy_status = rx_desc + desc_sz + pkt_stat->shift;  in rtw8821c_query_rx_desc()
615 	struct rtw_hal *hal = &rtwdev->hal;  in rtw8821c_set_tx_power_index_by_rate()
623 		pwr_index = hal->tx_pwr_tbl[path][rate];  in rtw8821c_set_tx_power_index_by_rate()
637 	struct rtw_hal *hal = &rtwdev->hal;  in rtw8821c_set_tx_power_index()
640 	for (path = 0; path < hal->rf_path_num; path++) {  in rtw8821c_set_tx_power_index()
652 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;  in rtw8821c_false_alarm_statistics()
659 	cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);  in rtw8821c_false_alarm_statistics()
663 	dm_info->cck_fa_cnt = cck_fa_cnt;  in rtw8821c_false_alarm_statistics()
664 	dm_info->ofdm_fa_cnt = ofdm_fa_cnt;  in rtw8821c_false_alarm_statistics()
666 		dm_info->total_fa_cnt += cck_fa_cnt;  in rtw8821c_false_alarm_statistics()
667 	dm_info->total_fa_cnt = ofdm_fa_cnt;  in rtw8821c_false_alarm_statistics()
670 	dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);  in rtw8821c_false_alarm_statistics()
671 	dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);  in rtw8821c_false_alarm_statistics()
674 	dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);  in rtw8821c_false_alarm_statistics()
675 	dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);  in rtw8821c_false_alarm_statistics()
678 	dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);  in rtw8821c_false_alarm_statistics()
679 	dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);  in rtw8821c_false_alarm_statistics()
682 	dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);  in rtw8821c_false_alarm_statistics()
683 	dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);  in rtw8821c_false_alarm_statistics()
686 	dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);  in rtw8821c_false_alarm_statistics()
687 	dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;  in rtw8821c_false_alarm_statistics()
690 		dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);  in rtw8821c_false_alarm_statistics()
691 		dm_info->total_cca_cnt += dm_info->cck_cca_cnt;  in rtw8821c_false_alarm_statistics()
694 	rtw_write32_set(rtwdev, REG_FAS, BIT(17));  in rtw8821c_false_alarm_statistics()
695 	rtw_write32_clr(rtwdev, REG_FAS, BIT(17));  in rtw8821c_false_alarm_statistics()
696 	rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));  in rtw8821c_false_alarm_statistics()
697 	rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));  in rtw8821c_false_alarm_statistics()
698 	rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));  in rtw8821c_false_alarm_statistics()
699 	rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));  in rtw8821c_false_alarm_statistics()
723 	reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));  in rtw8821c_do_iqk()
747 	/* enable PTA (3-wire function form BT side) */  in rtw8821c_coex_cfg_init()
758 	/* beacon queue always hi-pri  */  in rtw8821c_coex_cfg_init()
766 	struct rtw_coex *coex = &rtwdev->coex;  in rtw8821c_coex_cfg_ant_switch()
767 	struct rtw_coex_dm *coex_dm = &coex->dm;  in rtw8821c_coex_cfg_ant_switch()
768 	struct rtw_coex_rfe *coex_rfe = &coex->rfe;  in rtw8821c_coex_cfg_ant_switch()
773 	if (switch_status == coex_dm->cur_switch_status)  in rtw8821c_coex_cfg_ant_switch()
776 	coex_dm->cur_switch_status = switch_status;  in rtw8821c_coex_cfg_ant_switch()
778 	if (coex_rfe->ant_switch_diversity &&  in rtw8821c_coex_cfg_ant_switch()
782 	polarity_inverse = (coex_rfe->ant_switch_polarity == 1);  in rtw8821c_coex_cfg_ant_switch()
794 			if (coex_rfe->rfe_module_type != 0x4 &&  in rtw8821c_coex_cfg_ant_switch()
795 			    coex_rfe->rfe_module_type != 0x2)  in rtw8821c_coex_cfg_ant_switch()
866 	struct rtw_coex *coex = &rtwdev->coex;  in rtw8821c_coex_cfg_rfe_type()
867 	struct rtw_coex_rfe *coex_rfe = &coex->rfe;  in rtw8821c_coex_cfg_rfe_type()
868 	struct rtw_efuse *efuse = &rtwdev->efuse;  in rtw8821c_coex_cfg_rfe_type()
870 	coex_rfe->rfe_module_type = efuse->rfe_option;  in rtw8821c_coex_cfg_rfe_type()
871 	coex_rfe->ant_switch_polarity = 0;  in rtw8821c_coex_cfg_rfe_type()
872 	coex_rfe->ant_switch_exist = true;  in rtw8821c_coex_cfg_rfe_type()
873 	coex_rfe->wlg_at_btg = false;  in rtw8821c_coex_cfg_rfe_type()
875 	switch (coex_rfe->rfe_module_type) {  in rtw8821c_coex_cfg_rfe_type()
879 	case 9:  /* 1-Ant, Main, WLG */  in rtw8821c_coex_cfg_rfe_type()
880 	default: /* 2-Ant, DPDT, WLG */  in rtw8821c_coex_cfg_rfe_type()
883 	case 10: /* 1-Ant, Main, BTG */  in rtw8821c_coex_cfg_rfe_type()
885 	case 15: /* 2-Ant, DPDT, BTG */  in rtw8821c_coex_cfg_rfe_type()
886 		coex_rfe->wlg_at_btg = true;  in rtw8821c_coex_cfg_rfe_type()
889 	case 11: /* 1-Ant, Aux, WLG */  in rtw8821c_coex_cfg_rfe_type()
890 		coex_rfe->ant_switch_polarity = 1;  in rtw8821c_coex_cfg_rfe_type()
893 	case 12: /* 1-Ant, Aux, BTG */  in rtw8821c_coex_cfg_rfe_type()
894 		coex_rfe->wlg_at_btg = true;  in rtw8821c_coex_cfg_rfe_type()
895 		coex_rfe->ant_switch_polarity = 1;  in rtw8821c_coex_cfg_rfe_type()
898 	case 13: /* 2-Ant, no switch, WLG */  in rtw8821c_coex_cfg_rfe_type()
900 	case 14: /* 2-Ant, no antenna switch, WLG */  in rtw8821c_coex_cfg_rfe_type()
901 		coex_rfe->ant_switch_exist = false;  in rtw8821c_coex_cfg_rfe_type()
908 	struct rtw_coex *coex = &rtwdev->coex;  in rtw8821c_coex_cfg_wl_tx_power()
909 	struct rtw_coex_dm *coex_dm = &coex->dm;  in rtw8821c_coex_cfg_wl_tx_power()
910 	struct rtw_efuse *efuse = &rtwdev->efuse;  in rtw8821c_coex_cfg_wl_tx_power()
911 	bool share_ant = efuse->share_ant;  in rtw8821c_coex_cfg_wl_tx_power()
916 	if (wl_pwr == coex_dm->cur_wl_pwr_lvl)  in rtw8821c_coex_cfg_wl_tx_power()
919 	coex_dm->cur_wl_pwr_lvl = wl_pwr;  in rtw8821c_coex_cfg_wl_tx_power()
930 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;  in rtw8821c_txagc_swing_offset()
931 	s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];  in rtw8821c_txagc_swing_offset()
932 	u8 swing_upper_bound = dm_info->default_ofdm_index + 10;  in rtw8821c_txagc_swing_offset()
936 	u8 swing_index = dm_info->default_ofdm_index;  in rtw8821c_txagc_swing_offset()
939 	pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);  in rtw8821c_txagc_swing_offset()
944 			swing_index = dm_info->default_ofdm_index;  in rtw8821c_txagc_swing_offset()
947 			swing_index = dm_info->default_ofdm_index +  in rtw8821c_txagc_swing_offset()
948 					delta_pwr_idx - pwr_idx_offset;  in rtw8821c_txagc_swing_offset()
954 			swing_index = dm_info->default_ofdm_index;  in rtw8821c_txagc_swing_offset()
956 			if (dm_info->default_ofdm_index >  in rtw8821c_txagc_swing_offset()
957 				(pwr_idx_offset_lower - delta_pwr_idx))  in rtw8821c_txagc_swing_offset()
958 				swing_index = dm_info->default_ofdm_index +  in rtw8821c_txagc_swing_offset()
959 					delta_pwr_idx - pwr_idx_offset_lower;  in rtw8821c_txagc_swing_offset()
969 		swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;  in rtw8821c_txagc_swing_offset()
991 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;  in rtw8821c_pwrtrack_set()
994 	u8 channel = rtwdev->hal.current_channel;  in rtw8821c_pwrtrack_set()
995 	u8 band_width = rtwdev->hal.current_band_width;  in rtw8821c_pwrtrack_set()
996 	u8 regd = rtwdev->regd.txpwr_regd;  in rtw8821c_pwrtrack_set()
997 	u8 tx_rate = dm_info->tx_rate;  in rtw8821c_pwrtrack_set()
998 	u8 max_pwr_idx = rtwdev->chip->max_power_index;  in rtw8821c_pwrtrack_set()
1005 	pwr_idx_offset = max_pwr_idx - tx_pwr_idx;  in rtw8821c_pwrtrack_set()
1006 	pwr_idx_offset_lower = 0 - tx_pwr_idx;  in rtw8821c_pwrtrack_set()
1013 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;  in rtw8821c_phy_pwrtrack()
1019 	if (rtwdev->efuse.thermal_meter[0] == 0xff)  in rtw8821c_phy_pwrtrack()
1026 	if (dm_info->pwr_trk_init_trigger)  in rtw8821c_phy_pwrtrack()
1027 		dm_info->pwr_trk_init_trigger = false;  in rtw8821c_phy_pwrtrack()
1034 	delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);  in rtw8821c_phy_pwrtrack()
1036 	dm_info->delta_power_index[RF_PATH_A] =  in rtw8821c_phy_pwrtrack()
1039 	if (dm_info->delta_power_index[RF_PATH_A] ==  in rtw8821c_phy_pwrtrack()
1040 			dm_info->delta_power_index_last[RF_PATH_A])  in rtw8821c_phy_pwrtrack()
1043 		dm_info->delta_power_index_last[RF_PATH_A] =  in rtw8821c_phy_pwrtrack()
1044 			dm_info->delta_power_index[RF_PATH_A];  in rtw8821c_phy_pwrtrack()
1054 	struct rtw_efuse *efuse = &rtwdev->efuse;  in rtw8821c_pwr_track()
1055 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;  in rtw8821c_pwr_track()
1057 	if (efuse->power_track_type != 0)  in rtw8821c_pwr_track()
1060 	if (!dm_info->pwr_trk_triggered) {  in rtw8821c_pwr_track()
1063 		dm_info->pwr_trk_triggered = true;  in rtw8821c_pwr_track()
1068 	dm_info->pwr_trk_triggered = false;  in rtw8821c_pwr_track()
1094 	if (bfee->role == RTW_BFEE_SU)  in rtw8821c_bf_config_bfee()
1096 	else if (bfee->role == RTW_BFEE_MU)  in rtw8821c_bf_config_bfee()
1104 	struct rtw_dm_info *dm_info = &rtwdev->dm_info;  in rtw8821c_phy_cck_pd_set()
1108 	rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",  in rtw8821c_phy_cck_pd_set()
1109 		dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);  in rtw8821c_phy_cck_pd_set()
1111 	if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)  in rtw8821c_phy_cck_pd_set()
1119 		dm_info->cck_pd_default + new_lvl * 2,  in rtw8821c_phy_cck_pd_set()
1120 		pd[new_lvl], dm_info->cck_fa_avg);  in rtw8821c_phy_cck_pd_set()
1122 	dm_info->cck_fa_avg = CCK_FA_AVG_RESET;  in rtw8821c_phy_cck_pd_set()
1124 	dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;  in rtw8821c_phy_cck_pd_set()
1127 			 dm_info->cck_pd_default + new_lvl * 2);  in rtw8821c_phy_cck_pd_set()
1135 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1140 	 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1145 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1150 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1173 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1183 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1188 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1193 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1198 	 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1203 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1208 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1213 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
1218 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1223 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1228 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1233 	 RTW_PWR_CMD_POLLING, BIT(0), 0},
1238 	 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1243 	 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1248 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1253 	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1254 	 (BIT(7) | BIT(6) | BIT(5))},
1259 	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1264 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1277 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1287 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1292 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1297 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1302 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1307 	 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1312 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1317 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1322 	 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1340 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1345 	 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1350 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1355 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1360 	 RTW_PWR_CMD_WRITE, BIT(4), 0},
1365 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1370 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1375 	 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1380 	 RTW_PWR_CMD_WRITE, BIT(2), 0},
1385 	 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1390 	 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1395 	 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1400 	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1405 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1410 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1415 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1585 /* rssi in percentage % (dbm = % - 100) */
1589 /* Shared-Antenna Coex Table */
1591 	{0x55555555, 0x55555555}, /* case-0 */
1596 	{0xfafafafa, 0xfafafafa}, /* case-5 */
1601 	{0x66555555, 0x6a5a5a5a}, /* case-10 */
1606 	{0x66555555, 0xaaaaaaaa}, /* case-15 */
1611 	{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1616 	{0xffffffff, 0x5a5a5aaa}, /* case-25 */
1621 	{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1626 /* Non-Shared-Antenna Coex Table */
1628 	{0xffffffff, 0xffffffff}, /* case-100 */
1633 	{0xffffffff, 0xffffffff}, /* case-105 */
1638 	{0x66555555, 0x6a5a5a5a}, /* case-110 */
1643 	{0xffff55ff, 0xffff55ff}, /* case-115 */
1648 	{0xffffffff, 0xaaaaaaaa}, /* case-120 */
1654 /* Shared-Antenna TDMA */
1656 	{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1657 	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1661 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1666 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1671 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1676 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1681 	{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1686 /* Non-Shared-Antenna TDMA */
1688 	{ {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1693 	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1698 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1703 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1708 	{ {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1717 	{0, 20, false, 7}, /* for WL-CPT */
1726 	{0, 20, false, 7}, /* for WL-CPT */
1737 	 11, 11, 12, 12, 12, 12, 12},
1739 	 11, 12, 12, 12, 12, 12, 12, 12},
1741 	 11, 12, 12, 12, 12, 12, 12},
1746 	 12, 12, 12, 12, 12, 12, 12},
1748 	 12, 12, 12, 12, 12, 12, 12, 12},
1750 	 11, 12, 12, 12, 12, 12, 12, 12},
1755 	 11, 11, 12, 12, 12, 12, 12},
1757 	 11, 12, 12, 12, 12, 12, 12, 12},
1759 	 11, 12, 12, 12, 12, 12, 12},
1764 	 12, 12, 12, 12, 12, 12, 12},
1766 	 12, 12, 12, 12, 12, 12, 12, 12},
1768 	 11, 12, 12, 12, 12, 12, 12, 12},
1843 	{0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1846 	{0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1847 	{0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1848 	{0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1849 	{0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1854 	{0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1882 	.lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),