Lines Matching +full:0 +full:x61
48 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
49 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
51 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
54 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
55 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
60 for (i = 0; i < 4; i++) in rtw8821c_read_efuse()
72 return 0; in rtw8821c_read_efuse()
76 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
77 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
78 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
79 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
84 u8 i = 0; in rtw8821c_get_swing_index()
87 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); in rtw8821c_get_swing_index()
88 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { in rtw8821c_get_swing_index()
108 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
109 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
119 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); in rtw8821c_phy_bf_init()
151 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
152 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); in rtw8821c_phy_set_param()
153 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); in rtw8821c_phy_set_param()
154 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
158 rtwdev->chip->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
163 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
179 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); in rtw8821c_mac_init()
195 rtw_write16(rtwdev, REG_TXPAUSE, 0); in rtw8821c_mac_init()
220 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); in rtw8821c_mac_init()
226 return 0; in rtw8821c_mac_init()
276 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8821c_set_channel_rf()
305 if (rtwdev->efuse.rfe_option == 0) in rtw8821c_set_channel_rf()
309 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
310 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); in rtw8821c_set_channel_rf()
313 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
316 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); in rtw8821c_set_channel_rf()
318 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
326 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
327 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
328 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
329 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
332 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
333 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
334 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
335 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
338 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
339 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
340 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
341 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
351 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
352 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
353 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
354 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8821c_set_channel_bb()
356 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); in rtw8821c_set_channel_bb()
357 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); in rtw8821c_set_channel_bb()
359 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); in rtw8821c_set_channel_bb()
360 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8821c_set_channel_bb()
361 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); in rtw8821c_set_channel_bb()
364 rtwdev->chip->ch_param[0]); in rtw8821c_set_channel_bb()
371 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
372 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
373 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
374 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8821c_set_channel_bb()
377 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); in rtw8821c_set_channel_bb()
379 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); in rtw8821c_set_channel_bb()
381 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); in rtw8821c_set_channel_bb()
384 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); in rtw8821c_set_channel_bb()
386 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); in rtw8821c_set_channel_bb()
388 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); in rtw8821c_set_channel_bb()
390 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); in rtw8821c_set_channel_bb()
397 val32 &= 0xffcffc00; in rtw8821c_set_channel_bb()
398 val32 |= 0x10010000; in rtw8821c_set_channel_bb()
401 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
410 val32 &= 0xff3ff300; in rtw8821c_set_channel_bb()
411 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | in rtw8821c_set_channel_bb()
415 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
419 val32 &= 0xfcffcf00; in rtw8821c_set_channel_bb()
420 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | in rtw8821c_set_channel_bb()
424 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
428 val32 &= 0xefcefc00; in rtw8821c_set_channel_bb()
429 val32 |= 0x200240; in rtw8821c_set_channel_bb()
432 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
433 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
437 val32 &= 0xefcefc00; in rtw8821c_set_channel_bb()
438 val32 |= 0x300380; in rtw8821c_set_channel_bb()
441 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
442 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
451 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; in rtw8821c_get_bb_swing()
456 tx_bb_swing = 0; in rtw8821c_get_bb_swing()
484 s8 rx_pwr_all = 0; in get_cck_rx_pwr()
485 s8 lna_gain = 0; in get_cck_rx_pwr()
487 if (efuse->rfe_option == 0) { in get_cck_rx_pwr()
510 u8 lna_idx = 0; in query_phy_status_page0()
511 u8 vga_idx = 0; in query_phy_status_page0()
556 page = *phy_status & 0xf; in query_phy_status()
559 case 0: in query_phy_status()
579 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8821c_query_rx_desc()
616 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; in rtw8821c_set_tx_power_index_by_rate()
621 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8821c_set_tx_power_index_by_rate()
624 shift = rate & 0x3; in rtw8821c_set_tx_power_index_by_rate()
626 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { in rtw8821c_set_tx_power_index_by_rate()
627 rate_idx = rate & 0xfc; in rtw8821c_set_tx_power_index_by_rate()
630 phy_pwr_idx = 0; in rtw8821c_set_tx_power_index_by_rate()
640 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
641 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { in rtw8821c_set_tx_power_index()
670 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
674 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
678 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
682 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
690 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
698 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
699 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
705 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; in rtw8821c_do_iqk()
715 for (counter = 0; counter < 300; counter++) { in rtw8821c_do_iqk()
717 if (rf_reg == 0xabcde) in rtw8821c_do_iqk()
721 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); in rtw8821c_do_iqk()
724 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); in rtw8821c_do_iqk()
726 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", in rtw8821c_do_iqk()
742 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8821c_coex_cfg_init()
771 u8 regval = 0; in rtw8821c_coex_cfg_ant_switch()
794 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
795 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
796 regval = 0x3; in rtw8821c_coex_cfg_ant_switch()
798 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
800 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
802 regval = (!polarity_inverse ? 0x1 : 0x2); in rtw8821c_coex_cfg_ant_switch()
815 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
828 regval = (!polarity_inverse ? 0x0 : 0x1); in rtw8821c_coex_cfg_ant_switch()
871 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
876 case 0: in rtw8821c_coex_cfg_rfe_type()
933 u8 swing_lower_bound = 0; in rtw8821c_txagc_swing_offset()
934 u8 max_pwr_idx_offset = 0xf; in rtw8821c_txagc_swing_offset()
935 s8 agc_index = 0; in rtw8821c_txagc_swing_offset()
941 if (delta_pwr_idx >= 0) { in rtw8821c_txagc_swing_offset()
951 } else if (delta_pwr_idx < 0) { in rtw8821c_txagc_swing_offset()
1006 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1019 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
1022 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8821c_phy_pwrtrack()
1057 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
1062 GENMASK(17, 16), 0x03); in rtw8821c_pwr_track()
1117 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", in rtw8821c_phy_cck_pd_set()
1125 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); in rtw8821c_phy_cck_pd_set()
1126 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, in rtw8821c_phy_cck_pd_set()
1131 {0x0086,
1135 RTW_PWR_CMD_WRITE, BIT(0), 0},
1136 {0x0086,
1141 {0x004A,
1145 RTW_PWR_CMD_WRITE, BIT(0), 0},
1146 {0x0005,
1150 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1151 {0x0300,
1155 RTW_PWR_CMD_WRITE, 0xFF, 0},
1156 {0x0301,
1160 RTW_PWR_CMD_WRITE, 0xFF, 0},
1161 {0xFFFF,
1164 0,
1165 RTW_PWR_CMD_END, 0, 0},
1169 {0x0020,
1173 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1174 {0x0001,
1179 {0x0000,
1183 RTW_PWR_CMD_WRITE, BIT(5), 0},
1184 {0x0005,
1188 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1189 {0x0075,
1193 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1194 {0x0006,
1199 {0x0075,
1203 RTW_PWR_CMD_WRITE, BIT(0), 0},
1204 {0x0006,
1208 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1209 {0x0005,
1213 RTW_PWR_CMD_WRITE, BIT(7), 0},
1214 {0x0005,
1218 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1219 {0x10C3,
1223 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1224 {0x0005,
1228 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1229 {0x0005,
1233 RTW_PWR_CMD_POLLING, BIT(0), 0},
1234 {0x0020,
1239 {0x0074,
1244 {0x0022,
1248 RTW_PWR_CMD_WRITE, BIT(1), 0},
1249 {0x0062,
1255 {0x0061,
1259 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1260 {0x007C,
1264 RTW_PWR_CMD_WRITE, BIT(1), 0},
1265 {0xFFFF,
1268 0,
1269 RTW_PWR_CMD_END, 0, 0},
1273 {0x0093,
1277 RTW_PWR_CMD_WRITE, BIT(3), 0},
1278 {0x001F,
1282 RTW_PWR_CMD_WRITE, 0xFF, 0},
1283 {0x0049,
1287 RTW_PWR_CMD_WRITE, BIT(1), 0},
1288 {0x0006,
1292 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1293 {0x0002,
1297 RTW_PWR_CMD_WRITE, BIT(1), 0},
1298 {0x10C3,
1302 RTW_PWR_CMD_WRITE, BIT(0), 0},
1303 {0x0005,
1308 {0x0005,
1312 RTW_PWR_CMD_POLLING, BIT(1), 0},
1313 {0x0020,
1317 RTW_PWR_CMD_WRITE, BIT(3), 0},
1318 {0x0000,
1323 {0xFFFF,
1326 0,
1327 RTW_PWR_CMD_END, 0, 0},
1331 {0x0007,
1335 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1336 {0x0067,
1340 RTW_PWR_CMD_WRITE, BIT(5), 0},
1341 {0x0005,
1346 {0x004A,
1350 RTW_PWR_CMD_WRITE, BIT(0), 0},
1351 {0x0067,
1355 RTW_PWR_CMD_WRITE, BIT(5), 0},
1356 {0x0067,
1360 RTW_PWR_CMD_WRITE, BIT(4), 0},
1361 {0x004F,
1365 RTW_PWR_CMD_WRITE, BIT(0), 0},
1366 {0x0067,
1370 RTW_PWR_CMD_WRITE, BIT(1), 0},
1371 {0x0046,
1376 {0x0067,
1380 RTW_PWR_CMD_WRITE, BIT(2), 0},
1381 {0x0046,
1386 {0x0062,
1391 {0x0081,
1395 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1396 {0x0005,
1401 {0x0086,
1405 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1406 {0x0086,
1410 RTW_PWR_CMD_POLLING, BIT(1), 0},
1411 {0x0090,
1415 RTW_PWR_CMD_WRITE, BIT(1), 0},
1416 {0x0044,
1420 RTW_PWR_CMD_WRITE, 0xFF, 0},
1421 {0x0040,
1425 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1426 {0x0041,
1430 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1431 {0x0042,
1435 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1436 {0xFFFF,
1439 0,
1440 RTW_PWR_CMD_END, 0, 0},
1456 {0xFFFF, 0x00,
1463 {0xFFFF, 0x0000,
1470 {0x0009, 0x6380,
1474 {0xFFFF, 0x0000,
1481 {0xFFFF, 0x0000,
1499 [0] = RTW_DEF_RFE(8821c, 0, 0),
1500 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1504 [0] = { .addr = 0xc50, .mask = 0x7f },
1514 /* not sure what [0] stands for */
1517 {16, 16, 0, 0, 1},
1518 {16, 16, 16, 0, 1},
1523 /* not sure what [0] stands for */
1591 {0x55555555, 0x55555555}, /* case-0 */
1592 {0x55555555, 0x55555555},
1593 {0x66555555, 0x66555555},
1594 {0xaaaaaaaa, 0xaaaaaaaa},
1595 {0x5a5a5a5a, 0x5a5a5a5a},
1596 {0xfafafafa, 0xfafafafa}, /* case-5 */
1597 {0x6a5a5555, 0xaaaaaaaa},
1598 {0x6a5a56aa, 0x6a5a56aa},
1599 {0x6a5a5a5a, 0x6a5a5a5a},
1600 {0x66555555, 0x5a5a5a5a},
1601 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1602 {0x66555555, 0xaaaaaaaa},
1603 {0x66555555, 0x6a5a5aaa},
1604 {0x66555555, 0x6aaa6aaa},
1605 {0x66555555, 0x6a5a5aaa},
1606 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1607 {0xffff55ff, 0xfafafafa},
1608 {0xffff55ff, 0x6afa5afa},
1609 {0xaaffffaa, 0xfafafafa},
1610 {0xaa5555aa, 0x5a5a5a5a},
1611 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1612 {0xaa5555aa, 0xaaaaaaaa},
1613 {0xffffffff, 0x55555555},
1614 {0xffffffff, 0x5a5a5a5a},
1615 {0xffffffff, 0x5a5a5a5a},
1616 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1617 {0x55555555, 0x5a5a5a5a},
1618 {0x55555555, 0xaaaaaaaa},
1619 {0x66555555, 0x6a5a6a5a},
1620 {0x66556655, 0x66556655},
1621 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1622 {0xffffffff, 0x5aaa5aaa},
1623 {0x56555555, 0x5a5a5aaa}
1628 {0xffffffff, 0xffffffff}, /* case-100 */
1629 {0xffff55ff, 0xfafafafa},
1630 {0x66555555, 0x66555555},
1631 {0xaaaaaaaa, 0xaaaaaaaa},
1632 {0x5a5a5a5a, 0x5a5a5a5a},
1633 {0xffffffff, 0xffffffff}, /* case-105 */
1634 {0x5afa5afa, 0x5afa5afa},
1635 {0x55555555, 0xfafafafa},
1636 {0x66555555, 0xfafafafa},
1637 {0x66555555, 0x5a5a5a5a},
1638 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1639 {0x66555555, 0xaaaaaaaa},
1640 {0xffff55ff, 0xfafafafa},
1641 {0xffff55ff, 0x5afa5afa},
1642 {0xffff55ff, 0xaaaaaaaa},
1643 {0xffff55ff, 0xffff55ff}, /* case-115 */
1644 {0xaaffffaa, 0x5afa5afa},
1645 {0xaaffffaa, 0xaaaaaaaa},
1646 {0xffffffff, 0xfafafafa},
1647 {0xffff55ff, 0xfafafafa},
1648 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1649 {0xffff55ff, 0x5afa5afa},
1650 {0xffff55ff, 0x5afa5afa},
1651 {0x55ff55ff, 0x55ff55ff}
1656 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1657 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1658 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1659 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1660 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1661 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1662 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1663 { {0x61, 0x35, 0x03, 0x11, 0x10} },
1664 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1665 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1666 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1667 { {0x61, 0x08, 0x03, 0x11, 0x15} },
1668 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1669 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1670 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1671 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1672 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1673 { {0x51, 0x3a, 0x03, 0x11, 0x50} },
1674 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1675 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1676 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1677 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1678 { {0x51, 0x08, 0x03, 0x30, 0x54} },
1679 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1680 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1681 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1682 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1683 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1688 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1689 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1690 { {0x61, 0x25, 0x03, 0x11, 0x11} },
1691 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1692 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1693 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1694 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1695 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1696 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1697 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1698 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1699 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1700 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1701 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1702 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1703 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1704 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1705 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1706 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1707 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1708 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1709 { {0x51, 0x10, 0x03, 0x10, 0x50} }
1712 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1716 {0, 0, false, 7}, /* for normal */
1717 {0, 20, false, 7}, /* for WL-CPT */
1725 {0, 0, false, 7}, /* for normal */
1726 {0, 20, false, 7}, /* for WL-CPT */
1730 {0, 28, true, 5}
1736 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1738 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1740 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1745 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1747 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1749 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1754 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1756 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1758 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1763 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1765 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1767 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1772 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1777 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1782 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1787 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1792 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1797 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1802 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1807 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1812 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1815 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1818 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1821 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1835 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1836 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1837 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1838 {0, 0, RTW_REG_DOMAIN_NL},
1839 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1840 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1841 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1842 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1843 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1844 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1845 {0, 0, RTW_REG_DOMAIN_NL},
1846 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1847 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1848 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1849 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1850 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1851 {0, 0, RTW_REG_DOMAIN_NL},
1852 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1853 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1854 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1855 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1856 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1875 .max_power_index = 0x3f,
1876 .csi_buf_pg_num = 0,
1879 .dig_min = 0x1c,
1883 .sys_func_en = 0xD8,
1891 .rf_base_addr = {0x2800, 0x2c00},
1892 .rf_sipi_addr = {0xc90, 0xe90},
1906 .coex_para_ver = 0x19092746,
1907 .bt_desired_ver = 0x46,
1928 .bt_afh_span_bw20 = 0x24,
1929 .bt_afh_span_bw40 = 0x36,