170 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_dig_write()  local
179 	for (path = 0; path < hal->rf_path_num; path++) {  in rtw_phy_dig_write()
573 	for (i = 0; i < rtwdev->hal.rf_path_num; i++) {  in rtw_phy_parsing_cfo_iter()
668 	if (rtwdev->hal.current_band_type != RTW_BAND_2G)  in rtw_phy_cck_pd()
837 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_read_rf()  local
842 	if (rf_path >= hal->rf_phy_num) {  in rtw_phy_read_rf()
860 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_read_rf_sipi()  local
869 	if (rf_path >= hal->rf_phy_num) {  in rtw_phy_read_rf_sipi()
909 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_write_rf_reg_sipi()  local
916 	if (rf_path >= hal->rf_phy_num) {  in rtw_phy_write_rf_reg_sipi()
949 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_write_rf_reg()  local
954 	if (rf_path >= hal->rf_phy_num) {  in rtw_phy_write_rf_reg()
982 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_setup_phy_cond()  local
986 	cond.cut = hal->cut_version ? hal->cut_version : 15;  in rtw_phy_setup_phy_cond()
1004 	hal->phy_cond = cond;  in rtw_phy_setup_phy_cond()
1006 	rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond));  in rtw_phy_setup_phy_cond()
1011 	struct rtw_hal *hal = &rtwdev->hal;  in check_positive()  local
1012 	struct rtw_phy_cond drv_cond = hal->phy_cond;  in check_positive()
1392 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_store_tx_power_by_rate()  local
1412 			hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;  in rtw_phy_store_tx_power_by_rate()
1414 			hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;  in rtw_phy_store_tx_power_by_rate()
1472 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_set_tx_power_limit()  local
1490 		hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;  in rtw_phy_set_tx_power_limit()
1491 		ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];  in rtw_phy_set_tx_power_limit()
1493 		hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;  in rtw_phy_set_tx_power_limit()
1495 		hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;  in rtw_phy_set_tx_power_limit()
1496 		ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];  in rtw_phy_set_tx_power_limit()
1498 		hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;  in rtw_phy_set_tx_power_limit()
1507 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_xref_5g_txpwr_lmt()  local
1509 	s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];  in rtw_xref_5g_txpwr_lmt()
1510 	s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];  in rtw_xref_5g_txpwr_lmt()
1516 		hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;  in rtw_xref_5g_txpwr_lmt()
1519 		hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;  in rtw_xref_5g_txpwr_lmt()
1659 	for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {  in rtw_phy_load_tables()
1894 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_get_tx_power_limit()  local
1895 	u8 *cch_by_bw = hal->cch_by_bw;  in rtw_phy_get_tx_power_limit()
1937 			hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :  in rtw_phy_get_tx_power_limit()
1938 			hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];  in rtw_phy_get_tx_power_limit()
1954 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_get_tx_power_params()  local
1972 		*offset = hal->tx_pwr_by_rate_offset_2g[path][rate];  in rtw_get_tx_power_params()
1978 		*offset = hal->tx_pwr_by_rate_offset_5g[path][rate];  in rtw_get_tx_power_params()
2016 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_set_tx_power_index_by_rs()  local
2030 	bw = hal->current_band_width;  in rtw_phy_set_tx_power_index_by_rs()
2035 		hal->tx_pwr_tbl[path][rate] = pwr_idx;  in rtw_phy_set_tx_power_index_by_rs()
2047 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_set_tx_power_level_by_path()  local
2051 	if (hal->current_band_type == RTW_BAND_2G)  in rtw_phy_set_tx_power_level_by_path()
2063 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_set_tx_power_level()  local
2066 	mutex_lock(&hal->tx_power_mutex);  in rtw_phy_set_tx_power_level()
2068 	for (path = 0; path < hal->rf_path_num; path++)  in rtw_phy_set_tx_power_level()
2072 	mutex_unlock(&hal->tx_power_mutex);  in rtw_phy_set_tx_power_level()
2077 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,  in rtw_phy_tx_power_by_rate_config_by_path()  argument
2088 	base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];  in rtw_phy_tx_power_by_rate_config_by_path()
2089 	base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];  in rtw_phy_tx_power_by_rate_config_by_path()
2090 	hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;  in rtw_phy_tx_power_by_rate_config_by_path()
2091 	hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;  in rtw_phy_tx_power_by_rate_config_by_path()
2094 		hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;  in rtw_phy_tx_power_by_rate_config_by_path()
2095 		hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;  in rtw_phy_tx_power_by_rate_config_by_path()
2099 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)  in rtw_phy_tx_power_by_rate_config()  argument
2104 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,  in rtw_phy_tx_power_by_rate_config()
2107 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,  in rtw_phy_tx_power_by_rate_config()
2110 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,  in rtw_phy_tx_power_by_rate_config()
2113 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,  in rtw_phy_tx_power_by_rate_config()
2116 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,  in rtw_phy_tx_power_by_rate_config()
2119 		rtw_phy_tx_power_by_rate_config_by_path(hal, path,  in rtw_phy_tx_power_by_rate_config()
2126 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)  in __rtw_phy_tx_power_limit_config()  argument
2132 		base = hal->tx_pwr_by_rate_base_2g[0][rs];  in __rtw_phy_tx_power_limit_config()
2133 		hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;  in __rtw_phy_tx_power_limit_config()
2137 		base = hal->tx_pwr_by_rate_base_5g[0][rs];  in __rtw_phy_tx_power_limit_config()
2138 		hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;  in __rtw_phy_tx_power_limit_config()
2142 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)  in rtw_phy_tx_power_limit_config()  argument
2147 	hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;  in rtw_phy_tx_power_limit_config()
2152 				__rtw_phy_tx_power_limit_config(hal, regd, bw, rs);  in rtw_phy_tx_power_limit_config()
2158 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_init_tx_power_limit()  local
2164 		hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;  in rtw_phy_init_tx_power_limit()
2168 		hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;  in rtw_phy_init_tx_power_limit()
2173 	struct rtw_hal *hal = &rtwdev->hal;  in rtw_phy_init_tx_power()  local
2179 			hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;  in rtw_phy_init_tx_power()
2180 			hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;  in rtw_phy_init_tx_power()
2196 	u8 channel = rtwdev->hal.current_channel;  in rtw_phy_config_swing_table()
2345 	chip->ops->config_tx_path(rtwdev, rtwdev->hal.antenna_tx,  in rtw_phy_set_tx_path_by_reg()
2376 	if (rtwdev->hal.antenna_rx != BB_PATH_AB) {  in rtw_phy_tx_path_diversity_2ss()
2379 			rtwdev->hal.antenna_tx, rtwdev->hal.antenna_rx);  in rtw_phy_tx_path_diversity_2ss()