Lines Matching full:31
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
47 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
67 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
87 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
101 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
105 #define MT_RXD6_TA_LO GENMASK(31, 16)
107 #define MT_RXD7_TA_HI GENMASK(31, 0)
110 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
112 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
124 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
127 #define MT_PRXV_RCPI3 GENMASK(31, 24)
141 #define MT_CRXV_HE_UPLINK BIT(31)
154 #define MT_CRXV_FOE_LO GENMASK(31, 19)
194 #define MT_TXD0_Q_IDX GENMASK(31, 25)
199 #define MT_TXD1_LONG_FORMAT BIT(31)
211 #define MT_TXD2_FIX_RATE BIT(31)
227 #define MT_TXD3_SN_VALID BIT(31)
241 #define MT_TXD4_PN_LOW GENMASK(31, 0)
243 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
251 #define MT_TXD6_TX_IBF BIT(31)
263 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
308 #define MT_TX_FREE_PAIR BIT(31)