Lines Matching +full:0 +full:- +full:31
1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
31 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
47 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
50 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
67 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
73 #define MT_RXD3_NORMAL_U2M BIT(0)
74 #define MT_RXD3_NORMAL_HTC_VLD BIT(0)
87 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
90 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
91 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
93 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
101 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
104 #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)
105 #define MT_RXD6_TA_LO GENMASK(31, 16)
107 #define MT_RXD7_TA_HI GENMASK(31, 0)
109 #define MT_RXD8_SEQ_CTRL GENMASK(15, 0)
110 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
112 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
114 /* P-RXV DW0 */
115 #define MT_PRXV_TX_RATE GENMASK(6, 0)
124 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
126 /* P-RXV DW1 */
127 #define MT_PRXV_RCPI3 GENMASK(31, 24)
130 #define MT_PRXV_RCPI0 GENMASK(7, 0)
131 #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
133 /* C-RXV */
134 #define MT_CRXV_HT_STBC GENMASK(1, 0)
141 #define MT_CRXV_HE_UPLINK BIT(31)
148 #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
154 #define MT_CRXV_FOE_LO GENMASK(31, 19)
155 #define MT_CRXV_FOE_HI GENMASK(6, 0)
178 MT_TX_MCU_PORT_RX_Q0 = 0x20,
182 MT_TX_MCU_PORT_RX_FWDL = 0x3e
185 #define MT_CT_INFO_APPLY_TXD BIT(0)
194 #define MT_TXD0_Q_IDX GENMASK(31, 25)
197 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
199 #define MT_TXD1_LONG_FORMAT BIT(31)
209 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
211 #define MT_TXD2_FIX_RATE BIT(31)
225 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
227 #define MT_TXD3_SN_VALID BIT(31)
239 #define MT_TXD3_NO_ACK BIT(0)
241 #define MT_TXD4_PN_LOW GENMASK(31, 0)
243 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
249 #define MT_TXD5_PID GENMASK(7, 0)
251 #define MT_TXD6_TX_IBF BIT(31)
261 #define MT_TXD6_BW GENMASK(1, 0)
263 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
273 #define MT_TXD7_TX_TIME GENMASK(9, 0)
280 #define MT_TX_RATE_IDX GENMASK(3, 0)
302 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
304 #define MT_TX_FREE_LATENCY GENMASK(12, 0)
305 /* 0: success, others: dropped */
308 #define MT_TX_FREE_PAIR BIT(31)
310 #define MT_TX_FREE_RATE GENMASK(13, 0)
330 #define MT_TXD_LEN_MASK GENMASK(11, 0)