Lines Matching full:31
11 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
45 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
65 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
85 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
100 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
106 #define MT_RXD6_TA_LO GENMASK(31, 16)
108 #define MT_RXD7_TA_HI GENMASK(31, 0)
111 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
113 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
121 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
123 #define MT_PRXV_RCPI3 GENMASK(31, 24)
136 #define MT_CRXV_HE_UPLINK BIT(31)
149 #define MT_CRXV_FOE_LO GENMASK(31, 19)
189 #define MT_TXD0_Q_IDX GENMASK(31, 25)
194 #define MT_TXD1_LONG_FORMAT BIT(31)
206 #define MT_TXD2_FIX_RATE BIT(31)
222 #define MT_TXD3_SN_VALID BIT(31)
236 #define MT_TXD4_PN_LOW GENMASK(31, 0)
238 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
246 #define MT_TXD6_TX_IBF BIT(31)
258 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
303 #define MT_TX_FREE_PAIR BIT(31)
307 #define MT_TXS0_FIXED_RATE BIT(31)
326 #define MT_TXS1_SEQNO GENMASK(31, 20)
331 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
337 #define MT_TXS3_PID GENMASK(31, 24)
340 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
342 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
346 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
349 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
353 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
356 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
360 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)