Lines Matching +full:24 +full:- +full:bit
1 /* SPDX-License-Identifier: ISC */
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
37 #define MT_RXD1_NORMAL_CM BIT(23)
38 #define MT_RXD1_NORMAL_CLM BIT(24)
39 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
40 #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
41 #define MT_RXD1_NORMAL_FCS_ERR BIT(27)
42 #define MT_RXD1_NORMAL_BAND_IDX BIT(28)
43 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
44 #define MT_RXD1_NORMAL_ADD_OM BIT(30)
45 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
49 #define MT_RXD2_NORMAL_CO_ANT BIT(6)
50 #define MT_RXD2_NORMAL_BF_CQI BIT(7)
52 #define MT_RXD2_NORMAL_HDR_TRANS BIT(13)
55 #define MT_RXD2_NORMAL_MU_BAR BIT(21)
56 #define MT_RXD2_NORMAL_SW_BIT BIT(22)
57 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
58 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
59 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
60 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
61 #define MT_RXD2_NORMAL_FRAG BIT(27)
62 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
63 #define MT_RXD2_NORMAL_NDATA BIT(29)
64 #define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
65 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
71 #define MT_RXD3_NORMAL_U2M BIT(0)
72 #define MT_RXD3_NORMAL_HTC_VLD BIT(0)
73 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19)
74 #define MT_RXD3_NORMAL_BEACON_MC BIT(20)
75 #define MT_RXD3_NORMAL_BEACON_UC BIT(21)
76 #define MT_RXD3_NORMAL_AMSDU BIT(22)
77 #define MT_RXD3_NORMAL_MESH BIT(23)
78 #define MT_RXD3_NORMAL_MHCP BIT(24)
79 #define MT_RXD3_NORMAL_NO_INFO_WB BIT(25)
80 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26)
81 #define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27)
82 #define MT_RXD3_NORMAL_MORE BIT(28)
83 #define MT_RXD3_NORMAL_UNWANT BIT(29)
84 #define MT_RXD3_NORMAL_RX_DROP BIT(30)
85 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
90 #define MT_RXD4_MID_AMSDU_FRAME BIT(1)
91 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
93 #define MT_RXD4_NORMAL_PATTERN_DROP BIT(9)
94 #define MT_RXD4_NORMAL_CLS BIT(10)
96 #define MT_RXD4_NORMAL_MAGIC_PKT BIT(13)
99 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
102 #define MT_RXV_HDR_BAND_IDX BIT(24)
115 /* P-RXV */
117 #define MT_PRXV_TX_DCM BIT(4)
118 #define MT_PRXV_TX_ER_SU_106T BIT(5)
120 #define MT_PRXV_HT_AD_CODE BIT(11)
123 #define MT_PRXV_RCPI3 GENMASK(31, 24)
128 /* C-RXV */
134 #define MT_CRXV_HE_LDPC_EXT_SYM BIT(20)
135 #define MT_CRXV_HE_PE_DISAMBIG BIT(23)
136 #define MT_CRXV_HE_UPLINK BIT(31)
141 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
145 #define MT_CRXV_HE_BEAM_CHNG BIT(13)
146 #define MT_CRXV_HE_DOPPLER BIT(16)
180 #define MT_CT_INFO_APPLY_TXD BIT(0)
181 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
182 #define MT_CT_INFO_MGMT_FRAME BIT(2)
183 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
184 #define MT_CT_INFO_HSR2_TX BIT(4)
185 #define MT_CT_INFO_FROM_HOST BIT(7)
190 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
194 #define MT_TXD1_LONG_FORMAT BIT(31)
195 #define MT_TXD1_TGID BIT(30)
196 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
197 #define MT_TXD1_AMSDU BIT(23)
202 #define MT_TXD1_ETH_802_3 BIT(15)
203 #define MT_TXD1_VTA BIT(10)
206 #define MT_TXD2_FIX_RATE BIT(31)
207 #define MT_TXD2_FIXED_RATE BIT(30)
208 #define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
211 #define MT_TXD2_HTC_VLD BIT(13)
212 #define MT_TXD2_DURATION BIT(12)
213 #define MT_TXD2_BIP BIT(11)
214 #define MT_TXD2_MULTICAST BIT(10)
215 #define MT_TXD2_RTS BIT(9)
216 #define MT_TXD2_SOUNDING BIT(8)
217 #define MT_TXD2_NDPA BIT(7)
218 #define MT_TXD2_NDP BIT(6)
222 #define MT_TXD3_SN_VALID BIT(31)
223 #define MT_TXD3_PN_VALID BIT(30)
224 #define MT_TXD3_SW_POWER_MGMT BIT(29)
225 #define MT_TXD3_BA_DISABLE BIT(28)
229 #define MT_TXD3_TIMING_MEASURE BIT(5)
230 #define MT_TXD3_DAS BIT(4)
231 #define MT_TXD3_EEOSP BIT(3)
232 #define MT_TXD3_EMRD BIT(2)
233 #define MT_TXD3_PROTECT_FRAME BIT(1)
234 #define MT_TXD3_NO_ACK BIT(0)
239 #define MT_TXD5_MD BIT(15)
240 #define MT_TXD5_ADD_BA BIT(14)
241 #define MT_TXD5_TX_STATUS_HOST BIT(10)
242 #define MT_TXD5_TX_STATUS_MCU BIT(9)
243 #define MT_TXD5_TX_STATUS_FMT BIT(8)
246 #define MT_TXD6_TX_IBF BIT(31)
247 #define MT_TXD6_TX_EBF BIT(30)
251 #define MT_TXD6_LDPC BIT(11)
252 #define MT_TXD6_SPE_ID_IDX BIT(10)
254 #define MT_TXD6_DYN_BW BIT(3)
255 #define MT_TXD6_FIXED_BW BIT(2)
259 #define MT_TXD7_UDP_TCP_SUM BIT(29)
260 #define MT_TXD7_IP_SUM BIT(28)
267 #define MT_TXD7_HW_AMSDU BIT(10)
270 #define MT_TX_RATE_STBC BIT(13)
273 #define MT_TX_RATE_SU_EXT_TONE BIT(5)
274 #define MT_TX_RATE_DCM BIT(4)
303 #define MT_TX_FREE_PAIR BIT(31)
307 #define MT_TXS0_FIXED_RATE BIT(31)
310 #define MT_TXS0_AMPDU BIT(25)
311 #define MT_TXS0_TXS_FORMAT GENMASK(24, 23)
312 #define MT_TXS0_BA_ERROR BIT(22)
313 #define MT_TXS0_PS_FLAG BIT(21)
314 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
315 #define MT_TXS0_BIP_ERROR BIT(19)
317 #define MT_TXS0_QUEUE_TIMEOUT BIT(18)
318 #define MT_TXS0_RTS_TIMEOUT BIT(17)
319 #define MT_TXS0_ACK_TIMEOUT BIT(16)
322 #define MT_TXS0_TX_STATUS_HOST BIT(15)
323 #define MT_TXS0_TX_STATUS_MCU BIT(14)
333 #define MT_TXS2_SHARED_ANTENNA BIT(26)
337 #define MT_TXS3_PID GENMASK(31, 24)
342 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
343 #define MT_TXS5_F0_QOS BIT(30)
345 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
346 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
349 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
353 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
356 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
360 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)