Lines Matching +full:0 +full:- +full:31
1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
29 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
45 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
48 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
65 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
68 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
71 #define MT_RXD3_NORMAL_U2M BIT(0)
72 #define MT_RXD3_NORMAL_HTC_VLD BIT(0)
85 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
88 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
89 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
91 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
100 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
105 #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)
106 #define MT_RXD6_TA_LO GENMASK(31, 16)
108 #define MT_RXD7_TA_HI GENMASK(31, 0)
110 #define MT_RXD8_SEQ_CTRL GENMASK(15, 0)
111 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
113 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
115 /* P-RXV */
116 #define MT_PRXV_TX_RATE GENMASK(6, 0)
121 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
122 #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
123 #define MT_PRXV_RCPI3 GENMASK(31, 24)
126 #define MT_PRXV_RCPI0 GENMASK(7, 0)
128 /* C-RXV */
129 #define MT_CRXV_HT_STBC GENMASK(1, 0)
136 #define MT_CRXV_HE_UPLINK BIT(31)
143 #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
149 #define MT_CRXV_FOE_LO GENMASK(31, 19)
150 #define MT_CRXV_FOE_HI GENMASK(6, 0)
173 MT_TX_MCU_PORT_RX_Q0 = 0x20,
177 MT_TX_MCU_PORT_RX_FWDL = 0x3e
180 #define MT_CT_INFO_APPLY_TXD BIT(0)
189 #define MT_TXD0_Q_IDX GENMASK(31, 25)
192 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
194 #define MT_TXD1_LONG_FORMAT BIT(31)
204 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
206 #define MT_TXD2_FIX_RATE BIT(31)
220 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
222 #define MT_TXD3_SN_VALID BIT(31)
234 #define MT_TXD3_NO_ACK BIT(0)
236 #define MT_TXD4_PN_LOW GENMASK(31, 0)
238 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
244 #define MT_TXD5_PID GENMASK(7, 0)
246 #define MT_TXD6_TX_IBF BIT(31)
256 #define MT_TXD6_BW GENMASK(1, 0)
258 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
268 #define MT_TXD7_TX_TIME GENMASK(9, 0)
275 #define MT_TX_RATE_IDX GENMASK(3, 0)
297 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
299 #define MT_TX_FREE_LATENCY GENMASK(12, 0)
300 /* 0: success, others: dropped */
303 #define MT_TX_FREE_PAIR BIT(31)
305 #define MT_TX_FREE_RATE GENMASK(13, 0)
307 #define MT_TXS0_FIXED_RATE BIT(31)
324 #define MT_TXS0_TX_RATE GENMASK(13, 0)
326 #define MT_TXS1_SEQNO GENMASK(31, 20)
329 #define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)
331 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
335 #define MT_TXS2_TX_DELAY GENMASK(15, 0)
337 #define MT_TXS3_PID GENMASK(31, 24)
338 #define MT_TXS3_ANT_ID GENMASK(23, 0)
340 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
342 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
345 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
346 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
347 #define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)
349 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
352 #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)
353 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
354 #define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)
356 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
359 #define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)
360 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)
361 #define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)