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142 #define MT_AGC_41_RSSI_0 GENMASK(23, 16)
249 #define MT_DMA_FQCR0_DEST_PORT_ID GENMASK(23, 22)
361 #define MT_TMAC_TCR_RX_RIFS_MODE BIT(23)
398 #define MT_TMAC_PCR_SPE_EN BIT(23)
481 #define MT_WTBL_RMVTCR_RX_MV_MODE BIT(23)
501 #define MT_TBTT_DTIM_PERIOD GENMASK(23, 16)
530 #define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12)
556 #define MT_MIB_STAT_CCA_MASK GENMASK(23, 0)
559 #define MT_MIB_STAT_PSCCA_MASK GENMASK(23, 0)
564 #define MT_MIB_STAT_ED_MASK GENMASK(23, 0)
589 #define MT_LED_STATUS_ON GENMASK(23, 16)
640 #define MT_WTBL1_W0_KEY_IDX GENMASK(24, 23)
667 #define MT_WTBL1_W2_ITXBF BIT(23)
689 #define MT_WTBL1_W4_PARTIAL_AID GENMASK(31, 23)
697 #define MT_WTBL2_W2_TID1_SN GENMASK(23, 12)
714 #define MT_WTBL2_W6_TX_COUNT_RATE4 GENMASK(23, 16)
733 #define MT_WTBL2_W9_MPDU_FAIL_COUNT GENMASK(25, 23)
738 #define MT_WTBL2_W10_RATE2 GENMASK(23, 12)
752 #define MT_WTBL2_W13_AVG_RCPI2 GENAMSK(23, 16)