Lines Matching +full:cmdq +full:- +full:sync
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2007-2015, 2018-2020 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
24 #include "fw/error-dump.h"
28 #include "iwl-fh.h"
29 #include "iwl-context-info-gen3.h"
42 struct pci_dev *pdev = trans_pcie->pci_dev; in iwl_trans_pcie_dump_regs()
46 if (trans_pcie->pcie_dbg_dumped_once) in iwl_trans_pcie_dump_regs()
63 prefix = (char *)buf + alloc_size - PREFIX_LEN; in iwl_trans_pcie_dump_regs()
91 if (!pdev->bus->self) in iwl_trans_pcie_dump_regs()
94 pdev = pdev->bus->self; in iwl_trans_pcie_dump_regs()
125 trans_pcie->pcie_dbg_dumped_once = 1; in iwl_trans_pcie_dump_regs()
131 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ in iwl_trans_pcie_sw_reset()
138 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_free_fw_monitor()
140 if (!fw_mon->size) in iwl_pcie_free_fw_monitor()
143 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, in iwl_pcie_free_fw_monitor()
144 fw_mon->physical); in iwl_pcie_free_fw_monitor()
146 fw_mon->block = NULL; in iwl_pcie_free_fw_monitor()
147 fw_mon->physical = 0; in iwl_pcie_free_fw_monitor()
148 fw_mon->size = 0; in iwl_pcie_free_fw_monitor()
154 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_alloc_fw_monitor_block()
160 if (fw_mon->size) in iwl_pcie_alloc_fw_monitor_block()
163 for (power = max_power; power >= min_power; power--) { in iwl_pcie_alloc_fw_monitor_block()
165 block = dma_alloc_coherent(trans->dev, size, &physical, in iwl_pcie_alloc_fw_monitor_block()
181 "Sorry - debug buffer is only %luK while you requested %luK\n", in iwl_pcie_alloc_fw_monitor_block()
182 (unsigned long)BIT(power - 10), in iwl_pcie_alloc_fw_monitor_block()
183 (unsigned long)BIT(max_power - 10)); in iwl_pcie_alloc_fw_monitor_block()
185 fw_mon->block = block; in iwl_pcie_alloc_fw_monitor_block()
186 fw_mon->physical = physical; in iwl_pcie_alloc_fw_monitor_block()
187 fw_mon->size = size; in iwl_pcie_alloc_fw_monitor_block()
204 if (trans->dbg.fw_mon.size) in iwl_pcie_alloc_fw_monitor()
226 if (trans->cfg->apmg_not_supported) in iwl_pcie_set_pwr()
229 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
255 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); in iwl_pcie_apm_config()
256 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
258 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); in iwl_pcie_apm_config()
259 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
260 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
262 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
282 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
298 * wake device's PCI Express link L1a -> L0s in iwl_pcie_apm_init()
305 /* Configure analog phase-lock-loop before activating to D0A */ in iwl_pcie_apm_init()
306 if (trans->trans_cfg->base_params->pll_cfg) in iwl_pcie_apm_init()
309 ret = iwl_finish_nic_init(trans, trans->trans_cfg); in iwl_pcie_apm_init()
313 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
315 * This is a bit of an abuse - This is needed for 7260 / 3160 in iwl_pcie_apm_init()
320 * consumes slightly more power (100uA) - but allows to be sure in iwl_pcie_apm_init()
342 if (!trans->cfg->apmg_not_supported) { in iwl_pcie_apm_init()
347 /* Disable L1-Active */ in iwl_pcie_apm_init()
356 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
381 ret = iwl_finish_nic_init(trans, trans->trans_cfg); in iwl_pcie_apm_lp_xtal_enable()
428 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. in iwl_pcie_apm_lp_xtal_enable()
453 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_apm_stop_master()
480 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
484 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
487 else if (trans->trans_cfg->device_family >= in iwl_pcie_apm_stop()
501 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
506 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
515 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. in iwl_pcie_apm_stop()
526 spin_lock_bh(&trans_pcie->irq_lock); in iwl_pcie_nic_init()
528 spin_unlock_bh(&trans_pcie->irq_lock); in iwl_pcie_nic_init()
535 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
545 return -ENOMEM; in iwl_pcie_nic_init()
548 if (trans->trans_cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
580 /* Note: returns standard 0/-ERROR code */
657 trans_pcie->ucode_write_complete = false; in iwl_pcie_load_firmware_chunk()
660 return -EIO; in iwl_pcie_load_firmware_chunk()
666 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, in iwl_pcie_load_firmware_chunk()
667 trans_pcie->ucode_write_complete, 5 * HZ); in iwl_pcie_load_firmware_chunk()
671 return -ETIMEDOUT; in iwl_pcie_load_firmware_chunk()
682 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); in iwl_pcie_load_section()
688 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
693 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
696 return -ENOMEM; in iwl_pcie_load_section()
699 for (offset = 0; offset < section->len; offset += chunk_sz) { in iwl_pcie_load_section()
703 copy_size = min_t(u32, chunk_sz, section->len - offset); in iwl_pcie_load_section()
704 dst_addr = section->offset + offset; in iwl_pcie_load_section()
714 memcpy(v_addr, (u8 *)section->data + offset, copy_size); in iwl_pcie_load_section()
730 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
751 for (i = *first_ucode_section; i < image->num_sec; i++) { in iwl_pcie_load_cpu_sections_8000()
755 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections_8000()
757 * PAGING_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections_8000()
760 if (!image->sec[i].data || in iwl_pcie_load_cpu_sections_8000()
761 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || in iwl_pcie_load_cpu_sections_8000()
762 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { in iwl_pcie_load_cpu_sections_8000()
769 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
785 if (trans->trans_cfg->use_tfh) { in iwl_pcie_load_cpu_sections_8000()
817 for (i = *first_ucode_section; i < image->num_sec; i++) { in iwl_pcie_load_cpu_sections()
821 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections()
823 * PAGING_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections()
826 if (!image->sec[i].data || in iwl_pcie_load_cpu_sections()
827 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || in iwl_pcie_load_cpu_sections()
828 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { in iwl_pcie_load_cpu_sections()
835 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
849 &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_apply_destination_ini()
855 if (le32_to_cpu(fw_mon_cfg->buf_location) == in iwl_pcie_apply_destination_ini()
865 if (le32_to_cpu(fw_mon_cfg->buf_location) != in iwl_pcie_apply_destination_ini()
867 !trans->dbg.fw_mon_ini[alloc_id].num_frags) in iwl_pcie_apply_destination_ini()
870 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_apply_destination_ini()
876 frag->physical >> MON_BUFF_SHIFT_VER2); in iwl_pcie_apply_destination_ini()
878 (frag->physical + frag->size - 256) >> in iwl_pcie_apply_destination_ini()
884 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; in iwl_pcie_apply_destination()
885 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_apply_destination()
894 get_fw_dbg_mode_string(dest->monitor_mode)); in iwl_pcie_apply_destination()
896 if (dest->monitor_mode == EXTERNAL_MODE) in iwl_pcie_apply_destination()
897 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); in iwl_pcie_apply_destination()
901 for (i = 0; i < trans->dbg.n_dest_reg; i++) { in iwl_pcie_apply_destination()
902 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); in iwl_pcie_apply_destination()
903 u32 val = le32_to_cpu(dest->reg_ops[i].val); in iwl_pcie_apply_destination()
905 switch (dest->reg_ops[i].op) { in iwl_pcie_apply_destination()
933 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
934 dest->reg_ops[i].op); in iwl_pcie_apply_destination()
940 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { in iwl_pcie_apply_destination()
941 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
942 fw_mon->physical >> dest->base_shift); in iwl_pcie_apply_destination()
943 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
944 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
945 (fw_mon->physical + fw_mon->size - in iwl_pcie_apply_destination()
946 256) >> dest->end_shift); in iwl_pcie_apply_destination()
948 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
949 (fw_mon->physical + fw_mon->size) >> in iwl_pcie_apply_destination()
950 dest->end_shift); in iwl_pcie_apply_destination()
961 image->is_dual_cpus ? "Dual" : "Single"); in iwl_pcie_load_given_ucode()
968 if (image->is_dual_cpus) { in iwl_pcie_load_given_ucode()
999 image->is_dual_cpus ? "Dual" : "Single"); in iwl_pcie_load_given_ucode_8000()
1033 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1037 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1038 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1040 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1041 if (trans_pcie->opmode_down) in iwl_pcie_check_hw_rf_kill()
1042 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1045 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1080 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; in iwl_pcie_map_non_rx_causes()
1087 * the first interrupt vector will serve non-RX and FBQ causes. in iwl_pcie_map_non_rx_causes()
1100 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; in iwl_pcie_map_rx_causes()
1104 * The first RX queue - fallback queue, which is designated for in iwl_pcie_map_rx_causes()
1107 * the other (N - 2) interrupt vectors. in iwl_pcie_map_rx_causes()
1110 for (idx = 1; idx < trans->num_rx_queues; idx++) { in iwl_pcie_map_rx_causes()
1112 MSIX_FH_INT_CAUSES_Q(idx - offset)); in iwl_pcie_map_rx_causes()
1118 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) in iwl_pcie_map_rx_causes()
1122 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) in iwl_pcie_map_rx_causes()
1128 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_conf_msix_hw()
1130 if (!trans_pcie->msix_enabled) { in iwl_pcie_conf_msix_hw()
1131 if (trans->trans_cfg->mq_rx_supported && in iwl_pcie_conf_msix_hw()
1132 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1142 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1159 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_init_msix()
1163 if (!trans_pcie->msix_enabled) in iwl_pcie_init_msix()
1166 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); in iwl_pcie_init_msix()
1167 trans_pcie->fh_mask = trans_pcie->fh_init_mask; in iwl_pcie_init_msix()
1168 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); in iwl_pcie_init_msix()
1169 trans_pcie->hw_mask = trans_pcie->hw_init_mask; in iwl_pcie_init_msix()
1176 lockdep_assert_held(&trans_pcie->mutex); in _iwl_trans_pcie_stop_device()
1178 if (trans_pcie->is_down) in _iwl_trans_pcie_stop_device()
1181 trans_pcie->is_down = true; in _iwl_trans_pcie_stop_device()
1196 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in _iwl_trans_pcie_stop_device()
1202 /* Power-down device's busmaster DMA clocks */ in _iwl_trans_pcie_stop_device()
1203 if (!trans->cfg->apmg_not_supported) { in _iwl_trans_pcie_stop_device()
1220 * Upon stop, the IVAR table gets erased, so msi-x won't in _iwl_trans_pcie_stop_device()
1221 * work. This causes a bug in RF-KILL flows, since the interrupt in _iwl_trans_pcie_stop_device()
1233 * should be masked. Re-ACK all the interrupts here. in _iwl_trans_pcie_stop_device()
1238 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in _iwl_trans_pcie_stop_device()
1239 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_trans_pcie_stop_device()
1240 clear_bit(STATUS_TPOWER_PMI, &trans->status); in _iwl_trans_pcie_stop_device()
1248 /* re-take ownership to prevent other users from stealing the device */ in _iwl_trans_pcie_stop_device()
1256 if (trans_pcie->msix_enabled) { in iwl_pcie_synchronize_irqs()
1259 for (i = 0; i < trans_pcie->alloc_vecs; i++) in iwl_pcie_synchronize_irqs()
1260 synchronize_irq(trans_pcie->msix_entries[i].vector); in iwl_pcie_synchronize_irqs()
1262 synchronize_irq(trans_pcie->pci_dev->irq); in iwl_pcie_synchronize_irqs()
1276 ret = -EIO; in iwl_trans_pcie_start_fw()
1285 * We enabled the RF-Kill interrupt and the handler may very in iwl_trans_pcie_start_fw()
1294 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_start_fw()
1299 ret = -ERFKILL; in iwl_trans_pcie_start_fw()
1304 if (trans_pcie->is_down) { in iwl_trans_pcie_start_fw()
1307 ret = -EIO; in iwl_trans_pcie_start_fw()
1327 * by the RF-Kill interrupt (hence mask all the interrupt besides the in iwl_trans_pcie_start_fw()
1329 * RF-Kill switch is toggled, we will find out after having loaded in iwl_trans_pcie_start_fw()
1339 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1344 /* re-check RF-Kill state since we may have missed the interrupt */ in iwl_trans_pcie_start_fw()
1347 ret = -ERFKILL; in iwl_trans_pcie_start_fw()
1350 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_start_fw()
1379 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1380 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1382 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1383 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1394 iwl_op_mode_time_point(trans->op_mode, in iwl_trans_pcie_stop_device()
1398 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_stop_device()
1399 trans_pcie->opmode_down = true; in iwl_trans_pcie_stop_device()
1400 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_stop_device()
1403 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_stop_device()
1411 lockdep_assert_held(&trans_pcie->mutex); in iwl_trans_pcie_rf_kill()
1415 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { in iwl_trans_pcie_rf_kill()
1416 if (trans->trans_cfg->gen2) in iwl_trans_pcie_rf_kill()
1445 * reset TX queues -- some of their registers reset during S3 in iwl_pcie_d3_complete_suspend()
1466 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_d3_suspend()
1470 ret = wait_event_timeout(trans_pcie->sx_waitq, in iwl_trans_pcie_d3_suspend()
1471 trans_pcie->sx_complete, 2 * HZ); in iwl_trans_pcie_d3_suspend()
1475 trans_pcie->sx_complete = false; in iwl_trans_pcie_d3_suspend()
1479 return -ETIMEDOUT; in iwl_trans_pcie_d3_suspend()
1504 ret = iwl_finish_nic_init(trans, trans->trans_cfg); in iwl_trans_pcie_d3_resume()
1511 * Also enables interrupts - none will happen as in iwl_trans_pcie_d3_resume()
1516 if (!trans_pcie->msix_enabled) in iwl_trans_pcie_d3_resume()
1547 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_d3_resume()
1548 trans_pcie->sx_complete = false; in iwl_trans_pcie_d3_resume()
1552 ret = wait_event_timeout(trans_pcie->sx_waitq, in iwl_trans_pcie_d3_resume()
1553 trans_pcie->sx_complete, 2 * HZ); in iwl_trans_pcie_d3_resume()
1557 trans_pcie->sx_complete = false; in iwl_trans_pcie_d3_resume()
1561 return -ETIMEDOUT; in iwl_trans_pcie_d3_resume()
1577 if (!cfg_trans->mq_rx_supported) in iwl_pcie_set_interrupt_capa()
1580 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) in iwl_pcie_set_interrupt_capa()
1585 trans_pcie->msix_entries[i].entry = i; in iwl_pcie_set_interrupt_capa()
1587 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, in iwl_pcie_set_interrupt_capa()
1592 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", in iwl_pcie_set_interrupt_capa()
1596 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; in iwl_pcie_set_interrupt_capa()
1599 "MSI-X enabled. %d interrupt vectors were allocated\n", in iwl_pcie_set_interrupt_capa()
1609 if (num_irqs <= max_irqs - 2) { in iwl_pcie_set_interrupt_capa()
1610 trans_pcie->trans->num_rx_queues = num_irqs + 1; in iwl_pcie_set_interrupt_capa()
1611 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | in iwl_pcie_set_interrupt_capa()
1613 } else if (num_irqs == max_irqs - 1) { in iwl_pcie_set_interrupt_capa()
1614 trans_pcie->trans->num_rx_queues = num_irqs; in iwl_pcie_set_interrupt_capa()
1615 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; in iwl_pcie_set_interrupt_capa()
1617 trans_pcie->trans->num_rx_queues = num_irqs - 1; in iwl_pcie_set_interrupt_capa()
1621 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", in iwl_pcie_set_interrupt_capa()
1622 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); in iwl_pcie_set_interrupt_capa()
1624 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); in iwl_pcie_set_interrupt_capa()
1626 trans_pcie->alloc_vecs = num_irqs; in iwl_pcie_set_interrupt_capa()
1627 trans_pcie->msix_enabled = true; in iwl_pcie_set_interrupt_capa()
1633 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); in iwl_pcie_set_interrupt_capa()
1648 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; in iwl_pcie_irq_set_affinity()
1649 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; in iwl_pcie_irq_set_affinity()
1654 * (i.e. return will be > i - 1). in iwl_pcie_irq_set_affinity()
1656 cpu = cpumask_next(i - offset, cpu_online_mask); in iwl_pcie_irq_set_affinity()
1657 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); in iwl_pcie_irq_set_affinity()
1658 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, in iwl_pcie_irq_set_affinity()
1659 &trans_pcie->affinity_mask[i]); in iwl_pcie_irq_set_affinity()
1661 IWL_ERR(trans_pcie->trans, in iwl_pcie_irq_set_affinity()
1663 trans_pcie->msix_entries[i].vector); in iwl_pcie_irq_set_affinity()
1672 for (i = 0; i < trans_pcie->alloc_vecs; i++) { in iwl_pcie_init_msix_handler()
1675 const char *qname = queue_name(&pdev->dev, trans_pcie, i); in iwl_pcie_init_msix_handler()
1678 return -ENOMEM; in iwl_pcie_init_msix_handler()
1680 msix_entry = &trans_pcie->msix_entries[i]; in iwl_pcie_init_msix_handler()
1681 ret = devm_request_threaded_irq(&pdev->dev, in iwl_pcie_init_msix_handler()
1682 msix_entry->vector, in iwl_pcie_init_msix_handler()
1684 (i == trans_pcie->def_irq) ? in iwl_pcie_init_msix_handler()
1691 IWL_ERR(trans_pcie->trans, in iwl_pcie_init_msix_handler()
1697 iwl_pcie_irq_set_affinity(trans_pcie->trans); in iwl_pcie_init_msix_handler()
1706 switch (trans->trans_cfg->device_family) { in iwl_trans_pcie_clear_persistence_bit()
1724 return -EPERM; in iwl_trans_pcie_clear_persistence_bit()
1737 ret = iwl_finish_nic_init(trans, trans->trans_cfg); in iwl_pcie_gen2_force_power_gating()
1761 lockdep_assert_held(&trans_pcie->mutex); in _iwl_trans_pcie_start_hw()
1775 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && in _iwl_trans_pcie_start_hw()
1776 trans->trans_cfg->integrated) { in _iwl_trans_pcie_start_hw()
1791 trans_pcie->opmode_down = false; in _iwl_trans_pcie_start_hw()
1794 trans_pcie->is_down = false; in _iwl_trans_pcie_start_hw()
1807 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_start_hw()
1809 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_start_hw()
1818 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_op_mode_leave()
1820 /* disable interrupts - don't enable HW RF kill interrupt */ in iwl_trans_pcie_op_mode_leave()
1829 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_op_mode_leave()
1836 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1841 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1846 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1851 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_prph_msk()
1881 /* free all first - we might be reconfigured for a different size */ in iwl_trans_pcie_configure()
1884 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; in iwl_trans_pcie_configure()
1885 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; in iwl_trans_pcie_configure()
1886 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; in iwl_trans_pcie_configure()
1887 trans->txqs.page_offs = trans_cfg->cb_data_offs; in iwl_trans_pcie_configure()
1888 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); in iwl_trans_pcie_configure()
1890 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) in iwl_trans_pcie_configure()
1891 trans_pcie->n_no_reclaim_cmds = 0; in iwl_trans_pcie_configure()
1893 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; in iwl_trans_pcie_configure()
1894 if (trans_pcie->n_no_reclaim_cmds) in iwl_trans_pcie_configure()
1895 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, in iwl_trans_pcie_configure()
1896 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); in iwl_trans_pcie_configure()
1898 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; in iwl_trans_pcie_configure()
1899 trans_pcie->rx_page_order = in iwl_trans_pcie_configure()
1900 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); in iwl_trans_pcie_configure()
1901 trans_pcie->rx_buf_bytes = in iwl_trans_pcie_configure()
1902 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); in iwl_trans_pcie_configure()
1903 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); in iwl_trans_pcie_configure()
1904 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_configure()
1905 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); in iwl_trans_pcie_configure()
1907 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; in iwl_trans_pcie_configure()
1908 trans_pcie->scd_set_active = trans_cfg->scd_set_active; in iwl_trans_pcie_configure()
1910 trans->command_groups = trans_cfg->command_groups; in iwl_trans_pcie_configure()
1911 trans->command_groups_size = trans_cfg->command_groups_size; in iwl_trans_pcie_configure()
1913 /* Initialize NAPI here - it should be before registering to mac80211 in iwl_trans_pcie_configure()
1918 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) in iwl_trans_pcie_configure()
1919 init_dummy_netdev(&trans_pcie->napi_dev); in iwl_trans_pcie_configure()
1921 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; in iwl_trans_pcie_configure()
1931 if (trans->trans_cfg->gen2) in iwl_trans_pcie_free()
1937 if (trans_pcie->rba.alloc_wq) { in iwl_trans_pcie_free()
1938 destroy_workqueue(trans_pcie->rba.alloc_wq); in iwl_trans_pcie_free()
1939 trans_pcie->rba.alloc_wq = NULL; in iwl_trans_pcie_free()
1942 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_free()
1943 for (i = 0; i < trans_pcie->alloc_vecs; i++) { in iwl_trans_pcie_free()
1945 trans_pcie->msix_entries[i].vector, in iwl_trans_pcie_free()
1949 trans_pcie->msix_enabled = false; in iwl_trans_pcie_free()
1956 if (trans_pcie->pnvm_dram.size) in iwl_trans_pcie_free()
1957 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, in iwl_trans_pcie_free()
1958 trans_pcie->pnvm_dram.block, in iwl_trans_pcie_free()
1959 trans_pcie->pnvm_dram.physical); in iwl_trans_pcie_free()
1961 if (trans_pcie->reduce_power_dram.size) in iwl_trans_pcie_free()
1962 dma_free_coherent(trans->dev, in iwl_trans_pcie_free()
1963 trans_pcie->reduce_power_dram.size, in iwl_trans_pcie_free()
1964 trans_pcie->reduce_power_dram.block, in iwl_trans_pcie_free()
1965 trans_pcie->reduce_power_dram.physical); in iwl_trans_pcie_free()
1967 mutex_destroy(&trans_pcie->mutex); in iwl_trans_pcie_free()
1974 set_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
1976 clear_bit(STATUS_TPOWER_PMI, &trans->status); in iwl_trans_pcie_set_pmi()
1988 struct pci_dev *pdev = removal->pdev; in iwl_trans_pcie_removal_wk()
1991 dev_err(&pdev->dev, "Device gone - attempting removal\n"); in iwl_trans_pcie_removal_wk()
1992 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); in iwl_trans_pcie_removal_wk()
2015 spin_lock(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2017 if (trans_pcie->cmd_hold_nic_awake) in __iwl_trans_pcie_grab_nic_access()
2020 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in __iwl_trans_pcie_grab_nic_access()
2028 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in __iwl_trans_pcie_grab_nic_access()
2036 * host DRAM when sleeping/waking for power-saving. in __iwl_trans_pcie_grab_nic_access()
2048 * 5000 series and later (including 1000 series) have non-volatile SRAM, in __iwl_trans_pcie_grab_nic_access()
2064 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in __iwl_trans_pcie_grab_nic_access()
2067 IWL_ERR(trans, "Device gone - scheduling removal!\n"); in __iwl_trans_pcie_grab_nic_access()
2077 "Module is being unloaded - abort\n"); in __iwl_trans_pcie_grab_nic_access()
2090 set_bit(STATUS_TRANS_DEAD, &trans->status); in __iwl_trans_pcie_grab_nic_access()
2092 removal->pdev = to_pci_dev(trans->dev); in __iwl_trans_pcie_grab_nic_access()
2093 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); in __iwl_trans_pcie_grab_nic_access()
2094 pci_dev_get(removal->pdev); in __iwl_trans_pcie_grab_nic_access()
2095 schedule_work(&removal->work); in __iwl_trans_pcie_grab_nic_access()
2102 spin_unlock(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2108 * Fool sparse by faking we release the lock - sparse will in __iwl_trans_pcie_grab_nic_access()
2111 __release(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2133 lockdep_assert_held(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2136 * Fool sparse by faking we acquiring the lock - sparse will in iwl_trans_pcie_release_nic_access()
2139 __acquire(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2141 if (trans_pcie->cmd_hold_nic_awake) in iwl_trans_pcie_release_nic_access()
2153 spin_unlock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2186 return -EBUSY; in iwl_trans_pcie_read_mem()
2206 ret = -EBUSY; in iwl_trans_pcie_write_mem()
2214 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, in iwl_trans_pcie_read_config32()
2222 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { in iwl_trans_pcie_block_txq_ptrs()
2223 struct iwl_txq *txq = trans->txqs.txq[i]; in iwl_trans_pcie_block_txq_ptrs()
2225 if (i == trans->txqs.cmd.q_id) in iwl_trans_pcie_block_txq_ptrs()
2228 spin_lock_bh(&txq->lock); in iwl_trans_pcie_block_txq_ptrs()
2230 if (!block && !(WARN_ON_ONCE(!txq->block))) { in iwl_trans_pcie_block_txq_ptrs()
2231 txq->block--; in iwl_trans_pcie_block_txq_ptrs()
2232 if (!txq->block) { in iwl_trans_pcie_block_txq_ptrs()
2234 txq->write_ptr | (i << 8)); in iwl_trans_pcie_block_txq_ptrs()
2237 txq->block++; in iwl_trans_pcie_block_txq_ptrs()
2240 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_block_txq_ptrs()
2251 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) in iwl_trans_pcie_rxq_dma_data()
2252 return -EINVAL; in iwl_trans_pcie_rxq_dma_data()
2254 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; in iwl_trans_pcie_rxq_dma_data()
2255 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; in iwl_trans_pcie_rxq_dma_data()
2256 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; in iwl_trans_pcie_rxq_dma_data()
2257 data->fr_bd_wid = 0; in iwl_trans_pcie_rxq_dma_data()
2270 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_wait_txq_empty()
2271 return -ENODEV; in iwl_trans_pcie_wait_txq_empty()
2273 if (!test_bit(txq_idx, trans->txqs.queue_used)) in iwl_trans_pcie_wait_txq_empty()
2274 return -EINVAL; in iwl_trans_pcie_wait_txq_empty()
2277 txq = trans->txqs.txq[txq_idx]; in iwl_trans_pcie_wait_txq_empty()
2279 spin_lock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2280 overflow_tx = txq->overflow_tx || in iwl_trans_pcie_wait_txq_empty()
2281 !skb_queue_empty(&txq->overflow_q); in iwl_trans_pcie_wait_txq_empty()
2282 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2284 wr_ptr = READ_ONCE(txq->write_ptr); in iwl_trans_pcie_wait_txq_empty()
2286 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || in iwl_trans_pcie_wait_txq_empty()
2290 u8 write_ptr = READ_ONCE(txq->write_ptr); in iwl_trans_pcie_wait_txq_empty()
2298 "WR pointer moved while flushing %d -> %d\n", in iwl_trans_pcie_wait_txq_empty()
2300 return -ETIMEDOUT; in iwl_trans_pcie_wait_txq_empty()
2305 spin_lock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2306 overflow_tx = txq->overflow_tx || in iwl_trans_pcie_wait_txq_empty()
2307 !skb_queue_empty(&txq->overflow_q); in iwl_trans_pcie_wait_txq_empty()
2308 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2311 if (txq->read_ptr != txq->write_ptr) { in iwl_trans_pcie_wait_txq_empty()
2315 return -ETIMEDOUT; in iwl_trans_pcie_wait_txq_empty()
2330 cnt < trans->trans_cfg->base_params->num_of_queues; in iwl_trans_pcie_wait_txqs_empty()
2333 if (cnt == trans->txqs.cmd.q_id) in iwl_trans_pcie_wait_txqs_empty()
2335 if (!test_bit(cnt, trans->txqs.queue_used)) in iwl_trans_pcie_wait_txqs_empty()
2353 spin_lock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_set_bits_mask()
2355 spin_unlock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_set_bits_mask()
2471 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_start()
2474 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_start()
2480 state->pos = *pos; in iwl_dbgfs_tx_queue_seq_start()
2487 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_next()
2490 *pos = ++state->pos; in iwl_dbgfs_tx_queue_seq_next()
2492 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_next()
2505 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_show()
2507 struct iwl_trans *trans = priv->trans; in iwl_dbgfs_tx_queue_seq_show()
2508 struct iwl_txq *txq = trans->txqs.txq[state->pos]; in iwl_dbgfs_tx_queue_seq_show()
2511 (unsigned int)state->pos, in iwl_dbgfs_tx_queue_seq_show()
2512 !!test_bit(state->pos, trans->txqs.queue_used), in iwl_dbgfs_tx_queue_seq_show()
2513 !!test_bit(state->pos, trans->txqs.queue_stopped)); in iwl_dbgfs_tx_queue_seq_show()
2517 txq->read_ptr, txq->write_ptr, in iwl_dbgfs_tx_queue_seq_show()
2518 txq->need_update, txq->frozen, in iwl_dbgfs_tx_queue_seq_show()
2519 txq->n_window, txq->ampdu); in iwl_dbgfs_tx_queue_seq_show()
2523 if (state->pos == trans->txqs.cmd.q_id) in iwl_dbgfs_tx_queue_seq_show()
2545 return -ENOMEM; in iwl_dbgfs_tx_queue_open()
2547 priv->trans = inode->i_private; in iwl_dbgfs_tx_queue_open()
2555 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read()
2561 bufsz = sizeof(char) * 121 * trans->num_rx_queues; in iwl_dbgfs_rx_queue_read()
2563 if (!trans_pcie->rxq) in iwl_dbgfs_rx_queue_read()
2564 return -EAGAIN; in iwl_dbgfs_rx_queue_read()
2568 return -ENOMEM; in iwl_dbgfs_rx_queue_read()
2570 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { in iwl_dbgfs_rx_queue_read()
2571 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; in iwl_dbgfs_rx_queue_read()
2573 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", in iwl_dbgfs_rx_queue_read()
2575 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", in iwl_dbgfs_rx_queue_read()
2576 rxq->read); in iwl_dbgfs_rx_queue_read()
2577 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", in iwl_dbgfs_rx_queue_read()
2578 rxq->write); in iwl_dbgfs_rx_queue_read()
2579 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", in iwl_dbgfs_rx_queue_read()
2580 rxq->write_actual); in iwl_dbgfs_rx_queue_read()
2581 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", in iwl_dbgfs_rx_queue_read()
2582 rxq->need_update); in iwl_dbgfs_rx_queue_read()
2583 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", in iwl_dbgfs_rx_queue_read()
2584 rxq->free_count); in iwl_dbgfs_rx_queue_read()
2585 if (rxq->rb_stts) { in iwl_dbgfs_rx_queue_read()
2588 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_rx_queue_read()
2592 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_rx_queue_read()
2606 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read()
2608 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; in iwl_dbgfs_interrupt_read()
2617 return -ENOMEM; in iwl_dbgfs_interrupt_read()
2619 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2622 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2623 isr_stats->hw); in iwl_dbgfs_interrupt_read()
2624 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2625 isr_stats->sw); in iwl_dbgfs_interrupt_read()
2626 if (isr_stats->sw || isr_stats->hw) { in iwl_dbgfs_interrupt_read()
2627 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2629 isr_stats->err_code); in iwl_dbgfs_interrupt_read()
2632 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2633 isr_stats->sch); in iwl_dbgfs_interrupt_read()
2634 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2635 isr_stats->alive); in iwl_dbgfs_interrupt_read()
2637 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2638 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); in iwl_dbgfs_interrupt_read()
2640 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2641 isr_stats->ctkill); in iwl_dbgfs_interrupt_read()
2643 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2644 isr_stats->wakeup); in iwl_dbgfs_interrupt_read()
2646 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2647 "Rx command responses:\t\t %u\n", isr_stats->rx); in iwl_dbgfs_interrupt_read()
2649 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2650 isr_stats->tx); in iwl_dbgfs_interrupt_read()
2652 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2653 isr_stats->unhandled); in iwl_dbgfs_interrupt_read()
2664 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write()
2666 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; in iwl_dbgfs_interrupt_write()
2683 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write()
2694 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read()
2702 return -EINVAL; in iwl_dbgfs_fh_reg_read()
2712 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_read()
2718 trans_pcie->debug_rfkill, in iwl_dbgfs_rfkill_read()
2729 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_write()
2737 if (new_value == trans_pcie->debug_rfkill) in iwl_dbgfs_rfkill_write()
2739 IWL_WARN(trans, "changing debug rfkill %d->%d\n", in iwl_dbgfs_rfkill_write()
2740 trans_pcie->debug_rfkill, new_value); in iwl_dbgfs_rfkill_write()
2741 trans_pcie->debug_rfkill = new_value; in iwl_dbgfs_rfkill_write()
2750 struct iwl_trans *trans = inode->i_private; in iwl_dbgfs_monitor_data_open()
2753 if (!trans->dbg.dest_tlv || in iwl_dbgfs_monitor_data_open()
2754 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { in iwl_dbgfs_monitor_data_open()
2756 return -ENOENT; in iwl_dbgfs_monitor_data_open()
2759 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) in iwl_dbgfs_monitor_data_open()
2760 return -EBUSY; in iwl_dbgfs_monitor_data_open()
2762 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; in iwl_dbgfs_monitor_data_open()
2770 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); in iwl_dbgfs_monitor_data_release()
2772 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) in iwl_dbgfs_monitor_data_release()
2773 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; in iwl_dbgfs_monitor_data_release()
2781 int buf_size_left = count - *bytes_copied; in iwl_write_to_user_buf()
2783 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); in iwl_write_to_user_buf()
2787 *size -= copy_to_user(user_buf, buf, *size); in iwl_write_to_user_buf()
2799 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_monitor_data_read()
2801 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; in iwl_dbgfs_monitor_data_read()
2802 struct cont_rec *data = &trans_pcie->fw_mon_data; in iwl_dbgfs_monitor_data_read()
2807 if (trans->dbg.dest_tlv) { in iwl_dbgfs_monitor_data_read()
2809 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_dbgfs_monitor_data_read()
2810 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_dbgfs_monitor_data_read()
2816 if (unlikely(!trans->dbg.rec_on)) in iwl_dbgfs_monitor_data_read()
2819 mutex_lock(&data->mutex); in iwl_dbgfs_monitor_data_read()
2820 if (data->state == in iwl_dbgfs_monitor_data_read()
2822 mutex_unlock(&data->mutex); in iwl_dbgfs_monitor_data_read()
2830 if (data->prev_wrap_cnt == wrap_cnt) { in iwl_dbgfs_monitor_data_read()
2831 size = write_ptr - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2832 curr_buf = cpu_addr + data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2836 data->prev_wr_ptr += size; in iwl_dbgfs_monitor_data_read()
2838 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && in iwl_dbgfs_monitor_data_read()
2839 write_ptr < data->prev_wr_ptr) { in iwl_dbgfs_monitor_data_read()
2840 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2841 curr_buf = cpu_addr + data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2845 data->prev_wr_ptr += size; in iwl_dbgfs_monitor_data_read()
2852 data->prev_wr_ptr = size; in iwl_dbgfs_monitor_data_read()
2853 data->prev_wrap_cnt++; in iwl_dbgfs_monitor_data_read()
2856 if (data->prev_wrap_cnt == wrap_cnt - 1 && in iwl_dbgfs_monitor_data_read()
2857 write_ptr > data->prev_wr_ptr) in iwl_dbgfs_monitor_data_read()
2860 else if (!unlikely(data->prev_wrap_cnt == 0 && in iwl_dbgfs_monitor_data_read()
2861 data->prev_wr_ptr == 0)) in iwl_dbgfs_monitor_data_read()
2863 "monitor data is out of sync, start copying from the beginning\n"); in iwl_dbgfs_monitor_data_read()
2869 data->prev_wr_ptr = size; in iwl_dbgfs_monitor_data_read()
2870 data->prev_wrap_cnt = wrap_cnt; in iwl_dbgfs_monitor_data_read()
2873 mutex_unlock(&data->mutex); in iwl_dbgfs_monitor_data_read()
2882 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rf_read()
2885 if (!trans_pcie->rf_name[0]) in iwl_dbgfs_rf_read()
2886 return -ENODEV; in iwl_dbgfs_rf_read()
2889 trans_pcie->rf_name, in iwl_dbgfs_rf_read()
2890 strlen(trans_pcie->rf_name)); in iwl_dbgfs_rf_read()
2917 struct dentry *dir = trans->dbgfs_dir; in iwl_trans_pcie_dbgfs_register()
2932 struct cont_rec *data = &trans_pcie->fw_mon_data; in iwl_trans_pcie_debugfs_cleanup()
2934 mutex_lock(&data->mutex); in iwl_trans_pcie_debugfs_cleanup()
2935 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; in iwl_trans_pcie_debugfs_cleanup()
2936 mutex_unlock(&data->mutex); in iwl_trans_pcie_debugfs_cleanup()
2945 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) in iwl_trans_pcie_get_cmdlen()
2956 int max_len = trans_pcie->rx_buf_bytes; in iwl_trans_pcie_dump_rbs()
2957 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ in iwl_trans_pcie_dump_rbs()
2958 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; in iwl_trans_pcie_dump_rbs()
2961 spin_lock(&rxq->lock); in iwl_trans_pcie_dump_rbs()
2965 for (i = rxq->read, j = 0; in iwl_trans_pcie_dump_rbs()
2968 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; in iwl_trans_pcie_dump_rbs()
2971 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, in iwl_trans_pcie_dump_rbs()
2976 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); in iwl_trans_pcie_dump_rbs()
2977 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); in iwl_trans_pcie_dump_rbs()
2978 rb = (void *)(*data)->data; in iwl_trans_pcie_dump_rbs()
2979 rb->index = cpu_to_le32(i); in iwl_trans_pcie_dump_rbs()
2980 memcpy(rb->data, page_address(rxb->page), max_len); in iwl_trans_pcie_dump_rbs()
2985 spin_unlock(&rxq->lock); in iwl_trans_pcie_dump_rbs()
2998 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); in iwl_trans_pcie_dump_csr()
2999 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); in iwl_trans_pcie_dump_csr()
3000 val = (void *)(*data)->data; in iwl_trans_pcie_dump_csr()
3013 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; in iwl_trans_pcie_fh_regs_dump()
3020 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); in iwl_trans_pcie_fh_regs_dump()
3021 (*data)->len = cpu_to_le32(fh_regs_len); in iwl_trans_pcie_fh_regs_dump()
3022 val = (void *)(*data)->data; in iwl_trans_pcie_fh_regs_dump()
3024 if (!trans->trans_cfg->gen2) in iwl_trans_pcie_fh_regs_dump()
3048 u32 *buffer = (u32 *)fw_mon_data->data; in iwl_trans_pci_dump_marbh_monitor()
3071 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3076 } else if (trans->dbg.dest_tlv) { in iwl_trans_pcie_dump_pointers()
3077 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_pointers()
3078 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_trans_pcie_dump_pointers()
3079 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_pcie_dump_pointers()
3087 fw_mon_data->fw_mon_cycle_cnt = in iwl_trans_pcie_dump_pointers()
3089 fw_mon_data->fw_mon_base_ptr = in iwl_trans_pcie_dump_pointers()
3091 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3092 fw_mon_data->fw_mon_base_high_ptr = in iwl_trans_pcie_dump_pointers()
3098 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); in iwl_trans_pcie_dump_pointers()
3106 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_trans_pcie_dump_monitor()
3109 if (trans->dbg.dest_tlv || in iwl_trans_pcie_dump_monitor()
3110 (fw_mon->size && in iwl_trans_pcie_dump_monitor()
3111 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || in iwl_trans_pcie_dump_monitor()
3112 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { in iwl_trans_pcie_dump_monitor()
3115 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); in iwl_trans_pcie_dump_monitor()
3116 fw_mon_data = (void *)(*data)->data; in iwl_trans_pcie_dump_monitor()
3121 if (fw_mon->size) { in iwl_trans_pcie_dump_monitor()
3122 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); in iwl_trans_pcie_dump_monitor()
3123 monitor_len = fw_mon->size; in iwl_trans_pcie_dump_monitor()
3124 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
3125 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); in iwl_trans_pcie_dump_monitor()
3130 if (trans->dbg.dest_tlv->version) { in iwl_trans_pcie_dump_monitor()
3133 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3135 base += trans->cfg->smem_offset; in iwl_trans_pcie_dump_monitor()
3138 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3141 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_monitor()
3143 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
3149 /* Didn't match anything - output no monitor data */ in iwl_trans_pcie_dump_monitor()
3154 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); in iwl_trans_pcie_dump_monitor()
3162 if (trans->dbg.fw_mon.size) { in iwl_trans_get_fw_monitor_len()
3165 trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3166 return trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3167 } else if (trans->dbg.dest_tlv) { in iwl_trans_get_fw_monitor_len()
3170 if (trans->dbg.dest_tlv->version == 1) { in iwl_trans_get_fw_monitor_len()
3171 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3174 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3176 base += trans->cfg->smem_offset; in iwl_trans_get_fw_monitor_len()
3180 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3183 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3184 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); in iwl_trans_get_fw_monitor_len()
3187 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3189 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3192 if (trans->trans_cfg->device_family >= in iwl_trans_get_fw_monitor_len()
3194 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_get_fw_monitor_len()
3195 end += (1 << trans->dbg.dest_tlv->end_shift); in iwl_trans_get_fw_monitor_len()
3196 monitor_len = end - base; in iwl_trans_get_fw_monitor_len()
3212 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; in iwl_trans_pcie_dump_data() local
3217 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && in iwl_trans_pcie_dump_data()
3218 !trans->trans_cfg->mq_rx_supported && in iwl_trans_pcie_dump_data()
3228 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) in iwl_trans_pcie_dump_data()
3230 cmdq->n_window * (sizeof(*txcmd) + in iwl_trans_pcie_dump_data()
3243 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3245 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - in iwl_trans_pcie_dump_data()
3249 (FH_MEM_UPPER_BOUND - in iwl_trans_pcie_dump_data()
3254 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ in iwl_trans_pcie_dump_data()
3255 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; in iwl_trans_pcie_dump_data()
3260 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; in iwl_trans_pcie_dump_data()
3263 (PAGE_SIZE << trans_pcie->rx_page_order)); in iwl_trans_pcie_dump_data()
3267 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) in iwl_trans_pcie_dump_data()
3268 for (i = 0; i < trans->init_dram.paging_cnt; i++) in iwl_trans_pcie_dump_data()
3271 trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3278 data = (void *)dump_data->data; in iwl_trans_pcie_dump_data()
3280 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { in iwl_trans_pcie_dump_data()
3281 u16 tfd_size = trans->txqs.tfd.size; in iwl_trans_pcie_dump_data()
3283 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); in iwl_trans_pcie_dump_data()
3284 txcmd = (void *)data->data; in iwl_trans_pcie_dump_data()
3285 spin_lock_bh(&cmdq->lock); in iwl_trans_pcie_dump_data()
3286 ptr = cmdq->write_ptr; in iwl_trans_pcie_dump_data()
3287 for (i = 0; i < cmdq->n_window; i++) { in iwl_trans_pcie_dump_data()
3288 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); in iwl_trans_pcie_dump_data()
3292 if (trans->trans_cfg->use_tfh) in iwl_trans_pcie_dump_data()
3298 (u8 *)cmdq->tfds + in iwl_trans_pcie_dump_data()
3304 txcmd->cmdlen = cpu_to_le32(cmdlen); in iwl_trans_pcie_dump_data()
3305 txcmd->caplen = cpu_to_le32(caplen); in iwl_trans_pcie_dump_data()
3306 memcpy(txcmd->data, cmdq->entries[idx].cmd, in iwl_trans_pcie_dump_data()
3308 txcmd = (void *)((u8 *)txcmd->data + caplen); in iwl_trans_pcie_dump_data()
3313 spin_unlock_bh(&cmdq->lock); in iwl_trans_pcie_dump_data()
3315 data->len = cpu_to_le32(len); in iwl_trans_pcie_dump_data()
3328 if (trans->trans_cfg->gen2 && in iwl_trans_pcie_dump_data()
3330 for (i = 0; i < trans->init_dram.paging_cnt; i++) { in iwl_trans_pcie_dump_data()
3332 u32 page_len = trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3334 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); in iwl_trans_pcie_dump_data()
3335 data->len = cpu_to_le32(sizeof(*paging) + page_len); in iwl_trans_pcie_dump_data()
3336 paging = (void *)data->data; in iwl_trans_pcie_dump_data()
3337 paging->index = cpu_to_le32(i); in iwl_trans_pcie_dump_data()
3338 memcpy(paging->data, in iwl_trans_pcie_dump_data()
3339 trans->init_dram.paging[i].block, page_len); in iwl_trans_pcie_dump_data()
3348 dump_data->len = len; in iwl_trans_pcie_dump_data()
3366 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_sync_nmi()
3460 if (!cfg_trans->gen2) in iwl_trans_pcie_alloc()
3467 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, in iwl_trans_pcie_alloc()
3470 return ERR_PTR(-ENOMEM); in iwl_trans_pcie_alloc()
3474 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
3475 trans_pcie->opmode_down = true; in iwl_trans_pcie_alloc()
3476 spin_lock_init(&trans_pcie->irq_lock); in iwl_trans_pcie_alloc()
3477 spin_lock_init(&trans_pcie->reg_lock); in iwl_trans_pcie_alloc()
3478 spin_lock_init(&trans_pcie->alloc_page_lock); in iwl_trans_pcie_alloc()
3479 mutex_init(&trans_pcie->mutex); in iwl_trans_pcie_alloc()
3480 init_waitqueue_head(&trans_pcie->ucode_write_waitq); in iwl_trans_pcie_alloc()
3481 init_waitqueue_head(&trans_pcie->fw_reset_waitq); in iwl_trans_pcie_alloc()
3483 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", in iwl_trans_pcie_alloc()
3485 if (!trans_pcie->rba.alloc_wq) { in iwl_trans_pcie_alloc()
3486 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3489 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); in iwl_trans_pcie_alloc()
3491 trans_pcie->debug_rfkill = -1; in iwl_trans_pcie_alloc()
3493 if (!cfg_trans->base_params->pcie_l1_allowed) { in iwl_trans_pcie_alloc()
3495 * W/A - seems to solve weird behavior. We need to remove this in iwl_trans_pcie_alloc()
3504 trans_pcie->def_rx_queue = 0; in iwl_trans_pcie_alloc()
3508 addr_size = trans->txqs.tfd.addr_size; in iwl_trans_pcie_alloc()
3509 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); in iwl_trans_pcie_alloc()
3511 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in iwl_trans_pcie_alloc()
3514 dev_err(&pdev->dev, "No suitable DMA available\n"); in iwl_trans_pcie_alloc()
3521 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); in iwl_trans_pcie_alloc()
3527 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); in iwl_trans_pcie_alloc()
3528 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3532 trans_pcie->hw_base = table[0]; in iwl_trans_pcie_alloc()
3533 if (!trans_pcie->hw_base) { in iwl_trans_pcie_alloc()
3534 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); in iwl_trans_pcie_alloc()
3535 ret = -ENODEV; in iwl_trans_pcie_alloc()
3543 trans_pcie->pci_dev = pdev; in iwl_trans_pcie_alloc()
3546 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
3547 if (trans->hw_rev == 0xffffffff) { in iwl_trans_pcie_alloc()
3548 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); in iwl_trans_pcie_alloc()
3549 ret = -EIO; in iwl_trans_pcie_alloc()
3555 * changed, and now the revision step also includes bit 0-1 (no more in iwl_trans_pcie_alloc()
3556 * "dash" value). To keep hw_rev backwards compatible - we'll store it in iwl_trans_pcie_alloc()
3559 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_alloc()
3560 trans->hw_rev = (trans->hw_rev & 0xfff0) | in iwl_trans_pcie_alloc()
3561 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); in iwl_trans_pcie_alloc()
3563 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); in iwl_trans_pcie_alloc()
3566 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
3567 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
3568 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); in iwl_trans_pcie_alloc()
3570 init_waitqueue_head(&trans_pcie->sx_waitq); in iwl_trans_pcie_alloc()
3573 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_alloc()
3582 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, in iwl_trans_pcie_alloc()
3587 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
3593 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; in iwl_trans_pcie_alloc()
3594 mutex_init(&trans_pcie->fw_mon_data.mutex); in iwl_trans_pcie_alloc()
3604 destroy_workqueue(trans_pcie->rba.alloc_wq); in iwl_trans_pcie_alloc()