Lines Matching +full:ext +full:- +full:reset +full:- +full:output

1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
47 #define	RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
49 #define	RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
50 #define	RES_Tx_P	0x28	/* Reset TxINT Pending */
51 #define	ERR_RES		0x30	/* Error Reset */
52 #define	RES_H_IUS	0x38	/* Reset highest IUS */
54 #define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
55 #define	RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
56 #define	RES_EOM_L	0xC0	/* Reset EOM latch */
60 #define	EXT_INT_ENAB	0x1	/* Ext Int Enable */
112 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
121 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
123 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
133 #define	NORESET	0	/* No reset on write to R9 */
134 #define	CHRB	0x40	/* Reset channel B */
135 #define	CHRA	0x80	/* Reset channel A */
136 #define	FHWRES	0xc0	/* Force hardware reset */
151 #define	TRxCXT	0	/* TRxC = Xtal output */
153 #define	TRxCBR	2	/* TRxC = BR Generator Output */
154 #define	TRxCDP	3	/* TRxC = DPLL output */
158 #define	TCBR	0x10	/* Transmit clock = BR Generator output */
159 #define	TCDPLL	0x18	/* Transmit clock = DPLL output */
162 #define	RCBR	0x40	/* Receive clock = BR Generator output */
163 #define	RCDPLL	0x60	/* Receive clock = DPLL output */
177 #define	RMC	0x40	/* Reset missing clock */
222 /* Read Register 2 (channel b only) - Interrupt vector */
225 #define	CHBEXT	0x1		/* Channel B Ext/Stat IP */
228 #define	CHAEXT	0x8		/* Channel A Ext/Stat IP */
320 	u32		rx_overrun;		/* Overruns - not done yet */
344 #define Z85C30	1	/* CMOS - better */
347 	int active;	/* Soft interrupt enable - the Mac doesn't 
393  * Events are used to schedule things to happen at timer-interrupt