Lines Matching +full:flip +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0-or-later
25 * 512Kbit->1Mbit depending on motherboard.
57 * z8530_read_port - Architecture specific interface function
82 * z8530_write_port - Architecture specific interface function
107 * read_zsreg - Read a register from a Z85230
108 * @c: Z8530 channel to read from (2 per chip)
120 z8530_write_port(c->ctrlio, reg); in read_zsreg()
121 return z8530_read_port(c->ctrlio); in read_zsreg()
125 * read_zsdata - Read the data port of a Z8530 channel
136 r = z8530_read_port(c->dataio); in read_zsdata()
141 * write_zsreg - Write to a Z8530 channel register
150 * Assumes c->lock is held.
155 z8530_write_port(c->ctrlio, reg); in write_zsreg()
156 z8530_write_port(c->ctrlio, val); in write_zsreg()
160 * write_zsctrl - Write to a Z8530 control register
169 z8530_write_port(c->ctrlio, val); in write_zsctrl()
173 * write_zsdata - Write to a Z8530 control register
181 z8530_write_port(c->dataio, val); in write_zsdata()
243 * z8530_flush_fifo - Flush on chip RX FIFO
260 if (c->dev->type == Z85230) { in z8530_flush_fifo()
269 * z8530_rtsdtr - Control the outgoing DTS/RTS line
275 * on the chip. Apparently one or two don't. We'll scream about them
282 c->regs[5] |= (RTS | DTR); in z8530_rtsdtr()
284 c->regs[5] &= ~(RTS | DTR); in z8530_rtsdtr()
285 write_zsreg(c, R5, c->regs[5]); in z8530_rtsdtr()
289 * z8530_rx - Handle a PIO receive event
300 * by them as short as possible in all circumstances - clocks cost
302 * other code - this is true in the RT case too.
325 if (c->count < c->max) { in z8530_rx()
326 *c->dptr++ = ch; in z8530_rx()
327 c->count++; in z8530_rx()
335 if (c->skb) in z8530_rx()
336 c->dptr = c->skb->data; in z8530_rx()
337 c->count = 0; in z8530_rx()
339 pr_warn("%s: overrun\n", c->dev->name); in z8530_rx()
340 c->rx_overrun++; in z8530_rx()
343 c->rx_crc_err++; in z8530_rx()
363 * z8530_tx - Handle a PIO transmit event
374 while (c->txcount) { in z8530_tx()
378 c->txcount--; in z8530_tx()
381 write_zsreg(c, R8, *c->tx_ptr++); in z8530_tx()
384 if (c->txcount == 0) { in z8530_tx()
386 write_zsreg(c, R10, c->regs[10] & ~ABUNDER); in z8530_tx()
390 /* End of frame TX - fire another one in z8530_tx()
400 * z8530_status - Handle a PIO status exception
404 * reasons the chip will bother us here. A transmit underrun means we
405 * failed to feed the chip fast enough and just broke a packet. A DCD
414 altered = chan->status ^ status; in z8530_status()
416 chan->status = status; in z8530_status()
419 /* printk("%s: Tx underrun.\n", chan->dev->name); */ in z8530_status()
420 chan->netdevice->stats.tx_fifo_errors++; in z8530_status()
425 if (altered & chan->dcdcheck) { in z8530_status()
426 if (status & chan->dcdcheck) { in z8530_status()
427 pr_info("%s: DCD raised\n", chan->dev->name); in z8530_status()
428 write_zsreg(chan, R3, chan->regs[3] | RxENABLE); in z8530_status()
429 if (chan->netdevice) in z8530_status()
430 netif_carrier_on(chan->netdevice); in z8530_status()
432 pr_info("%s: DCD lost\n", chan->dev->name); in z8530_status()
433 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE); in z8530_status()
435 if (chan->netdevice) in z8530_status()
436 netif_carrier_off(chan->netdevice); in z8530_status()
451 * z8530_dma_rx - Handle a DMA RX event
462 if (chan->rxdma_on) { in z8530_dma_rx()
483 * z8530_dma_tx - Handle a DMA TX event
491 if (!chan->dma_tx) { in z8530_dma_tx()
497 pr_err("DMA tx - bogus event!\n"); in z8530_dma_tx()
502 * z8530_dma_status - Handle a DMA status exception
515 altered = chan->status ^ status; in z8530_dma_status()
517 chan->status = status; in z8530_dma_status()
519 if (chan->dma_tx) { in z8530_dma_status()
524 disable_dma(chan->txdma); in z8530_dma_status()
525 clear_dma_ff(chan->txdma); in z8530_dma_status()
526 chan->txdma_on = 0; in z8530_dma_status()
532 if (altered & chan->dcdcheck) { in z8530_dma_status()
533 if (status & chan->dcdcheck) { in z8530_dma_status()
534 pr_info("%s: DCD raised\n", chan->dev->name); in z8530_dma_status()
535 write_zsreg(chan, R3, chan->regs[3] | RxENABLE); in z8530_dma_status()
536 if (chan->netdevice) in z8530_dma_status()
537 netif_carrier_on(chan->netdevice); in z8530_dma_status()
539 pr_info("%s: DCD lost\n", chan->dev->name); in z8530_dma_status()
540 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE); in z8530_dma_status()
542 if (chan->netdevice) in z8530_dma_status()
543 netif_carrier_off(chan->netdevice); in z8530_dma_status()
564 * z8530_rx_clear - Handle RX events from a stopped chip
590 * z8530_tx_clear - Handle TX events from a stopped chip
605 * z8530_status_clear - Handle status events from a stopped chip
631 * z8530_interrupt - Handle an interrupt from a Z8530
636 * We scan both the channels on the chip for events and then call
642 * at the chip level (the 5uS delay issue is per chip not per
643 * channel). c->lock for both channels points to dev->lock
655 pr_err("IRQ re-enter\n"); in z8530_interrupt()
660 spin_lock(&dev->lock); in z8530_interrupt()
663 intr = read_zsreg(&dev->chanA, R3); in z8530_interrupt()
669 * from chan A even though it applies to the whole chip in z8530_interrupt()
672 /* Now walk the chip and see what it is wanting - it may be in z8530_interrupt()
676 irqs = dev->chanA.irqs; in z8530_interrupt()
680 irqs->rx(&dev->chanA); in z8530_interrupt()
682 irqs->tx(&dev->chanA); in z8530_interrupt()
684 irqs->status(&dev->chanA); in z8530_interrupt()
687 irqs = dev->chanB.irqs; in z8530_interrupt()
691 irqs->rx(&dev->chanB); in z8530_interrupt()
693 irqs->tx(&dev->chanB); in z8530_interrupt()
695 irqs->status(&dev->chanB); in z8530_interrupt()
698 spin_unlock(&dev->lock); in z8530_interrupt()
700 pr_err("%s: interrupt jammed - abort(0x%X)!\n", in z8530_interrupt()
701 dev->name, intr); in z8530_interrupt()
716 * z8530_sync_open - Open a Z8530 channel for PIO
727 spin_lock_irqsave(c->lock, flags); in z8530_sync_open()
729 c->sync = 1; in z8530_sync_open()
730 c->mtu = dev->mtu + 64; in z8530_sync_open()
731 c->count = 0; in z8530_sync_open()
732 c->skb = NULL; in z8530_sync_open()
733 c->skb2 = NULL; in z8530_sync_open()
734 c->irqs = &z8530_sync; in z8530_sync_open()
740 c->dma_tx = 0; in z8530_sync_open()
741 c->regs[R1] |= TxINT_ENAB; in z8530_sync_open()
742 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_open()
743 write_zsreg(c, R3, c->regs[R3] | RxENABLE); in z8530_sync_open()
745 spin_unlock_irqrestore(c->lock, flags); in z8530_sync_open()
751 * z8530_sync_close - Close a PIO Z8530 channel
763 spin_lock_irqsave(c->lock, flags); in z8530_sync_close()
764 c->irqs = &z8530_nop; in z8530_sync_close()
765 c->max = 0; in z8530_sync_close()
766 c->sync = 0; in z8530_sync_close()
769 write_zsreg(c, R3, c->regs[R3]); in z8530_sync_close()
772 spin_unlock_irqrestore(c->lock, flags); in z8530_sync_close()
778 * z8530_sync_dma_open - Open a Z8530 for DMA I/O
790 c->sync = 1; in z8530_sync_dma_open()
791 c->mtu = dev->mtu + 64; in z8530_sync_dma_open()
792 c->count = 0; in z8530_sync_dma_open()
793 c->skb = NULL; in z8530_sync_dma_open()
794 c->skb2 = NULL; in z8530_sync_dma_open()
798 c->rxdma_on = 0; in z8530_sync_dma_open()
799 c->txdma_on = 0; in z8530_sync_dma_open()
801 /* Allocate the DMA flip buffers. Limit by page size. in z8530_sync_dma_open()
806 if (c->mtu > PAGE_SIZE / 2) in z8530_sync_dma_open()
807 return -EMSGSIZE; in z8530_sync_dma_open()
809 c->rx_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); in z8530_sync_dma_open()
810 if (!c->rx_buf[0]) in z8530_sync_dma_open()
811 return -ENOBUFS; in z8530_sync_dma_open()
812 c->rx_buf[1] = c->rx_buf[0] + PAGE_SIZE / 2; in z8530_sync_dma_open()
814 c->tx_dma_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); in z8530_sync_dma_open()
815 if (!c->tx_dma_buf[0]) { in z8530_sync_dma_open()
816 free_page((unsigned long)c->rx_buf[0]); in z8530_sync_dma_open()
817 c->rx_buf[0] = NULL; in z8530_sync_dma_open()
818 return -ENOBUFS; in z8530_sync_dma_open()
820 c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE / 2; in z8530_sync_dma_open()
822 c->tx_dma_used = 0; in z8530_sync_dma_open()
823 c->dma_tx = 1; in z8530_sync_dma_open()
824 c->dma_num = 0; in z8530_sync_dma_open()
825 c->dma_ready = 1; in z8530_sync_dma_open()
830 spin_lock_irqsave(c->lock, cflags); in z8530_sync_dma_open()
835 c->regs[R14] |= DTRREQ; in z8530_sync_dma_open()
836 write_zsreg(c, R14, c->regs[R14]); in z8530_sync_dma_open()
838 c->regs[R1] &= ~TxINT_ENAB; in z8530_sync_dma_open()
839 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_dma_open()
844 c->regs[R1] |= WT_FN_RDYFN; in z8530_sync_dma_open()
845 c->regs[R1] |= WT_RDY_RT; in z8530_sync_dma_open()
846 c->regs[R1] |= INT_ERR_Rx; in z8530_sync_dma_open()
847 c->regs[R1] &= ~TxINT_ENAB; in z8530_sync_dma_open()
848 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_dma_open()
849 c->regs[R1] |= WT_RDY_ENAB; in z8530_sync_dma_open()
850 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_dma_open()
860 disable_dma(c->rxdma); in z8530_sync_dma_open()
861 clear_dma_ff(c->rxdma); in z8530_sync_dma_open()
862 set_dma_mode(c->rxdma, DMA_MODE_READ | 0x10); in z8530_sync_dma_open()
863 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0])); in z8530_sync_dma_open()
864 set_dma_count(c->rxdma, c->mtu); in z8530_sync_dma_open()
865 enable_dma(c->rxdma); in z8530_sync_dma_open()
867 disable_dma(c->txdma); in z8530_sync_dma_open()
868 clear_dma_ff(c->txdma); in z8530_sync_dma_open()
869 set_dma_mode(c->txdma, DMA_MODE_WRITE); in z8530_sync_dma_open()
870 disable_dma(c->txdma); in z8530_sync_dma_open()
877 c->rxdma_on = 1; in z8530_sync_dma_open()
878 c->txdma_on = 1; in z8530_sync_dma_open()
879 c->tx_dma_used = 1; in z8530_sync_dma_open()
881 c->irqs = &z8530_dma_sync; in z8530_sync_dma_open()
883 write_zsreg(c, R3, c->regs[R3] | RxENABLE); in z8530_sync_dma_open()
885 spin_unlock_irqrestore(c->lock, cflags); in z8530_sync_dma_open()
892 * z8530_sync_dma_close - Close down DMA I/O
904 c->irqs = &z8530_nop; in z8530_sync_dma_close()
905 c->max = 0; in z8530_sync_dma_close()
906 c->sync = 0; in z8530_sync_dma_close()
912 disable_dma(c->rxdma); in z8530_sync_dma_close()
913 clear_dma_ff(c->rxdma); in z8530_sync_dma_close()
915 c->rxdma_on = 0; in z8530_sync_dma_close()
917 disable_dma(c->txdma); in z8530_sync_dma_close()
918 clear_dma_ff(c->txdma); in z8530_sync_dma_close()
921 c->txdma_on = 0; in z8530_sync_dma_close()
922 c->tx_dma_used = 0; in z8530_sync_dma_close()
924 spin_lock_irqsave(c->lock, flags); in z8530_sync_dma_close()
929 c->regs[R1] &= ~WT_RDY_ENAB; in z8530_sync_dma_close()
930 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_dma_close()
931 c->regs[R1] &= ~(WT_RDY_RT | WT_FN_RDYFN | INT_ERR_Rx); in z8530_sync_dma_close()
932 c->regs[R1] |= INT_ALL_Rx; in z8530_sync_dma_close()
933 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_dma_close()
934 c->regs[R14] &= ~DTRREQ; in z8530_sync_dma_close()
935 write_zsreg(c, R14, c->regs[R14]); in z8530_sync_dma_close()
937 if (c->rx_buf[0]) { in z8530_sync_dma_close()
938 free_page((unsigned long)c->rx_buf[0]); in z8530_sync_dma_close()
939 c->rx_buf[0] = NULL; in z8530_sync_dma_close()
941 if (c->tx_dma_buf[0]) { in z8530_sync_dma_close()
942 free_page((unsigned long)c->tx_dma_buf[0]); in z8530_sync_dma_close()
943 c->tx_dma_buf[0] = NULL; in z8530_sync_dma_close()
946 write_zsreg(c, R3, c->regs[R3]); in z8530_sync_dma_close()
949 spin_unlock_irqrestore(c->lock, flags); in z8530_sync_dma_close()
956 * z8530_sync_txdma_open - Open a Z8530 for TX driven DMA
969 printk("Opening sync interface for TX-DMA\n"); in z8530_sync_txdma_open()
970 c->sync = 1; in z8530_sync_txdma_open()
971 c->mtu = dev->mtu + 64; in z8530_sync_txdma_open()
972 c->count = 0; in z8530_sync_txdma_open()
973 c->skb = NULL; in z8530_sync_txdma_open()
974 c->skb2 = NULL; in z8530_sync_txdma_open()
976 /* Allocate the DMA flip buffers. Limit by page size. in z8530_sync_txdma_open()
981 if (c->mtu > PAGE_SIZE / 2) in z8530_sync_txdma_open()
982 return -EMSGSIZE; in z8530_sync_txdma_open()
984 c->tx_dma_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); in z8530_sync_txdma_open()
985 if (!c->tx_dma_buf[0]) in z8530_sync_txdma_open()
986 return -ENOBUFS; in z8530_sync_txdma_open()
988 c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE / 2; in z8530_sync_txdma_open()
990 spin_lock_irqsave(c->lock, cflags); in z8530_sync_txdma_open()
1001 c->rxdma_on = 0; in z8530_sync_txdma_open()
1002 c->txdma_on = 0; in z8530_sync_txdma_open()
1004 c->tx_dma_used = 0; in z8530_sync_txdma_open()
1005 c->dma_num = 0; in z8530_sync_txdma_open()
1006 c->dma_ready = 1; in z8530_sync_txdma_open()
1007 c->dma_tx = 1; in z8530_sync_txdma_open()
1014 c->regs[R14] |= DTRREQ; in z8530_sync_txdma_open()
1015 write_zsreg(c, R14, c->regs[R14]); in z8530_sync_txdma_open()
1017 c->regs[R1] &= ~TxINT_ENAB; in z8530_sync_txdma_open()
1018 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_txdma_open()
1025 disable_dma(c->txdma); in z8530_sync_txdma_open()
1026 clear_dma_ff(c->txdma); in z8530_sync_txdma_open()
1027 set_dma_mode(c->txdma, DMA_MODE_WRITE); in z8530_sync_txdma_open()
1028 disable_dma(c->txdma); in z8530_sync_txdma_open()
1035 c->rxdma_on = 0; in z8530_sync_txdma_open()
1036 c->txdma_on = 1; in z8530_sync_txdma_open()
1037 c->tx_dma_used = 1; in z8530_sync_txdma_open()
1039 c->irqs = &z8530_txdma_sync; in z8530_sync_txdma_open()
1041 write_zsreg(c, R3, c->regs[R3] | RxENABLE); in z8530_sync_txdma_open()
1042 spin_unlock_irqrestore(c->lock, cflags); in z8530_sync_txdma_open()
1049 * z8530_sync_txdma_close - Close down a TX driven DMA channel
1062 spin_lock_irqsave(c->lock, cflags); in z8530_sync_txdma_close()
1064 c->irqs = &z8530_nop; in z8530_sync_txdma_close()
1065 c->max = 0; in z8530_sync_txdma_close()
1066 c->sync = 0; in z8530_sync_txdma_close()
1073 disable_dma(c->txdma); in z8530_sync_txdma_close()
1074 clear_dma_ff(c->txdma); in z8530_sync_txdma_close()
1075 c->txdma_on = 0; in z8530_sync_txdma_close()
1076 c->tx_dma_used = 0; in z8530_sync_txdma_close()
1083 c->regs[R1] &= ~WT_RDY_ENAB; in z8530_sync_txdma_close()
1084 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_txdma_close()
1085 c->regs[R1] &= ~(WT_RDY_RT | WT_FN_RDYFN | INT_ERR_Rx); in z8530_sync_txdma_close()
1086 c->regs[R1] |= INT_ALL_Rx; in z8530_sync_txdma_close()
1087 write_zsreg(c, R1, c->regs[R1]); in z8530_sync_txdma_close()
1088 c->regs[R14] &= ~DTRREQ; in z8530_sync_txdma_close()
1089 write_zsreg(c, R14, c->regs[R14]); in z8530_sync_txdma_close()
1091 if (c->tx_dma_buf[0]) { in z8530_sync_txdma_close()
1092 free_page((unsigned long)c->tx_dma_buf[0]); in z8530_sync_txdma_close()
1093 c->tx_dma_buf[0] = NULL; in z8530_sync_txdma_close()
1096 write_zsreg(c, R3, c->regs[R3]); in z8530_sync_txdma_close()
1099 spin_unlock_irqrestore(c->lock, cflags); in z8530_sync_txdma_close()
1114 * z8530_describe - Uniformly describe a Z8530 port
1127 dev->name, in z8530_describe()
1128 z8530_type_name[dev->type], in z8530_describe()
1131 dev->irq); in z8530_describe()
1139 /* NOP the interrupt handlers first - we might get a in do_z8530_init()
1140 * floating IRQ transition when we reset the chip in do_z8530_init()
1142 dev->chanA.irqs = &z8530_nop; in do_z8530_init()
1143 dev->chanB.irqs = &z8530_nop; in do_z8530_init()
1144 dev->chanA.dcdcheck = DCD; in do_z8530_init()
1145 dev->chanB.dcdcheck = DCD; in do_z8530_init()
1147 /* Reset the chip */ in do_z8530_init()
1148 write_zsreg(&dev->chanA, R9, 0xC0); in do_z8530_init()
1151 write_zsreg(&dev->chanA, R12, 0xAA); in do_z8530_init()
1152 if (read_zsreg(&dev->chanA, R12) != 0xAA) in do_z8530_init()
1153 return -ENODEV; in do_z8530_init()
1154 write_zsreg(&dev->chanA, R12, 0x55); in do_z8530_init()
1155 if (read_zsreg(&dev->chanA, R12) != 0x55) in do_z8530_init()
1156 return -ENODEV; in do_z8530_init()
1158 dev->type = Z8530; in do_z8530_init()
1163 write_zsreg(&dev->chanA, R15, 0x01); in do_z8530_init()
1166 * the chip is enhanced. in do_z8530_init()
1169 if (read_zsreg(&dev->chanA, R15) == 0x01) { in do_z8530_init()
1172 write_zsreg(&dev->chanA, R8, 0); in do_z8530_init()
1173 if (read_zsreg(&dev->chanA, R0) & Tx_BUF_EMP) in do_z8530_init()
1174 dev->type = Z85230; /* Has a FIFO */ in do_z8530_init()
1176 dev->type = Z85C30; /* Z85C30, 1 byte FIFO */ in do_z8530_init()
1184 write_zsreg(&dev->chanA, R15, 0); in do_z8530_init()
1186 /* At this point it looks like the chip is behaving in do_z8530_init()
1189 memcpy(dev->chanA.regs, reg_init, 16); in do_z8530_init()
1190 memcpy(dev->chanB.regs, reg_init, 16); in do_z8530_init()
1196 * z8530_init - Initialise a Z8530 device
1199 * Configure up a Z8530/Z85C30 or Z85230 chip. We check the device
1217 /* Set up the chip level lock */ in z8530_init()
1218 spin_lock_init(&dev->lock); in z8530_init()
1219 dev->chanA.lock = &dev->lock; in z8530_init()
1220 dev->chanB.lock = &dev->lock; in z8530_init()
1222 spin_lock_irqsave(&dev->lock, flags); in z8530_init()
1224 spin_unlock_irqrestore(&dev->lock, flags); in z8530_init()
1231 * z8530_shutdown - Shutdown a Z8530 device
1232 * @dev: The Z8530 chip to shutdown
1235 * reset the chip and wait 100uS to be sure the reset completed. Just
1243 /* Reset the chip */ in z8530_shutdown()
1245 spin_lock_irqsave(&dev->lock, flags); in z8530_shutdown()
1246 dev->chanA.irqs = &z8530_nop; in z8530_shutdown()
1247 dev->chanB.irqs = &z8530_nop; in z8530_shutdown()
1248 write_zsreg(&dev->chanA, R9, 0xC0); in z8530_shutdown()
1249 /* We must lock the udelay, the chip is offlimits here */ in z8530_shutdown()
1251 spin_unlock_irqrestore(&dev->lock, flags); in z8530_shutdown()
1257 * z8530_channel_load - Load channel data
1271 spin_lock_irqsave(c->lock, flags); in z8530_channel_load()
1277 write_zsreg(c, R15, c->regs[15] | 1); in z8530_channel_load()
1280 write_zsreg(c, R15, c->regs[15] & ~1); in z8530_channel_load()
1281 c->regs[reg] = *rtable++; in z8530_channel_load()
1283 c->rx_function = z8530_null_rx; in z8530_channel_load()
1284 c->skb = NULL; in z8530_channel_load()
1285 c->tx_skb = NULL; in z8530_channel_load()
1286 c->tx_next_skb = NULL; in z8530_channel_load()
1287 c->mtu = 1500; in z8530_channel_load()
1288 c->max = 0; in z8530_channel_load()
1289 c->count = 0; in z8530_channel_load()
1290 c->status = read_zsreg(c, R0); in z8530_channel_load()
1291 c->sync = 1; in z8530_channel_load()
1292 write_zsreg(c, R3, c->regs[R3] | RxENABLE); in z8530_channel_load()
1294 spin_unlock_irqrestore(c->lock, flags); in z8530_channel_load()
1300 * z8530_tx_begin - Begin packet transmission
1317 if (c->tx_skb) in z8530_tx_begin()
1320 c->tx_skb = c->tx_next_skb; in z8530_tx_begin()
1321 c->tx_next_skb = NULL; in z8530_tx_begin()
1322 c->tx_ptr = c->tx_next_ptr; in z8530_tx_begin()
1324 if (!c->tx_skb) { in z8530_tx_begin()
1326 if (c->dma_tx) { in z8530_tx_begin()
1328 disable_dma(c->txdma); in z8530_tx_begin()
1331 if (get_dma_residue(c->txdma)) { in z8530_tx_begin()
1332 c->netdevice->stats.tx_dropped++; in z8530_tx_begin()
1333 c->netdevice->stats.tx_fifo_errors++; in z8530_tx_begin()
1337 c->txcount = 0; in z8530_tx_begin()
1339 c->txcount = c->tx_skb->len; in z8530_tx_begin()
1341 if (c->dma_tx) { in z8530_tx_begin()
1349 disable_dma(c->txdma); in z8530_tx_begin()
1354 if (c->dev->type != Z85230) { in z8530_tx_begin()
1358 write_zsreg(c, R10, c->regs[10] & ~ABUNDER); in z8530_tx_begin()
1359 clear_dma_ff(c->txdma); in z8530_tx_begin()
1360 set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr)); in z8530_tx_begin()
1361 set_dma_count(c->txdma, c->txcount); in z8530_tx_begin()
1362 enable_dma(c->txdma); in z8530_tx_begin()
1365 write_zsreg(c, R5, c->regs[R5] | TxENAB); in z8530_tx_begin()
1368 write_zsreg(c, R10, c->regs[10]); in z8530_tx_begin()
1371 while (c->txcount && (read_zsreg(c, R0) & Tx_BUF_EMP)) { in z8530_tx_begin()
1372 write_zsreg(c, R8, *c->tx_ptr++); in z8530_tx_begin()
1373 c->txcount--; in z8530_tx_begin()
1379 netif_wake_queue(c->netdevice); in z8530_tx_begin()
1383 * z8530_tx_done - TX complete callback
1398 if (!c->tx_skb) in z8530_tx_done()
1401 skb = c->tx_skb; in z8530_tx_done()
1402 c->tx_skb = NULL; in z8530_tx_done()
1404 c->netdevice->stats.tx_packets++; in z8530_tx_done()
1405 c->netdevice->stats.tx_bytes += skb->len; in z8530_tx_done()
1410 * z8530_null_rx - Discard a packet
1424 * z8530_rx_done - Receive completion callback
1429 * ESCC mode, but on the older chips we have no choice. We flip to the
1442 if (c->rxdma_on) { in z8530_rx_done()
1446 int ready = c->dma_ready; in z8530_rx_done()
1447 unsigned char *rxb = c->rx_buf[c->dma_num]; in z8530_rx_done()
1454 disable_dma(c->rxdma); in z8530_rx_done()
1455 clear_dma_ff(c->rxdma); in z8530_rx_done()
1456 c->rxdma_on = 0; in z8530_rx_done()
1457 ct = c->mtu - get_dma_residue(c->rxdma); in z8530_rx_done()
1460 c->dma_ready = 0; in z8530_rx_done()
1467 c->dma_num ^= 1; in z8530_rx_done()
1468 set_dma_mode(c->rxdma, DMA_MODE_READ | 0x10); in z8530_rx_done()
1469 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num])); in z8530_rx_done()
1470 set_dma_count(c->rxdma, c->mtu); in z8530_rx_done()
1471 c->rxdma_on = 1; in z8530_rx_done()
1472 enable_dma(c->rxdma); in z8530_rx_done()
1479 * after the flip is done in z8530_rx_done()
1481 netdev_warn(c->netdevice, "DMA flip overrun!\n"); in z8530_rx_done()
1487 * directly into one on a PC - it might be above the 16Mb in z8530_rx_done()
1488 * boundary. Optimisation - we could check to see if we in z8530_rx_done()
1489 * can avoid the copy. Optimisation 2 - make the memcpy in z8530_rx_done()
1495 c->netdevice->stats.rx_dropped++; in z8530_rx_done()
1496 netdev_warn(c->netdevice, "Memory squeeze\n"); in z8530_rx_done()
1500 c->netdevice->stats.rx_packets++; in z8530_rx_done()
1501 c->netdevice->stats.rx_bytes += ct; in z8530_rx_done()
1503 c->dma_ready = 1; in z8530_rx_done()
1506 skb = c->skb; in z8530_rx_done()
1511 * fifo length for this. Thus we want to flip to the new in z8530_rx_done()
1519 ct = c->count; in z8530_rx_done()
1521 c->skb = c->skb2; in z8530_rx_done()
1522 c->count = 0; in z8530_rx_done()
1523 c->max = c->mtu; in z8530_rx_done()
1524 if (c->skb) { in z8530_rx_done()
1525 c->dptr = c->skb->data; in z8530_rx_done()
1526 c->max = c->mtu; in z8530_rx_done()
1528 c->count = 0; in z8530_rx_done()
1529 c->max = 0; in z8530_rx_done()
1533 c->skb2 = dev_alloc_skb(c->mtu); in z8530_rx_done()
1534 if (c->skb2) in z8530_rx_done()
1535 skb_put(c->skb2, c->mtu); in z8530_rx_done()
1537 c->netdevice->stats.rx_packets++; in z8530_rx_done()
1538 c->netdevice->stats.rx_bytes += ct; in z8530_rx_done()
1544 c->rx_function(c, skb); in z8530_rx_done()
1546 c->netdevice->stats.rx_dropped++; in z8530_rx_done()
1547 netdev_err(c->netdevice, "Lost a frame\n"); in z8530_rx_done()
1552 * spans_boundary - Check a packet can be ISA DMA'd
1561 unsigned long a = (unsigned long)skb->data; in spans_boundary()
1563 a ^= (a + skb->len); in spans_boundary()
1570 * z8530_queue_xmit - Queue a packet
1576 * even in DMA mode we do the flip to DMA buffer if needed here
1586 netif_stop_queue(c->netdevice); in z8530_queue_xmit()
1587 if (c->tx_next_skb) in z8530_queue_xmit()
1590 /* PC SPECIFIC - DMA limits */ in z8530_queue_xmit()
1592 * limit, then copy to the flip buffer in z8530_queue_xmit()
1595 if (c->dma_tx && in z8530_queue_xmit()
1596 ((unsigned long)(virt_to_bus(skb->data + skb->len)) >= in z8530_queue_xmit()
1598 /* Send the flip buffer, and flip the flippy bit. in z8530_queue_xmit()
1604 c->tx_next_ptr = c->tx_dma_buf[c->tx_dma_used]; in z8530_queue_xmit()
1605 c->tx_dma_used ^= 1; /* Flip temp buffer */ in z8530_queue_xmit()
1606 skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len); in z8530_queue_xmit()
1608 c->tx_next_ptr = skb->data; in z8530_queue_xmit()
1611 c->tx_next_skb = skb; in z8530_queue_xmit()
1614 spin_lock_irqsave(c->lock, flags); in z8530_queue_xmit()
1616 spin_unlock_irqrestore(c->lock, flags); in z8530_queue_xmit()