Lines Matching +full:big +full:- +full:endian +full:- +full:desc

4  * Copyright (C) 2008-2021, VMware, Inc. All Rights Reserved.
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23  * Maintained by: pv-drivers@vmware.com
57 #define VMXNET3_REG_ALIGN       8	/* All registers are 8-byte aligned. */
107  *	Little Endian layout of bitfields -
113  *	Big Endian layout of bitfields -
119  *	Thus, le32_to_cpu on the dword will allow the big endian driver to read
121  *	bit fields written by big endian driver to format required by device.
375 /* # of tx desc needed for a tx buffer size */
376 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
379 /* max # of tx descs for a non-tso pkt */
383 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
390 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
394 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
398 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
402 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
419  VMXNET3_ERR_NOEOP        = 0x80000000,  /* cannot find the EOP desc of a pkt */
448 	u32		gosBits:2;    /* 32-bit or 64-bit? */
450 	u32		gosBits:2;     /* 32-bit or 64-bit? */
482 	__le32		queueDescLen; /* queue desc. table len in bytes */
497 	__le32		txRingSize;   /* # of tx desc */
498 	__le32		dataRingSize; /* # of data desc */
499 	__le32		compRingSize; /* # of comp desc */
513 	__le32		rxRingSize[2];   /* # of rx desc */
514 	__le32		compRingSize;    /* # of rx comp desc */
738 	/* read-only region for device, read by dev in response to a SET cmd */
748 	/* read-only region for device, read by dev in response to a SET cmd */