4  * Copyright (C) 2008-2021, VMware, Inc. All Rights Reserved.
8  * Free Software Foundation; version 2 of the License and no later version.
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23  * Maintained by: pv-drivers@vmware.com
51 	VMXNET3_REG_RXPROD2	= 0xA00	 /* Rx Producer Index for ring 2 */
57 #define VMXNET3_REG_ALIGN       8	/* All registers are 8-byte aligned. */
107  *	Little Endian layout of bitfields -
109  *	Byte 1 :	oco gen 13.len.8
110  *	Byte 2 : 	5.msscof.0 ext1  dtype
113  *	Big Endian layout of bitfields -
116  *	Byte 2 :	oco gen 13.len.8
132 	u32 gen:1;      /* generation bit */  member
136 	u32 gen:1;      /* generation bit */  member
149 	u32 om:2;       /* offload mode */
153 	u32 om:2;       /* offload mode */
165 #define VMXNET3_OM_CSUM         2
173 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
203 	u32		gen:1;        /* generation bit */  member
210 	u32		gen:1;        /* Generation bit */  member
220 	u32		gen:1;        /* Generation bit */  member
243 	u32		ext1:2;
247 	u32		ext1:2;
272 	u32		gen:1;        /* generation bit */  member
294 	u32		gen:1;        /* generation bit */  member
305 	u32		gen:1;        /* generation bit */  member
327 	u32		gen:1;        /* generation bit */  member
349 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4  2
360 	__le64				qword[2];
376 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
379 /* max # of tx descs for a non-tso pkt */
383 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
390 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
394 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
398 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
402 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
437 	VMXNET3_GOS_BITS_64     = 2,
448 	u32		gosBits:2;    /* 32-bit or 64-bit? */
450 	u32		gosBits:2;     /* 32-bit or 64-bit? */
509 	__le64		rxRingBasePA[2];
513 	__le32		rxRingSize[2];   /* # of rx desc */
526 	VMXNET3_IMM_LAZY   = 2
532 	VMXNET3_IT_MSI  = 2,
559 	__le32		reserved[2];
680 	VMXNET3_COALESCE_STATIC     = 2,
734 	__le64					data[2];
738 	/* read-only region for device, read by dev in response to a SET cmd */
748 	/* read-only region for device, read by dev in response to a SET cmd */
773 #define VMXNET3_ECR_LINK        (1 << 2)
777 /* flip the gen bit of a ring */
778 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)  argument
780 /* only use this if moving the idx won't affect the gen bit */