Lines Matching +full:0 +full:xcd00
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RCR1 0xc012
47 #define PLA_RMS 0xc016
48 #define PLA_RXFIFO_CTRL0 0xc0a0
49 #define PLA_RXFIFO_FULL 0xc0a2
50 #define PLA_RXFIFO_CTRL1 0xc0a4
51 #define PLA_RX_FIFO_FULL 0xc0a6
52 #define PLA_RXFIFO_CTRL2 0xc0a8
53 #define PLA_RX_FIFO_EMPTY 0xc0aa
54 #define PLA_DMY_REG0 0xc0b0
55 #define PLA_FMC 0xc0b4
56 #define PLA_CFG_WOL 0xc0b6
57 #define PLA_TEREDO_CFG 0xc0bc
58 #define PLA_TEREDO_WAKE_BASE 0xc0c4
59 #define PLA_MAR 0xcd00
60 #define PLA_BACKUP 0xd000
61 #define PLA_BDC_CR 0xd1a0
62 #define PLA_TEREDO_TIMER 0xd2cc
63 #define PLA_REALWOW_TIMER 0xd2e8
64 #define PLA_UPHY_TIMER 0xd388
65 #define PLA_SUSPEND_FLAG 0xd38a
66 #define PLA_INDICATE_FALG 0xd38c
67 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
68 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
69 #define PLA_EXTRA_STATUS 0xd398
70 #define PLA_GPHY_CTRL 0xd3ae
71 #define PLA_POL_GPIO_CTRL 0xdc6a
72 #define PLA_EFUSE_DATA 0xdd00
73 #define PLA_EFUSE_CMD 0xdd02
74 #define PLA_LEDSEL 0xdd90
75 #define PLA_LED_FEATURE 0xdd92
76 #define PLA_PHYAR 0xde00
77 #define PLA_BOOT_CTRL 0xe004
78 #define PLA_LWAKE_CTRL_REG 0xe007
79 #define PLA_GPHY_INTR_IMR 0xe022
80 #define PLA_EEE_CR 0xe040
81 #define PLA_EEE_TXTWSYS 0xe04c
82 #define PLA_EEE_TXTWSYS_2P5G 0xe058
83 #define PLA_EEEP_CR 0xe080
84 #define PLA_MAC_PWR_CTRL 0xe0c0
85 #define PLA_MAC_PWR_CTRL2 0xe0ca
86 #define PLA_MAC_PWR_CTRL3 0xe0cc
87 #define PLA_MAC_PWR_CTRL4 0xe0ce
88 #define PLA_WDT6_CTRL 0xe428
89 #define PLA_TCR0 0xe610
90 #define PLA_TCR1 0xe612
91 #define PLA_MTPS 0xe615
92 #define PLA_TXFIFO_CTRL 0xe618
93 #define PLA_TXFIFO_FULL 0xe61a
94 #define PLA_RSTTALLY 0xe800
95 #define PLA_CR 0xe813
96 #define PLA_CRWECR 0xe81c
97 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
98 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
99 #define PLA_CONFIG5 0xe822
100 #define PLA_PHY_PWR 0xe84c
101 #define PLA_OOB_CTRL 0xe84f
102 #define PLA_CPCR 0xe854
103 #define PLA_MISC_0 0xe858
104 #define PLA_MISC_1 0xe85a
105 #define PLA_OCP_GPHY_BASE 0xe86c
106 #define PLA_TALLYCNT 0xe890
107 #define PLA_SFF_STS_7 0xe8de
108 #define PLA_PHYSTATUS 0xe908
109 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
110 #define PLA_USB_CFG 0xe952
111 #define PLA_BP_BA 0xfc26
112 #define PLA_BP_0 0xfc28
113 #define PLA_BP_1 0xfc2a
114 #define PLA_BP_2 0xfc2c
115 #define PLA_BP_3 0xfc2e
116 #define PLA_BP_4 0xfc30
117 #define PLA_BP_5 0xfc32
118 #define PLA_BP_6 0xfc34
119 #define PLA_BP_7 0xfc36
120 #define PLA_BP_EN 0xfc38
122 #define USB_USB2PHY 0xb41e
123 #define USB_SSPHYLINK1 0xb426
124 #define USB_SSPHYLINK2 0xb428
125 #define USB_L1_CTRL 0xb45e
126 #define USB_U2P3_CTRL 0xb460
127 #define USB_CSR_DUMMY1 0xb464
128 #define USB_CSR_DUMMY2 0xb466
129 #define USB_DEV_STAT 0xb808
130 #define USB_CONNECT_TIMER 0xcbf8
131 #define USB_MSC_TIMER 0xcbfc
132 #define USB_BURST_SIZE 0xcfc0
133 #define USB_FW_FIX_EN0 0xcfca
134 #define USB_FW_FIX_EN1 0xcfcc
135 #define USB_LPM_CONFIG 0xcfd8
136 #define USB_ECM_OPTION 0xcfee
137 #define USB_CSTMR 0xcfef /* RTL8153A */
138 #define USB_MISC_2 0xcfff
139 #define USB_ECM_OP 0xd26b
140 #define USB_GPHY_CTRL 0xd284
141 #define USB_SPEED_OPTION 0xd32a
142 #define USB_FW_CTRL 0xd334 /* RTL8153B */
143 #define USB_FC_TIMER 0xd340
144 #define USB_USB_CTRL 0xd406
145 #define USB_PHY_CTRL 0xd408
146 #define USB_TX_AGG 0xd40a
147 #define USB_RX_BUF_TH 0xd40c
148 #define USB_USB_TIMER 0xd428
149 #define USB_RX_EARLY_TIMEOUT 0xd42c
150 #define USB_RX_EARLY_SIZE 0xd42e
151 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
152 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
153 #define USB_TX_DMA 0xd434
154 #define USB_UPT_RXDMA_OWN 0xd437
155 #define USB_UPHY3_MDCMDIO 0xd480
156 #define USB_TOLERANCE 0xd490
157 #define USB_LPM_CTRL 0xd41a
158 #define USB_BMU_RESET 0xd4b0
159 #define USB_BMU_CONFIG 0xd4b4
160 #define USB_U1U2_TIMER 0xd4da
161 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
162 #define USB_RX_AGGR_NUM 0xd4ee
163 #define USB_UPS_CTRL 0xd800
164 #define USB_POWER_CUT 0xd80a
165 #define USB_MISC_0 0xd81a
166 #define USB_MISC_1 0xd81f
167 #define USB_AFE_CTRL2 0xd824
168 #define USB_UPHY_XTAL 0xd826
169 #define USB_UPS_CFG 0xd842
170 #define USB_UPS_FLAGS 0xd848
171 #define USB_WDT1_CTRL 0xe404
172 #define USB_WDT11_CTRL 0xe43c
183 #define USB_BP_8 0xfc38 /* RTL8153B */
184 #define USB_BP_9 0xfc3a
185 #define USB_BP_10 0xfc3c
186 #define USB_BP_11 0xfc3e
187 #define USB_BP_12 0xfc40
188 #define USB_BP_13 0xfc42
189 #define USB_BP_14 0xfc44
190 #define USB_BP_15 0xfc46
191 #define USB_BP2_EN 0xfc48
194 #define OCP_ALDPS_CONFIG 0x2010
195 #define OCP_EEE_CONFIG1 0x2080
196 #define OCP_EEE_CONFIG2 0x2092
197 #define OCP_EEE_CONFIG3 0x2094
198 #define OCP_BASE_MII 0xa400
199 #define OCP_EEE_AR 0xa41a
200 #define OCP_EEE_DATA 0xa41c
201 #define OCP_PHY_STATUS 0xa420
202 #define OCP_NCTL_CFG 0xa42c
203 #define OCP_POWER_CFG 0xa430
204 #define OCP_EEE_CFG 0xa432
205 #define OCP_SRAM_ADDR 0xa436
206 #define OCP_SRAM_DATA 0xa438
207 #define OCP_DOWN_SPEED 0xa442
208 #define OCP_EEE_ABLE 0xa5c4
209 #define OCP_EEE_ADV 0xa5d0
210 #define OCP_EEE_LPABLE 0xa5d2
211 #define OCP_10GBT_CTRL 0xa5d4
212 #define OCP_10GBT_STAT 0xa5d6
213 #define OCP_EEE_ADV2 0xa6d4
214 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
215 #define OCP_PHY_PATCH_STAT 0xb800
216 #define OCP_PHY_PATCH_CMD 0xb820
217 #define OCP_PHY_LOCK 0xb82e
218 #define OCP_ADC_IOFFSET 0xbcfc
219 #define OCP_ADC_CFG 0xbc06
220 #define OCP_SYSCLK_CFG 0xc416
223 #define SRAM_GREEN_CFG 0x8011
224 #define SRAM_LPF_CFG 0x8012
225 #define SRAM_GPHY_FW_VER 0x801e
226 #define SRAM_10M_AMP1 0x8080
227 #define SRAM_10M_AMP2 0x8082
228 #define SRAM_IMPEDANCE 0x8084
229 #define SRAM_PHY_LOCK 0xb82e
232 #define RCR_AAP 0x00000001
233 #define RCR_APM 0x00000002
234 #define RCR_AM 0x00000004
235 #define RCR_AB 0x00000008
244 #define RXFIFO_THR1_NORMAL 0x00080002
245 #define RXFIFO_THR1_OOB 0x01800003
248 #define RXFIFO_FULL_MASK 0xfff
251 #define RXFIFO_THR2_FULL 0x00000060
252 #define RXFIFO_THR2_HIGH 0x00000038
253 #define RXFIFO_THR2_OOB 0x0000004a
254 #define RXFIFO_THR2_NORMAL 0x00a0
257 #define RXFIFO_THR3_FULL 0x00000078
258 #define RXFIFO_THR3_HIGH 0x00000048
259 #define RXFIFO_THR3_OOB 0x0000005a
260 #define RXFIFO_THR3_NORMAL 0x0110
263 #define TXFIFO_THR_NORMAL 0x00400008
264 #define TXFIFO_THR_NORMAL2 0x01000008
267 #define ECM_ALDPS 0x0002
270 #define FMC_FCR_MCU_EN 0x0001
273 #define EEEP_CR_EEEP_TX 0x0002
276 #define WDT6_SET_MODE 0x0010
279 #define TCR0_TX_EMPTY 0x0800
280 #define TCR0_AUTO_FIFO 0x0080
283 #define VERSION_MASK 0x7cf0
293 #define TALLY_RESET 0x0001
296 #define CR_RST 0x10
297 #define CR_RE 0x08
298 #define CR_TE 0x04
301 #define CRWECR_NORAML 0x00
302 #define CRWECR_CONFIG 0xc0
305 #define NOW_IS_OOB 0x80
306 #define TXFIFO_EMPTY 0x20
307 #define RXFIFO_EMPTY 0x10
308 #define LINK_LIST_READY 0x02
309 #define DIS_MCU_CLROOB 0x01
313 #define RXDY_GATED_EN 0x0008
316 #define RE_INIT_LL 0x8000
317 #define MCU_BORW_EN 0x4000
320 #define FLOW_CTRL_EN BIT(0)
321 #define CPCR_RX_VLAN 0x0040
324 #define MAGIC_EN 0x0001
327 #define TEREDO_SEL 0x8000
328 #define TEREDO_WAKE_MASK 0x7f00
329 #define TEREDO_RS_EVENT_MASK 0x00fe
330 #define OOB_TEREDO_EN 0x0001
333 #define ALDPS_PROXY_MODE 0x0001
340 #define LINK_ON_WAKE_EN 0x0010
341 #define LINK_OFF_WAKE_EN 0x0008
344 #define LANWAKE_CLR_EN BIT(0)
351 #define BWF_EN 0x0040
352 #define MWF_EN 0x0020
353 #define UWF_EN 0x0010
354 #define LAN_WAKE_EN 0x0002
357 #define LED_MODE_MASK 0x0700
360 #define TX_10M_IDLE_EN 0x0080
361 #define PFM_PWM_SWITCH 0x0040
365 #define D3_CLK_GATED_EN 0x00004000
366 #define MCU_CLK_RATIO 0x07010f07
367 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
368 #define ALDPS_SPDWN_RATIO 0x0f87
371 #define EEE_SPDWN_RATIO 0x8007
373 #define EEE_SPDWN_RATIO_MASK 0xff
377 #define PKT_AVAIL_SPDWN_EN 0x0100
378 #define SUSPEND_SPDWN_EN 0x0004
379 #define U1U2_SPDWN_EN 0x0002
380 #define L1_SPDWN_EN 0x0001
383 #define PWRSAVE_SPDWN_EN 0x1000
384 #define RXDV_SPDWN_EN 0x0800
385 #define TX10MIDLE_EN 0x0100
387 #define TP100_SPDWN_EN 0x0020
388 #define TP500_SPDWN_EN 0x0010
389 #define TP1000_SPDWN_EN 0x0008
390 #define EEE_SPDWN_EN 0x0001
393 #define GPHY_STS_MSK 0x0001
394 #define SPEED_DOWN_MSK 0x0002
395 #define SPDWN_RXDV_MSK 0x0004
396 #define SPDWN_LINKCHG_MSK 0x0008
399 #define PHYAR_FLAG 0x80000000
402 #define EEE_RX_EN 0x0001
403 #define EEE_TX_EN 0x0002
406 #define AUTOLOAD_DONE 0x0002
412 #define LINK_CHG_EVENT BIT(0)
415 #define UPCOMING_RUNTIME_D3 BIT(0)
418 #define DEBUG_OE BIT(0)
419 #define DEBUG_LTSSM 0x0082
425 #define POLL_LINK_CHG BIT(0)
435 #define USB2PHY_SUSPEND 0x0001
436 #define USB2PHY_L1 0x0002
442 #define pwd_dn_scale_mask 0x3ffe
446 #define DYNAMIC_BURST 0x0001
449 #define EP4_FULL_FC 0x0001
452 #define STAT_SPEED_MASK 0x0006
453 #define STAT_SPEED_HIGH 0x0000
454 #define STAT_SPEED_FULL 0x0002
463 #define LPM_U1U2_EN BIT(0)
466 #define TX_AGG_MAX_THRESHOLD 0x03
469 #define RX_THR_SUPPER 0x0c350180
470 #define RX_THR_HIGH 0x7a120180
471 #define RX_THR_SLOW 0xffff0180
472 #define RX_THR_B 0x00010001
475 #define TEST_MODE_DISABLE 0x00000001
476 #define TX_SIZE_ADJUST1 0x00000100
479 #define BMU_RESET_EP_IN 0x01
480 #define BMU_RESET_EP_OUT 0x02
486 #define OWN_UPDATE BIT(0)
493 #define RX_AGGR_NUM_MASK 0x1ff
496 #define POWER_CUT 0x0100
499 #define RESUME_INDICATE 0x0001
505 #define FORCE_SUPER BIT(0)
508 #define UPS_FORCE_PWR_DOWN BIT(0)
511 #define EN_ALL_SPEED BIT(0)
532 #define RX_AGG_DISABLE 0x0010
533 #define RX_ZERO_EN 0x0080
536 #define U2P3_ENABLE 0x0001
540 #define PWR_EN 0x0001
541 #define PHASE2_EN 0x0008
546 #define PCUT_STATUS 0x0001
554 #define WTD1_EN BIT(0)
557 #define TIMER11_EN 0x0001
561 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
563 #define LPM_TIMER_MASK 0x0c
564 #define LPM_TIMER_500MS 0x04 /* 500 ms */
565 #define LPM_TIMER_500US 0x0c /* 500 us */
566 #define ROK_EXIT_LPM 0x02
569 #define SEN_VAL_MASK 0xf800
570 #define SEN_VAL_NORMAL 0xa000
571 #define SEL_RXIDLE 0x0100
577 #define SAW_CNT_1MS_MASK 0x0fff
581 #define UPS_FLAGS_R_TUNE BIT(0)
586 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
612 #define ENPWRSAVE 0x8000
613 #define ENPDNPS 0x0200
614 #define LINKENA 0x0100
615 #define DIS_SDSAVE 0x0010
618 #define PHY_STAT_MASK 0x0007
627 #define EEE_CLKDIV_EN 0x8000
628 #define EN_ALDPS 0x0004
629 #define EN_10M_PLLOFF 0x0001
632 #define RG_TXLPI_MSK_HFDUP 0x8000
633 #define RG_MATCLR_EN 0x4000
634 #define EEE_10_CAP 0x2000
635 #define EEE_NWAY_EN 0x1000
636 #define TX_QUIET_EN 0x0200
637 #define RX_QUIET_EN 0x0100
638 #define sd_rise_time_mask 0x0070
640 #define RG_RXLPI_MSK_HFDUP 0x0008
641 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
644 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
645 #define RG_DACQUIET_EN 0x0400
646 #define RG_LDVQUIET_EN 0x0200
647 #define RG_CKRSEL 0x0020
648 #define RG_EEEPRG_EN 0x0010
651 #define fast_snr_mask 0xff80
652 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
653 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
654 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
658 #define FUN_ADDR 0x0000
659 #define FUN_DATA 0x4000
660 /* bit[4:0] device addr */
663 #define CTAP_SHORT_EN 0x0040
664 #define EEE10_EN 0x0010
671 #define EN_10M_BGOFF 0x0080
677 #define TXDIS_STATE 0x01
678 #define ABD_STATE 0x02
687 #define PATCH_LOCK BIT(0)
690 #define CKADSEL_L 0x0100
691 #define ADC_EN 0x0080
692 #define EN_EMI_L 0x0040
703 #define LPF_AUTO_TUNE 0x8000
706 #define GDAC_IB_UPALL 0x0008
709 #define AMP_DN 0x0200
712 #define RX_DRIVING_MASK 0x6000
715 #define PHY_PATCH_LOCK 0x0001
718 #define AD_MASK 0xfee0
719 #define BND_MASK 0x0004
720 #define BD_MASK 0x0001
721 #define EFUSE 0xcfdb
722 #define PASS_THRU_MASK 0x1
724 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
732 _1000bps = 0x10,
733 _100bps = 0x08,
734 _10bps = 0x04,
735 LINK_STATUS = 0x02,
736 FULL_DUP = 0x01,
751 #define INTR_LINK 0x0004
762 RTL8152_UNPLUG = 0,
773 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
774 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
794 #define RX_LEN_MASK 0x7fff
820 #define GTTCPHO_MAX 0x7fU
821 #define TX_LEN_MAX 0x3ffffU
829 #define MSS_MAX 0x7ffU
831 #define TCPHO_MAX 0x7ffU
975 FW_FLAGS_USB = 0,
989 FW_FIXUP_AND = 0,
1132 RTL_FW_END = 0,
1150 RTL_VER_UNKNOWN = 0,
1173 TX_CSUM_SUCCESS = 0,
1178 #define RTL_ADVERTISED_10_HALF BIT(0)
1207 if (ret < 0) in get_registers()
1208 memset(data, 0xff, size); in get_registers()
1248 int ret = 0; in generic_ocp_read()
1257 if ((u32)index + (u32)size > 0xffff) in generic_ocp_read()
1263 if (ret < 0) in generic_ocp_read()
1271 if (ret < 0) in generic_ocp_read()
1276 size = 0; in generic_ocp_read()
1301 if ((u32)index + (u32)size > 0xffff) in generic_ocp_write()
1309 if (ret < 0) in generic_ocp_write()
1324 if (ret < 0) in generic_ocp_write()
1334 if (ret < 0) in generic_ocp_write()
1339 size = 0; in generic_ocp_write()
1346 if (ret < 0) in generic_ocp_write()
1405 data &= 0xffff; in ocp_read_word()
1412 u32 mask = 0xffff; in ocp_write_word()
1443 data &= 0xff; in ocp_read_byte()
1450 u32 mask = 0xff; in ocp_write_byte()
1473 ocp_base = addr & 0xf000; in ocp_reg_read()
1479 ocp_index = (addr & 0x0fff) | 0xb000; in ocp_reg_read()
1487 ocp_base = addr & 0xf000; in ocp_reg_write()
1493 ocp_index = (addr & 0x0fff) | 0xb000; in ocp_reg_write()
1568 if (ret < 0) in __rtl8152_set_mac_address()
1612 mac_strlen = 0x16; in vendor_mac_passthru_addr_read()
1616 if ((ocp_data & AD_MASK) == 0x1000) { in vendor_mac_passthru_addr_read()
1627 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { in vendor_mac_passthru_addr_read()
1636 mac_strlen = 0x17; in vendor_mac_passthru_addr_read()
1651 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || in vendor_mac_passthru_addr_read()
1652 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { in vendor_mac_passthru_addr_read()
1658 if (!(ret == 0 && is_valid_ether_addr(buf))) { in vendor_mac_passthru_addr_read()
1682 if (ret < 0) { in determine_ethernet_addr()
1690 if (ret < 0) in determine_ethernet_addr()
1696 if (ret < 0) { in determine_ethernet_addr()
1705 return 0; in determine_ethernet_addr()
1718 if (ret < 0) in set_ethernet_addr()
1761 case 0: in read_bulk_callback()
1775 urb->actual_length = 0; in read_bulk_callback()
1862 case 0: /* success */ in intr_callback()
1883 if (INTR_LINK & __le16_to_cpu(d[0])) { in intr_callback()
1886 schedule_delayed_work(&tp->schedule, 0); in intr_callback()
1892 schedule_delayed_work(&tp->schedule, 0); in intr_callback()
1946 rx_agg->urb = usb_alloc_urb(0, mflags); in alloc_rx_agg()
1984 for (i = 0; i < RTL8152_MAX_TX; i++) { in free_all_mem()
2017 atomic_set(&tp->rx_count, 0); in alloc_all_mem()
2019 for (i = 0; i < RTL8152_MAX_RX; i++) { in alloc_all_mem()
2024 for (i = 0; i < RTL8152_MAX_TX; i++) { in alloc_all_mem()
2040 urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
2055 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
2068 return 0; in alloc_all_mem()
2123 if (skb_checksum_help(skb) < 0) in r8152_csum_workaround()
2153 swab16(opts2 & 0xffff)); in rtl_rx_vlan_tag()
2160 u32 opts1, opts2 = 0; in r8152_tx_csum()
2170 "Invalid transport offset 0x%x for TSO\n", in r8152_tx_csum()
2182 if (skb_cow_head(skb, 0)) { in r8152_tx_csum()
2202 "Invalid transport offset 0x%x\n", in r8152_tx_csum()
2253 agg->skb_num = 0; in r8152_tx_agg_fill()
2254 agg->skb_len = 0; in r8152_tx_agg_fill()
2289 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { in r8152_tx_agg_fill()
2325 if (ret < 0) in r8152_tx_agg_fill()
2333 if (ret < 0) in r8152_tx_agg_fill()
2413 int ret = 0, work_done = 0; in rx_bottom()
2446 int len_used = 0; in rx_bottom()
2454 if (urb->status != 0 || urb->actual_length < ETH_ZLEN) in rx_bottom()
2501 skb_add_rx_frag(skb, 0, agg->page, in rx_bottom()
2544 urb->actual_length = 0; in rx_bottom()
2593 } while (res == 0); in tx_bottom()
2642 return 0; in r8152_submit_rx()
2656 urb->actual_length = 0; in r8152_submit_rx()
2705 schedule_delayed_work(&tp->schedule, 0); in rtl8152_set_rx_mode()
2725 mc_filter[1] = 0xffffffff; in _rtl8152_set_rx_mode()
2726 mc_filter[0] = 0xffffffff; in _rtl8152_set_rx_mode()
2731 mc_filter[1] = 0xffffffff; in _rtl8152_set_rx_mode()
2732 mc_filter[0] = 0xffffffff; in _rtl8152_set_rx_mode()
2736 mc_filter[1] = 0; in _rtl8152_set_rx_mode()
2737 mc_filter[0] = 0; in _rtl8152_set_rx_mode()
2746 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); in _rtl8152_set_rx_mode()
2747 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); in _rtl8152_set_rx_mode()
2782 schedule_delayed_work(&tp->schedule, 0); in rtl8152_start_xmit()
2842 for (i = 0; i < 1000; i++) { in rtl8152_nic_reset()
2898 int ret = 0, i = 0; in rtl_start_rx()
2919 } else if (unlikely(ret < 0)) { in rtl_start_rx()
2973 return 0; in rtl_stop_rx()
3027 return 0; in rtl_enable()
3164 for (i = 0; i < RTL8152_MAX_TX; i++) in rtl_disable()
3169 for (i = 0; i < 1000; i++) { in rtl_disable()
3176 for (i = 0; i < 1000; i++) { in rtl_disable()
3251 if (ret < 0) in rtl8152_set_features()
3276 u32 wolopts = 0; in __rtl_get_wol()
3354 0x0403); in r8156_mac_clk_spd()
3358 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ in r8156_mac_clk_spd()
3372 memset(u1u2, 0xff, sizeof(u1u2)); in r8153_u1u2en()
3374 memset(u1u2, 0x00, sizeof(u1u2)); in r8153_u1u2en()
3406 u32 ups_flags = 0; in r8153b_ups_flags()
3481 u32 ups_flags = 0; in r8156_ups_flags()
3512 ups_flags |= ups_flags_speed(0); in r8156_ups_flags()
3547 ups_flags |= 0 << 5; in r8156_ups_flags()
3552 case 0: in r8156_ups_flags()
3578 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ in r8153b_green_en()
3579 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ in r8153b_green_en()
3580 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ in r8153b_green_en()
3582 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ in r8153b_green_en()
3583 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ in r8153b_green_en()
3584 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ in r8153b_green_en()
3595 for (i = 0; i < 500; i++) { in r8153_phy_status()
3638 for (i = 0; i < 500; i++) { in r8153b_ups_en()
3678 for (i = 0; i < 500; i++) { in r8153c_ups_en()
3931 /* The bit 0 ~ 7 are relative with teredo settings. They are in r8153_teredo_off()
3934 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); in r8153_teredo_off()
3939 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); in r8153_teredo_off()
3940 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); in r8153_teredo_off()
3966 ocp_write_byte(tp, type, PLA_BP_EN, 0); in rtl_clear_bp()
3969 ocp_write_word(tp, type, USB_BP2_EN, 0); in rtl_clear_bp()
3971 ocp_write_word(tp, type, USB_BP_8, 0); in rtl_clear_bp()
3972 ocp_write_word(tp, type, USB_BP_9, 0); in rtl_clear_bp()
3973 ocp_write_word(tp, type, USB_BP_10, 0); in rtl_clear_bp()
3974 ocp_write_word(tp, type, USB_BP_11, 0); in rtl_clear_bp()
3975 ocp_write_word(tp, type, USB_BP_12, 0); in rtl_clear_bp()
3976 ocp_write_word(tp, type, USB_BP_13, 0); in rtl_clear_bp()
3977 ocp_write_word(tp, type, USB_BP_14, 0); in rtl_clear_bp()
3978 ocp_write_word(tp, type, USB_BP_15, 0); in rtl_clear_bp()
3989 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0); in rtl_clear_bp()
3991 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0); in rtl_clear_bp()
3992 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0); in rtl_clear_bp()
3993 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0); in rtl_clear_bp()
3994 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0); in rtl_clear_bp()
3995 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0); in rtl_clear_bp()
3996 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0); in rtl_clear_bp()
3997 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0); in rtl_clear_bp()
3998 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0); in rtl_clear_bp()
4000 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); in rtl_clear_bp()
4005 ocp_write_word(tp, type, PLA_BP_0, 0); in rtl_clear_bp()
4006 ocp_write_word(tp, type, PLA_BP_1, 0); in rtl_clear_bp()
4007 ocp_write_word(tp, type, PLA_BP_2, 0); in rtl_clear_bp()
4008 ocp_write_word(tp, type, PLA_BP_3, 0); in rtl_clear_bp()
4009 ocp_write_word(tp, type, PLA_BP_4, 0); in rtl_clear_bp()
4010 ocp_write_word(tp, type, PLA_BP_5, 0); in rtl_clear_bp()
4011 ocp_write_word(tp, type, PLA_BP_6, 0); in rtl_clear_bp()
4012 ocp_write_word(tp, type, PLA_BP_7, 0); in rtl_clear_bp()
4016 ocp_write_word(tp, type, PLA_BP_BA, 0); in rtl_clear_bp()
4027 check = 0; in rtl_phy_patch_request()
4034 for (i = 0; wait && i < 5000; i++) { in rtl_phy_patch_request()
4049 return 0; in rtl_phy_patch_request()
4061 sram_write(tp, 0x0000, 0x0000); in rtl_patch_key_set()
4067 sram_write(tp, key_addr, 0x0000); in rtl_patch_key_set()
4081 return 0; in rtl_pre_ram_code()
4086 rtl_patch_key_set(tp, key_addr, 0); in rtl_post_ram_code()
4092 return 0; in rtl_post_ram_code()
4135 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) { in rtl8152_is_fw_phy_speed_up_ok()
4261 fw_reg = 0xa014; in rtl8152_is_fw_phy_nc_ok()
4262 ba_reg = 0xa012; in rtl8152_is_fw_phy_nc_ok()
4263 patch_en_addr = 0xa01a; in rtl8152_is_fw_phy_nc_ok()
4264 mode_reg = 0xb820; in rtl8152_is_fw_phy_nc_ok()
4265 bp_start = 0xa000; in rtl8152_is_fw_phy_nc_ok()
4340 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
4342 bp_en_addr = 0; in rtl8152_is_fw_mac_ok()
4356 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
4363 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
4378 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
4391 fw_reg = 0xe600; in rtl8152_is_fw_mac_ok()
4476 alg = crypto_alloc_shash("sha256", 0, 0); in rtl8152_fw_verify_checksum()
4518 unsigned long fw_flags = 0; in rtl8152_check_firmware()
4793 return 0; in rtl8152_check_firmware()
4828 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB); in rtl_ram_code_speed_up()
4837 for (i = 0; i < 1000; i++) { in rtl_ram_code_speed_up()
4866 return 0; in rtl8152_fw_phy_ver()
4912 for (i = 0; i < num; i++) in rtl8152_fw_phy_union_apply()
4922 for (i = 0; i < num; i++) in rtl8152_fw_phy_union_apply()
4926 for (i = 0; i < num; i++) in rtl8152_fw_phy_union_apply()
4952 for (i = 0; i < num; i++) in rtl8152_fw_phy_nc_apply()
4960 for (i = 0; i < num; i++) { in rtl8152_fw_phy_nc_apply()
5011 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data, in rtl8152_fw_mac_apply()
5019 for (i = 0; i < bp_num; i++) { in rtl8152_fw_mac_apply()
5042 u16 key_addr = 0; in rtl8152_apply_firmware()
5131 rc = 0; in rtl8152_request_firmware()
5136 if (rc < 0) in rtl8152_request_firmware()
5140 if (rc < 0) in rtl8152_request_firmware()
5180 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); in r8152_mmd_read()
5189 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); in r8152_mmd_write()
5273 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in rtl_eee_enable()
5288 ocp_reg_write(tp, OCP_EEE_ADV, 0); in rtl_eee_enable()
5301 ocp_reg_write(tp, OCP_EEE_ADV, 0); in rtl_eee_enable()
5342 for (i = 0; i < 1000; i++) { in wait_oob_link_list_ready()
5356 for (i = 0; i < 100; i++) { in r8156b_wait_loading_flash()
5375 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); in r8152b_exit_oob()
5476 for (i = 0; i < 104; i++) { in r8153_pre_firmware_1()
5484 return 0; in r8153_pre_firmware_1()
5496 return 0; in r8153_post_firmware_1()
5509 return 0; in r8153_pre_firmware_2()
5519 ocp_data |= BIT(0); in r8153_post_firmware_2()
5537 return 0; in r8153_post_firmware_2()
5552 return 0; in r8153_post_firmware_3()
5561 return 0; in r8153b_pre_firmware_1()
5572 ocp_data |= BIT(0); in r8153b_post_firmware_1()
5588 return 0; in r8153b_post_firmware_1()
5603 return 0; in r8153c_post_firmware_1()
5615 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); in r8156a_post_firmware_1()
5616 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9); in r8156a_post_firmware_1()
5618 return 0; in r8156a_post_firmware_1()
5634 for (i = 0; i < 20; i++) { in r8153_aldps_en()
5636 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) in r8153_aldps_en()
5673 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); in r8153_hw_phy_cfg()
5680 sram_write(tp, SRAM_LPF_CFG, 0xf70f); in r8153_hw_phy_cfg()
5683 sram_write(tp, SRAM_10M_AMP1, 0x00af); in r8153_hw_phy_cfg()
5684 sram_write(tp, SRAM_10M_AMP2, 0x0208); in r8153_hw_phy_cfg()
5738 data = r8153_phy_status(tp, 0); in r8153b_hw_phy_cfg()
5765 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake in r8153b_hw_phy_cfg()
5769 ocp_data = r8152_efuse_read(tp, 0x7d); in r8153b_hw_phy_cfg()
5770 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); in r8153b_hw_phy_cfg()
5771 if (data != 0xffff) in r8153b_hw_phy_cfg()
5775 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] in r8153b_hw_phy_cfg()
5778 ocp_data = ocp_reg_read(tp, 0xc426); in r8153b_hw_phy_cfg()
5779 ocp_data &= 0x3fff; in r8153b_hw_phy_cfg()
5807 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); in r8153b_hw_phy_cfg()
5919 * type. Set it to zero. bits[7:0] are the W1C bits about in r8153_enter_oob()
5922 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); in r8153_enter_oob()
5978 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); in rtl8156_enable()
5980 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); in rtl8156_enable()
5983 /* USB 0xb45e[3:0] l1_nyet_hird */ in rtl8156_enable()
5985 ocp_data &= ~0xf; in rtl8156_enable()
5987 ocp_data |= 0xf; in rtl8156_enable()
5989 ocp_data |= 0x1; in rtl8156_enable()
6026 ocp_data &= ~0xf; in rtl8156b_enable()
6028 ocp_data |= 0xf; in rtl8156b_enable()
6030 ocp_data |= 0x1; in rtl8156b_enable()
6048 int ret = 0; in rtl8152_set_speed()
6088 tp->mii.full_duplex = 0; in rtl8152_set_speed()
6163 tp->mii.force_media = 0; in rtl8152_set_speed()
6174 for (i = 0; i < 50; i++) { in rtl8152_set_speed()
6176 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) in rtl8152_set_speed()
6374 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02); in rtl8153c_up()
6375 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08); in rtl8153c_up()
6491 ocp_data |= 0x08; in rtl8156_up()
6502 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); in rtl8156_up()
6542 * type. Set it to zero. bits[7:0] are the W1C bits about in rtl8156_down()
6545 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); in rtl8156_down()
6565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); in rtl8152_in_nway()
6566 tp->ocp_base = 0x2000; in rtl8152_in_nway()
6567 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ in rtl8152_in_nway()
6568 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); in rtl8152_in_nway()
6571 if (nway_state & 0xc000) in rtl8152_in_nway()
6579 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; in rtl8153_in_nway()
6634 if (usb_autopm_get_interface(tp->intf) < 0) in rtl_work_func_t()
6641 schedule_delayed_work(&tp->schedule, 0); in rtl_work_func_t()
6673 if (usb_autopm_get_interface(tp->intf) < 0) in rtl_hw_phy_work_func_t()
6729 int res = 0; in rtl8152_open()
6741 if (res < 0) in rtl8152_open()
6770 return 0; in rtl8152_open()
6784 int res = 0; in rtl8152_close()
6797 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { in rtl8152_close()
6879 for (i = 0; i < 500; i++) { in r8153_init()
6889 data = r8153_phy_status(tp, 0); in r8153_init()
6920 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) in r8153_init()
6927 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) in r8153_init()
6968 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); in r8153_init()
7019 for (i = 0; i < 500; i++) { in r8153b_init()
7029 data = r8153_phy_status(tp, 0); in r8153b_init()
7041 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8153b_init()
7042 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8153b_init()
7071 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { in r8153b_init()
7106 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); in r8153c_init()
7108 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); in r8153c_init()
7110 for (i = 0; i < 500; i++) { in r8153c_init()
7120 data = r8153_phy_status(tp, 0); in r8153c_init()
7132 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8153c_init()
7133 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8153c_init()
7183 data = r8153_phy_status(tp, 0); in r8156_hw_phy_cfg()
7188 data = ocp_reg_read(tp, 0xa468); in r8156_hw_phy_cfg()
7190 ocp_reg_write(tp, 0xa468, data); in r8156_hw_phy_cfg()
7214 data = ocp_reg_read(tp, 0xad40); in r8156_hw_phy_cfg()
7215 data &= ~0x3ff; in r8156_hw_phy_cfg()
7217 ocp_reg_write(tp, 0xad40, data); in r8156_hw_phy_cfg()
7219 data = ocp_reg_read(tp, 0xad4e); in r8156_hw_phy_cfg()
7221 ocp_reg_write(tp, 0xad4e, data); in r8156_hw_phy_cfg()
7222 data = ocp_reg_read(tp, 0xad16); in r8156_hw_phy_cfg()
7223 data &= ~0x3ff; in r8156_hw_phy_cfg()
7224 data |= 0x6; in r8156_hw_phy_cfg()
7225 ocp_reg_write(tp, 0xad16, data); in r8156_hw_phy_cfg()
7226 data = ocp_reg_read(tp, 0xad32); in r8156_hw_phy_cfg()
7227 data &= ~0x3f; in r8156_hw_phy_cfg()
7229 ocp_reg_write(tp, 0xad32, data); in r8156_hw_phy_cfg()
7230 data = ocp_reg_read(tp, 0xac08); in r8156_hw_phy_cfg()
7232 ocp_reg_write(tp, 0xac08, data); in r8156_hw_phy_cfg()
7233 data = ocp_reg_read(tp, 0xac8a); in r8156_hw_phy_cfg()
7236 ocp_reg_write(tp, 0xac8a, data); in r8156_hw_phy_cfg()
7237 data = ocp_reg_read(tp, 0xad18); in r8156_hw_phy_cfg()
7239 ocp_reg_write(tp, 0xad18, data); in r8156_hw_phy_cfg()
7240 data = ocp_reg_read(tp, 0xad1a); in r8156_hw_phy_cfg()
7241 data |= 0x3ff; in r8156_hw_phy_cfg()
7242 ocp_reg_write(tp, 0xad1a, data); in r8156_hw_phy_cfg()
7243 data = ocp_reg_read(tp, 0xad1c); in r8156_hw_phy_cfg()
7244 data |= 0x3ff; in r8156_hw_phy_cfg()
7245 ocp_reg_write(tp, 0xad1c, data); in r8156_hw_phy_cfg()
7247 data = sram_read(tp, 0x80ea); in r8156_hw_phy_cfg()
7248 data &= ~0xff00; in r8156_hw_phy_cfg()
7249 data |= 0xc400; in r8156_hw_phy_cfg()
7250 sram_write(tp, 0x80ea, data); in r8156_hw_phy_cfg()
7251 data = sram_read(tp, 0x80eb); in r8156_hw_phy_cfg()
7252 data &= ~0x0700; in r8156_hw_phy_cfg()
7253 data |= 0x0300; in r8156_hw_phy_cfg()
7254 sram_write(tp, 0x80eb, data); in r8156_hw_phy_cfg()
7255 data = sram_read(tp, 0x80f8); in r8156_hw_phy_cfg()
7256 data &= ~0xff00; in r8156_hw_phy_cfg()
7257 data |= 0x1c00; in r8156_hw_phy_cfg()
7258 sram_write(tp, 0x80f8, data); in r8156_hw_phy_cfg()
7259 data = sram_read(tp, 0x80f1); in r8156_hw_phy_cfg()
7260 data &= ~0xff00; in r8156_hw_phy_cfg()
7261 data |= 0x3000; in r8156_hw_phy_cfg()
7262 sram_write(tp, 0x80f1, data); in r8156_hw_phy_cfg()
7264 data = sram_read(tp, 0x80fe); in r8156_hw_phy_cfg()
7265 data &= ~0xff00; in r8156_hw_phy_cfg()
7266 data |= 0xa500; in r8156_hw_phy_cfg()
7267 sram_write(tp, 0x80fe, data); in r8156_hw_phy_cfg()
7268 data = sram_read(tp, 0x8102); in r8156_hw_phy_cfg()
7269 data &= ~0xff00; in r8156_hw_phy_cfg()
7270 data |= 0x5000; in r8156_hw_phy_cfg()
7271 sram_write(tp, 0x8102, data); in r8156_hw_phy_cfg()
7272 data = sram_read(tp, 0x8015); in r8156_hw_phy_cfg()
7273 data &= ~0xff00; in r8156_hw_phy_cfg()
7274 data |= 0x3300; in r8156_hw_phy_cfg()
7275 sram_write(tp, 0x8015, data); in r8156_hw_phy_cfg()
7276 data = sram_read(tp, 0x8100); in r8156_hw_phy_cfg()
7277 data &= ~0xff00; in r8156_hw_phy_cfg()
7278 data |= 0x7000; in r8156_hw_phy_cfg()
7279 sram_write(tp, 0x8100, data); in r8156_hw_phy_cfg()
7280 data = sram_read(tp, 0x8014); in r8156_hw_phy_cfg()
7281 data &= ~0xff00; in r8156_hw_phy_cfg()
7282 data |= 0xf000; in r8156_hw_phy_cfg()
7283 sram_write(tp, 0x8014, data); in r8156_hw_phy_cfg()
7284 data = sram_read(tp, 0x8016); in r8156_hw_phy_cfg()
7285 data &= ~0xff00; in r8156_hw_phy_cfg()
7286 data |= 0x6500; in r8156_hw_phy_cfg()
7287 sram_write(tp, 0x8016, data); in r8156_hw_phy_cfg()
7288 data = sram_read(tp, 0x80dc); in r8156_hw_phy_cfg()
7289 data &= ~0xff00; in r8156_hw_phy_cfg()
7290 data |= 0xed00; in r8156_hw_phy_cfg()
7291 sram_write(tp, 0x80dc, data); in r8156_hw_phy_cfg()
7292 data = sram_read(tp, 0x80df); in r8156_hw_phy_cfg()
7294 sram_write(tp, 0x80df, data); in r8156_hw_phy_cfg()
7295 data = sram_read(tp, 0x80e1); in r8156_hw_phy_cfg()
7297 sram_write(tp, 0x80e1, data); in r8156_hw_phy_cfg()
7299 data = ocp_reg_read(tp, 0xbf06); in r8156_hw_phy_cfg()
7300 data &= ~0x003f; in r8156_hw_phy_cfg()
7301 data |= 0x0038; in r8156_hw_phy_cfg()
7302 ocp_reg_write(tp, 0xbf06, data); in r8156_hw_phy_cfg()
7304 sram_write(tp, 0x819f, 0xddb6); in r8156_hw_phy_cfg()
7306 ocp_reg_write(tp, 0xbc34, 0x5555); in r8156_hw_phy_cfg()
7307 data = ocp_reg_read(tp, 0xbf0a); in r8156_hw_phy_cfg()
7308 data &= ~0x0e00; in r8156_hw_phy_cfg()
7309 data |= 0x0a00; in r8156_hw_phy_cfg()
7310 ocp_reg_write(tp, 0xbf0a, data); in r8156_hw_phy_cfg()
7312 data = ocp_reg_read(tp, 0xbd2c); in r8156_hw_phy_cfg()
7314 ocp_reg_write(tp, 0xbd2c, data); in r8156_hw_phy_cfg()
7317 data = ocp_reg_read(tp, 0xad16); in r8156_hw_phy_cfg()
7318 data |= 0x3ff; in r8156_hw_phy_cfg()
7319 ocp_reg_write(tp, 0xad16, data); in r8156_hw_phy_cfg()
7320 data = ocp_reg_read(tp, 0xad32); in r8156_hw_phy_cfg()
7321 data &= ~0x3f; in r8156_hw_phy_cfg()
7323 ocp_reg_write(tp, 0xad32, data); in r8156_hw_phy_cfg()
7324 data = ocp_reg_read(tp, 0xac08); in r8156_hw_phy_cfg()
7326 ocp_reg_write(tp, 0xac08, data); in r8156_hw_phy_cfg()
7327 data = ocp_reg_read(tp, 0xacc0); in r8156_hw_phy_cfg()
7328 data &= ~0x3; in r8156_hw_phy_cfg()
7330 ocp_reg_write(tp, 0xacc0, data); in r8156_hw_phy_cfg()
7331 data = ocp_reg_read(tp, 0xad40); in r8156_hw_phy_cfg()
7332 data &= ~0xe7; in r8156_hw_phy_cfg()
7334 ocp_reg_write(tp, 0xad40, data); in r8156_hw_phy_cfg()
7335 data = ocp_reg_read(tp, 0xac14); in r8156_hw_phy_cfg()
7337 ocp_reg_write(tp, 0xac14, data); in r8156_hw_phy_cfg()
7338 data = ocp_reg_read(tp, 0xac80); in r8156_hw_phy_cfg()
7340 ocp_reg_write(tp, 0xac80, data); in r8156_hw_phy_cfg()
7341 data = ocp_reg_read(tp, 0xac5e); in r8156_hw_phy_cfg()
7342 data &= ~0x7; in r8156_hw_phy_cfg()
7344 ocp_reg_write(tp, 0xac5e, data); in r8156_hw_phy_cfg()
7345 ocp_reg_write(tp, 0xad4c, 0x00a8); in r8156_hw_phy_cfg()
7346 ocp_reg_write(tp, 0xac5c, 0x01ff); in r8156_hw_phy_cfg()
7347 data = ocp_reg_read(tp, 0xac8a); in r8156_hw_phy_cfg()
7348 data &= ~0xf0; in r8156_hw_phy_cfg()
7350 ocp_reg_write(tp, 0xac8a, data); in r8156_hw_phy_cfg()
7351 ocp_reg_write(tp, 0xb87c, 0x8157); in r8156_hw_phy_cfg()
7352 data = ocp_reg_read(tp, 0xb87e); in r8156_hw_phy_cfg()
7353 data &= ~0xff00; in r8156_hw_phy_cfg()
7354 data |= 0x0500; in r8156_hw_phy_cfg()
7355 ocp_reg_write(tp, 0xb87e, data); in r8156_hw_phy_cfg()
7356 ocp_reg_write(tp, 0xb87c, 0x8159); in r8156_hw_phy_cfg()
7357 data = ocp_reg_read(tp, 0xb87e); in r8156_hw_phy_cfg()
7358 data &= ~0xff00; in r8156_hw_phy_cfg()
7359 data |= 0x0700; in r8156_hw_phy_cfg()
7360 ocp_reg_write(tp, 0xb87e, data); in r8156_hw_phy_cfg()
7363 ocp_reg_write(tp, 0xb87c, 0x80a2); in r8156_hw_phy_cfg()
7364 ocp_reg_write(tp, 0xb87e, 0x0153); in r8156_hw_phy_cfg()
7365 ocp_reg_write(tp, 0xb87c, 0x809c); in r8156_hw_phy_cfg()
7366 ocp_reg_write(tp, 0xb87e, 0x0153); in r8156_hw_phy_cfg()
7369 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); in r8156_hw_phy_cfg()
7375 sram_write(tp, 0x8257, 0x020f); /* XG PLL */ in r8156_hw_phy_cfg()
7376 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ in r8156_hw_phy_cfg()
7399 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); in r8156_hw_phy_cfg()
7406 data = ocp_reg_read(tp, 0xd068); in r8156_hw_phy_cfg()
7408 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7411 data = sram_read(tp, 0x81a2); in r8156_hw_phy_cfg()
7413 sram_write(tp, 0x81a2, data); in r8156_hw_phy_cfg()
7414 data = ocp_reg_read(tp, 0xb54c); in r8156_hw_phy_cfg()
7415 data &= ~0xff00; in r8156_hw_phy_cfg()
7416 data |= 0xdb00; in r8156_hw_phy_cfg()
7417 ocp_reg_write(tp, 0xb54c, data); in r8156_hw_phy_cfg()
7420 data = ocp_reg_read(tp, 0xa454); in r8156_hw_phy_cfg()
7421 data &= ~BIT(0); in r8156_hw_phy_cfg()
7422 ocp_reg_write(tp, 0xa454, data); in r8156_hw_phy_cfg()
7428 data = ocp_reg_read(tp, 0xad4e); in r8156_hw_phy_cfg()
7430 ocp_reg_write(tp, 0xad4e, data); in r8156_hw_phy_cfg()
7431 data = ocp_reg_read(tp, 0xa86a); in r8156_hw_phy_cfg()
7432 data &= ~BIT(0); in r8156_hw_phy_cfg()
7433 ocp_reg_write(tp, 0xa86a, data); in r8156_hw_phy_cfg()
7437 (ocp_reg_read(tp, 0xd068) & BIT(1))) { in r8156_hw_phy_cfg()
7440 data = ocp_reg_read(tp, 0xd068); in r8156_hw_phy_cfg()
7441 data &= ~0x1f; in r8156_hw_phy_cfg()
7442 data |= 0x1; /* p0 */ in r8156_hw_phy_cfg()
7443 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7444 swap_a = ocp_reg_read(tp, 0xd06a); in r8156_hw_phy_cfg()
7445 data &= ~0x18; in r8156_hw_phy_cfg()
7446 data |= 0x18; /* p3 */ in r8156_hw_phy_cfg()
7447 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7448 swap_b = ocp_reg_read(tp, 0xd06a); in r8156_hw_phy_cfg()
7449 data &= ~0x18; /* p0 */ in r8156_hw_phy_cfg()
7450 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7451 ocp_reg_write(tp, 0xd06a, in r8156_hw_phy_cfg()
7452 (swap_a & ~0x7ff) | (swap_b & 0x7ff)); in r8156_hw_phy_cfg()
7453 data |= 0x18; /* p3 */ in r8156_hw_phy_cfg()
7454 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7455 ocp_reg_write(tp, 0xd06a, in r8156_hw_phy_cfg()
7456 (swap_b & ~0x7ff) | (swap_a & 0x7ff)); in r8156_hw_phy_cfg()
7457 data &= ~0x18; in r8156_hw_phy_cfg()
7458 data |= 0x08; /* p1 */ in r8156_hw_phy_cfg()
7459 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7460 swap_a = ocp_reg_read(tp, 0xd06a); in r8156_hw_phy_cfg()
7461 data &= ~0x18; in r8156_hw_phy_cfg()
7462 data |= 0x10; /* p2 */ in r8156_hw_phy_cfg()
7463 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7464 swap_b = ocp_reg_read(tp, 0xd06a); in r8156_hw_phy_cfg()
7465 data &= ~0x18; in r8156_hw_phy_cfg()
7466 data |= 0x08; /* p1 */ in r8156_hw_phy_cfg()
7467 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7468 ocp_reg_write(tp, 0xd06a, in r8156_hw_phy_cfg()
7469 (swap_a & ~0x7ff) | (swap_b & 0x7ff)); in r8156_hw_phy_cfg()
7470 data &= ~0x18; in r8156_hw_phy_cfg()
7471 data |= 0x10; /* p2 */ in r8156_hw_phy_cfg()
7472 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7473 ocp_reg_write(tp, 0xd06a, in r8156_hw_phy_cfg()
7474 (swap_b & ~0x7ff) | (swap_a & 0x7ff)); in r8156_hw_phy_cfg()
7475 swap_a = ocp_reg_read(tp, 0xbd5a); in r8156_hw_phy_cfg()
7476 swap_b = ocp_reg_read(tp, 0xbd5c); in r8156_hw_phy_cfg()
7477 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) | in r8156_hw_phy_cfg()
7478 ((swap_b & 0x1f) << 8) | in r8156_hw_phy_cfg()
7479 ((swap_b >> 8) & 0x1f)); in r8156_hw_phy_cfg()
7480 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) | in r8156_hw_phy_cfg()
7481 ((swap_a & 0x1f) << 8) | in r8156_hw_phy_cfg()
7482 ((swap_a >> 8) & 0x1f)); in r8156_hw_phy_cfg()
7483 swap_a = ocp_reg_read(tp, 0xbc18); in r8156_hw_phy_cfg()
7484 swap_b = ocp_reg_read(tp, 0xbc1a); in r8156_hw_phy_cfg()
7485 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) | in r8156_hw_phy_cfg()
7486 ((swap_b & 0x1f) << 8) | in r8156_hw_phy_cfg()
7487 ((swap_b >> 8) & 0x1f)); in r8156_hw_phy_cfg()
7488 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) | in r8156_hw_phy_cfg()
7489 ((swap_a & 0x1f) << 8) | in r8156_hw_phy_cfg()
7490 ((swap_a >> 8) & 0x1f)); in r8156_hw_phy_cfg()
7499 data = ocp_reg_read(tp, 0xa428); in r8156_hw_phy_cfg()
7501 ocp_reg_write(tp, 0xa428, data); in r8156_hw_phy_cfg()
7502 data = ocp_reg_read(tp, 0xa5ea); in r8156_hw_phy_cfg()
7503 data &= ~BIT(0); in r8156_hw_phy_cfg()
7504 ocp_reg_write(tp, 0xa5ea, data); in r8156_hw_phy_cfg()
7505 tp->ups_info.lite_mode = 0; in r8156_hw_phy_cfg()
7524 ocp_reg_write(tp, 0xbf86, 0x9000); in r8156b_hw_phy_cfg()
7525 data = ocp_reg_read(tp, 0xc402); in r8156b_hw_phy_cfg()
7527 ocp_reg_write(tp, 0xc402, data); in r8156b_hw_phy_cfg()
7529 ocp_reg_write(tp, 0xc402, data); in r8156b_hw_phy_cfg()
7530 ocp_reg_write(tp, 0xbd86, 0x1010); in r8156b_hw_phy_cfg()
7531 ocp_reg_write(tp, 0xbd88, 0x1010); in r8156b_hw_phy_cfg()
7532 data = ocp_reg_read(tp, 0xbd4e); in r8156b_hw_phy_cfg()
7535 ocp_reg_write(tp, 0xbd4e, data); in r8156b_hw_phy_cfg()
7536 data = ocp_reg_read(tp, 0xbf46); in r8156b_hw_phy_cfg()
7537 data &= ~0xf00; in r8156b_hw_phy_cfg()
7538 data |= 0x700; in r8156b_hw_phy_cfg()
7539 ocp_reg_write(tp, 0xbf46, data); in r8156b_hw_phy_cfg()
7555 data = r8153_phy_status(tp, 0); in r8156b_hw_phy_cfg()
7560 data = ocp_reg_read(tp, 0xa466); in r8156b_hw_phy_cfg()
7561 data &= ~BIT(0); in r8156b_hw_phy_cfg()
7562 ocp_reg_write(tp, 0xa466, data); in r8156b_hw_phy_cfg()
7564 data = ocp_reg_read(tp, 0xa468); in r8156b_hw_phy_cfg()
7566 ocp_reg_write(tp, 0xa468, data); in r8156b_hw_phy_cfg()
7596 data = ocp_reg_read(tp, 0xbc08); in r8156b_hw_phy_cfg()
7598 ocp_reg_write(tp, 0xbc08, data); in r8156b_hw_phy_cfg()
7600 data = sram_read(tp, 0x8fff); in r8156b_hw_phy_cfg()
7601 data &= ~0xff00; in r8156b_hw_phy_cfg()
7602 data |= 0x0400; in r8156b_hw_phy_cfg()
7603 sram_write(tp, 0x8fff, data); in r8156b_hw_phy_cfg()
7605 data = ocp_reg_read(tp, 0xacda); in r8156b_hw_phy_cfg()
7606 data |= 0xff00; in r8156b_hw_phy_cfg()
7607 ocp_reg_write(tp, 0xacda, data); in r8156b_hw_phy_cfg()
7608 data = ocp_reg_read(tp, 0xacde); in r8156b_hw_phy_cfg()
7609 data |= 0xf000; in r8156b_hw_phy_cfg()
7610 ocp_reg_write(tp, 0xacde, data); in r8156b_hw_phy_cfg()
7611 ocp_reg_write(tp, 0xac8c, 0x0ffc); in r8156b_hw_phy_cfg()
7612 ocp_reg_write(tp, 0xac46, 0xb7b4); in r8156b_hw_phy_cfg()
7613 ocp_reg_write(tp, 0xac50, 0x0fbc); in r8156b_hw_phy_cfg()
7614 ocp_reg_write(tp, 0xac3c, 0x9240); in r8156b_hw_phy_cfg()
7615 ocp_reg_write(tp, 0xac4e, 0x0db4); in r8156b_hw_phy_cfg()
7616 ocp_reg_write(tp, 0xacc6, 0x0707); in r8156b_hw_phy_cfg()
7617 ocp_reg_write(tp, 0xacc8, 0xa0d3); in r8156b_hw_phy_cfg()
7618 ocp_reg_write(tp, 0xad08, 0x0007); in r8156b_hw_phy_cfg()
7620 ocp_reg_write(tp, 0xb87c, 0x8560); in r8156b_hw_phy_cfg()
7621 ocp_reg_write(tp, 0xb87e, 0x19cc); in r8156b_hw_phy_cfg()
7622 ocp_reg_write(tp, 0xb87c, 0x8562); in r8156b_hw_phy_cfg()
7623 ocp_reg_write(tp, 0xb87e, 0x19cc); in r8156b_hw_phy_cfg()
7624 ocp_reg_write(tp, 0xb87c, 0x8564); in r8156b_hw_phy_cfg()
7625 ocp_reg_write(tp, 0xb87e, 0x19cc); in r8156b_hw_phy_cfg()
7626 ocp_reg_write(tp, 0xb87c, 0x8566); in r8156b_hw_phy_cfg()
7627 ocp_reg_write(tp, 0xb87e, 0x147d); in r8156b_hw_phy_cfg()
7628 ocp_reg_write(tp, 0xb87c, 0x8568); in r8156b_hw_phy_cfg()
7629 ocp_reg_write(tp, 0xb87e, 0x147d); in r8156b_hw_phy_cfg()
7630 ocp_reg_write(tp, 0xb87c, 0x856a); in r8156b_hw_phy_cfg()
7631 ocp_reg_write(tp, 0xb87e, 0x147d); in r8156b_hw_phy_cfg()
7632 ocp_reg_write(tp, 0xb87c, 0x8ffe); in r8156b_hw_phy_cfg()
7633 ocp_reg_write(tp, 0xb87e, 0x0907); in r8156b_hw_phy_cfg()
7634 ocp_reg_write(tp, 0xb87c, 0x80d6); in r8156b_hw_phy_cfg()
7635 ocp_reg_write(tp, 0xb87e, 0x2801); in r8156b_hw_phy_cfg()
7636 ocp_reg_write(tp, 0xb87c, 0x80f2); in r8156b_hw_phy_cfg()
7637 ocp_reg_write(tp, 0xb87e, 0x2801); in r8156b_hw_phy_cfg()
7638 ocp_reg_write(tp, 0xb87c, 0x80f4); in r8156b_hw_phy_cfg()
7639 ocp_reg_write(tp, 0xb87e, 0x6077); in r8156b_hw_phy_cfg()
7640 ocp_reg_write(tp, 0xb506, 0x01e7); in r8156b_hw_phy_cfg()
7642 ocp_reg_write(tp, 0xb87c, 0x8013); in r8156b_hw_phy_cfg()
7643 ocp_reg_write(tp, 0xb87e, 0x0700); in r8156b_hw_phy_cfg()
7644 ocp_reg_write(tp, 0xb87c, 0x8fb9); in r8156b_hw_phy_cfg()
7645 ocp_reg_write(tp, 0xb87e, 0x2801); in r8156b_hw_phy_cfg()
7646 ocp_reg_write(tp, 0xb87c, 0x8fba); in r8156b_hw_phy_cfg()
7647 ocp_reg_write(tp, 0xb87e, 0x0100); in r8156b_hw_phy_cfg()
7648 ocp_reg_write(tp, 0xb87c, 0x8fbc); in r8156b_hw_phy_cfg()
7649 ocp_reg_write(tp, 0xb87e, 0x1900); in r8156b_hw_phy_cfg()
7650 ocp_reg_write(tp, 0xb87c, 0x8fbe); in r8156b_hw_phy_cfg()
7651 ocp_reg_write(tp, 0xb87e, 0xe100); in r8156b_hw_phy_cfg()
7652 ocp_reg_write(tp, 0xb87c, 0x8fc0); in r8156b_hw_phy_cfg()
7653 ocp_reg_write(tp, 0xb87e, 0x0800); in r8156b_hw_phy_cfg()
7654 ocp_reg_write(tp, 0xb87c, 0x8fc2); in r8156b_hw_phy_cfg()
7655 ocp_reg_write(tp, 0xb87e, 0xe500); in r8156b_hw_phy_cfg()
7656 ocp_reg_write(tp, 0xb87c, 0x8fc4); in r8156b_hw_phy_cfg()
7657 ocp_reg_write(tp, 0xb87e, 0x0f00); in r8156b_hw_phy_cfg()
7658 ocp_reg_write(tp, 0xb87c, 0x8fc6); in r8156b_hw_phy_cfg()
7659 ocp_reg_write(tp, 0xb87e, 0xf100); in r8156b_hw_phy_cfg()
7660 ocp_reg_write(tp, 0xb87c, 0x8fc8); in r8156b_hw_phy_cfg()
7661 ocp_reg_write(tp, 0xb87e, 0x0400); in r8156b_hw_phy_cfg()
7662 ocp_reg_write(tp, 0xb87c, 0x8fca); in r8156b_hw_phy_cfg()
7663 ocp_reg_write(tp, 0xb87e, 0xf300); in r8156b_hw_phy_cfg()
7664 ocp_reg_write(tp, 0xb87c, 0x8fcc); in r8156b_hw_phy_cfg()
7665 ocp_reg_write(tp, 0xb87e, 0xfd00); in r8156b_hw_phy_cfg()
7666 ocp_reg_write(tp, 0xb87c, 0x8fce); in r8156b_hw_phy_cfg()
7667 ocp_reg_write(tp, 0xb87e, 0xff00); in r8156b_hw_phy_cfg()
7668 ocp_reg_write(tp, 0xb87c, 0x8fd0); in r8156b_hw_phy_cfg()
7669 ocp_reg_write(tp, 0xb87e, 0xfb00); in r8156b_hw_phy_cfg()
7670 ocp_reg_write(tp, 0xb87c, 0x8fd2); in r8156b_hw_phy_cfg()
7671 ocp_reg_write(tp, 0xb87e, 0x0100); in r8156b_hw_phy_cfg()
7672 ocp_reg_write(tp, 0xb87c, 0x8fd4); in r8156b_hw_phy_cfg()
7673 ocp_reg_write(tp, 0xb87e, 0xf400); in r8156b_hw_phy_cfg()
7674 ocp_reg_write(tp, 0xb87c, 0x8fd6); in r8156b_hw_phy_cfg()
7675 ocp_reg_write(tp, 0xb87e, 0xff00); in r8156b_hw_phy_cfg()
7676 ocp_reg_write(tp, 0xb87c, 0x8fd8); in r8156b_hw_phy_cfg()
7677 ocp_reg_write(tp, 0xb87e, 0xf600); in r8156b_hw_phy_cfg()
7682 ocp_reg_write(tp, 0xb87c, 0x813d); in r8156b_hw_phy_cfg()
7683 ocp_reg_write(tp, 0xb87e, 0x390e); in r8156b_hw_phy_cfg()
7684 ocp_reg_write(tp, 0xb87c, 0x814f); in r8156b_hw_phy_cfg()
7685 ocp_reg_write(tp, 0xb87e, 0x790e); in r8156b_hw_phy_cfg()
7686 ocp_reg_write(tp, 0xb87c, 0x80b0); in r8156b_hw_phy_cfg()
7687 ocp_reg_write(tp, 0xb87e, 0x0f31); in r8156b_hw_phy_cfg()
7688 data = ocp_reg_read(tp, 0xbf4c); in r8156b_hw_phy_cfg()
7690 ocp_reg_write(tp, 0xbf4c, data); in r8156b_hw_phy_cfg()
7691 data = ocp_reg_read(tp, 0xbcca); in r8156b_hw_phy_cfg()
7693 ocp_reg_write(tp, 0xbcca, data); in r8156b_hw_phy_cfg()
7694 ocp_reg_write(tp, 0xb87c, 0x8141); in r8156b_hw_phy_cfg()
7695 ocp_reg_write(tp, 0xb87e, 0x320e); in r8156b_hw_phy_cfg()
7696 ocp_reg_write(tp, 0xb87c, 0x8153); in r8156b_hw_phy_cfg()
7697 ocp_reg_write(tp, 0xb87e, 0x720e); in r8156b_hw_phy_cfg()
7698 ocp_reg_write(tp, 0xb87c, 0x8529); in r8156b_hw_phy_cfg()
7699 ocp_reg_write(tp, 0xb87e, 0x050e); in r8156b_hw_phy_cfg()
7704 sram_write(tp, 0x816c, 0xc4a0); in r8156b_hw_phy_cfg()
7705 sram_write(tp, 0x8170, 0xc4a0); in r8156b_hw_phy_cfg()
7706 sram_write(tp, 0x8174, 0x04a0); in r8156b_hw_phy_cfg()
7707 sram_write(tp, 0x8178, 0x04a0); in r8156b_hw_phy_cfg()
7708 sram_write(tp, 0x817c, 0x0719); in r8156b_hw_phy_cfg()
7709 sram_write(tp, 0x8ff4, 0x0400); in r8156b_hw_phy_cfg()
7710 sram_write(tp, 0x8ff1, 0x0404); in r8156b_hw_phy_cfg()
7712 ocp_reg_write(tp, 0xbf4a, 0x001b); in r8156b_hw_phy_cfg()
7713 ocp_reg_write(tp, 0xb87c, 0x8033); in r8156b_hw_phy_cfg()
7714 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7715 ocp_reg_write(tp, 0xb87c, 0x8037); in r8156b_hw_phy_cfg()
7716 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7717 ocp_reg_write(tp, 0xb87c, 0x803b); in r8156b_hw_phy_cfg()
7718 ocp_reg_write(tp, 0xb87e, 0xfc32); in r8156b_hw_phy_cfg()
7719 ocp_reg_write(tp, 0xb87c, 0x803f); in r8156b_hw_phy_cfg()
7720 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7721 ocp_reg_write(tp, 0xb87c, 0x8043); in r8156b_hw_phy_cfg()
7722 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7723 ocp_reg_write(tp, 0xb87c, 0x8047); in r8156b_hw_phy_cfg()
7724 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7726 ocp_reg_write(tp, 0xb87c, 0x8145); in r8156b_hw_phy_cfg()
7727 ocp_reg_write(tp, 0xb87e, 0x370e); in r8156b_hw_phy_cfg()
7728 ocp_reg_write(tp, 0xb87c, 0x8157); in r8156b_hw_phy_cfg()
7729 ocp_reg_write(tp, 0xb87e, 0x770e); in r8156b_hw_phy_cfg()
7730 ocp_reg_write(tp, 0xb87c, 0x8169); in r8156b_hw_phy_cfg()
7731 ocp_reg_write(tp, 0xb87e, 0x0d0a); in r8156b_hw_phy_cfg()
7732 ocp_reg_write(tp, 0xb87c, 0x817b); in r8156b_hw_phy_cfg()
7733 ocp_reg_write(tp, 0xb87e, 0x1d0a); in r8156b_hw_phy_cfg()
7735 data = sram_read(tp, 0x8217); in r8156b_hw_phy_cfg()
7736 data &= ~0xff00; in r8156b_hw_phy_cfg()
7737 data |= 0x5000; in r8156b_hw_phy_cfg()
7738 sram_write(tp, 0x8217, data); in r8156b_hw_phy_cfg()
7739 data = sram_read(tp, 0x821a); in r8156b_hw_phy_cfg()
7740 data &= ~0xff00; in r8156b_hw_phy_cfg()
7741 data |= 0x5000; in r8156b_hw_phy_cfg()
7742 sram_write(tp, 0x821a, data); in r8156b_hw_phy_cfg()
7743 sram_write(tp, 0x80da, 0x0403); in r8156b_hw_phy_cfg()
7744 data = sram_read(tp, 0x80dc); in r8156b_hw_phy_cfg()
7745 data &= ~0xff00; in r8156b_hw_phy_cfg()
7746 data |= 0x1000; in r8156b_hw_phy_cfg()
7747 sram_write(tp, 0x80dc, data); in r8156b_hw_phy_cfg()
7748 sram_write(tp, 0x80b3, 0x0384); in r8156b_hw_phy_cfg()
7749 sram_write(tp, 0x80b7, 0x2007); in r8156b_hw_phy_cfg()
7750 data = sram_read(tp, 0x80ba); in r8156b_hw_phy_cfg()
7751 data &= ~0xff00; in r8156b_hw_phy_cfg()
7752 data |= 0x6c00; in r8156b_hw_phy_cfg()
7753 sram_write(tp, 0x80ba, data); in r8156b_hw_phy_cfg()
7754 sram_write(tp, 0x80b5, 0xf009); in r8156b_hw_phy_cfg()
7755 data = sram_read(tp, 0x80bd); in r8156b_hw_phy_cfg()
7756 data &= ~0xff00; in r8156b_hw_phy_cfg()
7757 data |= 0x9f00; in r8156b_hw_phy_cfg()
7758 sram_write(tp, 0x80bd, data); in r8156b_hw_phy_cfg()
7759 sram_write(tp, 0x80c7, 0xf083); in r8156b_hw_phy_cfg()
7760 sram_write(tp, 0x80dd, 0x03f0); in r8156b_hw_phy_cfg()
7761 data = sram_read(tp, 0x80df); in r8156b_hw_phy_cfg()
7762 data &= ~0xff00; in r8156b_hw_phy_cfg()
7763 data |= 0x1000; in r8156b_hw_phy_cfg()
7764 sram_write(tp, 0x80df, data); in r8156b_hw_phy_cfg()
7765 sram_write(tp, 0x80cb, 0x2007); in r8156b_hw_phy_cfg()
7766 data = sram_read(tp, 0x80ce); in r8156b_hw_phy_cfg()
7767 data &= ~0xff00; in r8156b_hw_phy_cfg()
7768 data |= 0x6c00; in r8156b_hw_phy_cfg()
7769 sram_write(tp, 0x80ce, data); in r8156b_hw_phy_cfg()
7770 sram_write(tp, 0x80c9, 0x8009); in r8156b_hw_phy_cfg()
7771 data = sram_read(tp, 0x80d1); in r8156b_hw_phy_cfg()
7772 data &= ~0xff00; in r8156b_hw_phy_cfg()
7773 data |= 0x8000; in r8156b_hw_phy_cfg()
7774 sram_write(tp, 0x80d1, data); in r8156b_hw_phy_cfg()
7775 sram_write(tp, 0x80a3, 0x200a); in r8156b_hw_phy_cfg()
7776 sram_write(tp, 0x80a5, 0xf0ad); in r8156b_hw_phy_cfg()
7777 sram_write(tp, 0x809f, 0x6073); in r8156b_hw_phy_cfg()
7778 sram_write(tp, 0x80a1, 0x000b); in r8156b_hw_phy_cfg()
7779 data = sram_read(tp, 0x80a9); in r8156b_hw_phy_cfg()
7780 data &= ~0xff00; in r8156b_hw_phy_cfg()
7781 data |= 0xc000; in r8156b_hw_phy_cfg()
7782 sram_write(tp, 0x80a9, data); in r8156b_hw_phy_cfg()
7787 data = ocp_reg_read(tp, 0xb896); in r8156b_hw_phy_cfg()
7788 data &= ~BIT(0); in r8156b_hw_phy_cfg()
7789 ocp_reg_write(tp, 0xb896, data); in r8156b_hw_phy_cfg()
7790 data = ocp_reg_read(tp, 0xb892); in r8156b_hw_phy_cfg()
7791 data &= ~0xff00; in r8156b_hw_phy_cfg()
7792 ocp_reg_write(tp, 0xb892, data); in r8156b_hw_phy_cfg()
7793 ocp_reg_write(tp, 0xb88e, 0xc23e); in r8156b_hw_phy_cfg()
7794 ocp_reg_write(tp, 0xb890, 0x0000); in r8156b_hw_phy_cfg()
7795 ocp_reg_write(tp, 0xb88e, 0xc240); in r8156b_hw_phy_cfg()
7796 ocp_reg_write(tp, 0xb890, 0x0103); in r8156b_hw_phy_cfg()
7797 ocp_reg_write(tp, 0xb88e, 0xc242); in r8156b_hw_phy_cfg()
7798 ocp_reg_write(tp, 0xb890, 0x0507); in r8156b_hw_phy_cfg()
7799 ocp_reg_write(tp, 0xb88e, 0xc244); in r8156b_hw_phy_cfg()
7800 ocp_reg_write(tp, 0xb890, 0x090b); in r8156b_hw_phy_cfg()
7801 ocp_reg_write(tp, 0xb88e, 0xc246); in r8156b_hw_phy_cfg()
7802 ocp_reg_write(tp, 0xb890, 0x0c0e); in r8156b_hw_phy_cfg()
7803 ocp_reg_write(tp, 0xb88e, 0xc248); in r8156b_hw_phy_cfg()
7804 ocp_reg_write(tp, 0xb890, 0x1012); in r8156b_hw_phy_cfg()
7805 ocp_reg_write(tp, 0xb88e, 0xc24a); in r8156b_hw_phy_cfg()
7806 ocp_reg_write(tp, 0xb890, 0x1416); in r8156b_hw_phy_cfg()
7807 data = ocp_reg_read(tp, 0xb896); in r8156b_hw_phy_cfg()
7808 data |= BIT(0); in r8156b_hw_phy_cfg()
7809 ocp_reg_write(tp, 0xb896, data); in r8156b_hw_phy_cfg()
7813 data = ocp_reg_read(tp, 0xa86a); in r8156b_hw_phy_cfg()
7814 data |= BIT(0); in r8156b_hw_phy_cfg()
7815 ocp_reg_write(tp, 0xa86a, data); in r8156b_hw_phy_cfg()
7816 data = ocp_reg_read(tp, 0xa6f0); in r8156b_hw_phy_cfg()
7817 data |= BIT(0); in r8156b_hw_phy_cfg()
7818 ocp_reg_write(tp, 0xa6f0, data); in r8156b_hw_phy_cfg()
7820 ocp_reg_write(tp, 0xbfa0, 0xd70d); in r8156b_hw_phy_cfg()
7821 ocp_reg_write(tp, 0xbfa2, 0x4100); in r8156b_hw_phy_cfg()
7822 ocp_reg_write(tp, 0xbfa4, 0xe868); in r8156b_hw_phy_cfg()
7823 ocp_reg_write(tp, 0xbfa6, 0xdc59); in r8156b_hw_phy_cfg()
7824 ocp_reg_write(tp, 0xb54c, 0x3c18); in r8156b_hw_phy_cfg()
7825 data = ocp_reg_read(tp, 0xbfa4); in r8156b_hw_phy_cfg()
7827 ocp_reg_write(tp, 0xbfa4, data); in r8156b_hw_phy_cfg()
7828 data = sram_read(tp, 0x817d); in r8156b_hw_phy_cfg()
7830 sram_write(tp, 0x817d, data); in r8156b_hw_phy_cfg()
7834 data = ocp_reg_read(tp, 0xac46); in r8156b_hw_phy_cfg()
7835 data &= ~0x00f0; in r8156b_hw_phy_cfg()
7836 data |= 0x0090; in r8156b_hw_phy_cfg()
7837 ocp_reg_write(tp, 0xac46, data); in r8156b_hw_phy_cfg()
7838 data = ocp_reg_read(tp, 0xad30); in r8156b_hw_phy_cfg()
7839 data &= ~0x0003; in r8156b_hw_phy_cfg()
7840 data |= 0x0001; in r8156b_hw_phy_cfg()
7841 ocp_reg_write(tp, 0xad30, data); in r8156b_hw_phy_cfg()
7845 ocp_reg_write(tp, 0xb87c, 0x80f5); in r8156b_hw_phy_cfg()
7846 ocp_reg_write(tp, 0xb87e, 0x760e); in r8156b_hw_phy_cfg()
7847 ocp_reg_write(tp, 0xb87c, 0x8107); in r8156b_hw_phy_cfg()
7848 ocp_reg_write(tp, 0xb87e, 0x360e); in r8156b_hw_phy_cfg()
7849 ocp_reg_write(tp, 0xb87c, 0x8551); in r8156b_hw_phy_cfg()
7850 data = ocp_reg_read(tp, 0xb87e); in r8156b_hw_phy_cfg()
7851 data &= ~0xff00; in r8156b_hw_phy_cfg()
7852 data |= 0x0800; in r8156b_hw_phy_cfg()
7853 ocp_reg_write(tp, 0xb87e, data); in r8156b_hw_phy_cfg()
7856 data = ocp_reg_read(tp, 0xbf00); in r8156b_hw_phy_cfg()
7857 data &= ~0xe000; in r8156b_hw_phy_cfg()
7858 data |= 0xa000; in r8156b_hw_phy_cfg()
7859 ocp_reg_write(tp, 0xbf00, data); in r8156b_hw_phy_cfg()
7860 data = ocp_reg_read(tp, 0xbf46); in r8156b_hw_phy_cfg()
7861 data &= ~0x0f00; in r8156b_hw_phy_cfg()
7862 data |= 0x0300; in r8156b_hw_phy_cfg()
7863 ocp_reg_write(tp, 0xbf46, data); in r8156b_hw_phy_cfg()
7866 sram_write(tp, 0x8044, 0x2417); in r8156b_hw_phy_cfg()
7867 sram_write(tp, 0x804a, 0x2417); in r8156b_hw_phy_cfg()
7868 sram_write(tp, 0x8050, 0x2417); in r8156b_hw_phy_cfg()
7869 sram_write(tp, 0x8056, 0x2417); in r8156b_hw_phy_cfg()
7870 sram_write(tp, 0x805c, 0x2417); in r8156b_hw_phy_cfg()
7871 sram_write(tp, 0x8062, 0x2417); in r8156b_hw_phy_cfg()
7872 sram_write(tp, 0x8068, 0x2417); in r8156b_hw_phy_cfg()
7873 sram_write(tp, 0x806e, 0x2417); in r8156b_hw_phy_cfg()
7874 sram_write(tp, 0x8074, 0x2417); in r8156b_hw_phy_cfg()
7875 sram_write(tp, 0x807a, 0x2417); in r8156b_hw_phy_cfg()
7878 data = ocp_reg_read(tp, 0xbf84); in r8156b_hw_phy_cfg()
7879 data &= ~0xe000; in r8156b_hw_phy_cfg()
7880 data |= 0xa000; in r8156b_hw_phy_cfg()
7881 ocp_reg_write(tp, 0xbf84, data); in r8156b_hw_phy_cfg()
7911 data = ocp_reg_read(tp, 0xa428); in r8156b_hw_phy_cfg()
7913 ocp_reg_write(tp, 0xa428, data); in r8156b_hw_phy_cfg()
7914 data = ocp_reg_read(tp, 0xa5ea); in r8156b_hw_phy_cfg()
7915 data &= ~BIT(0); in r8156b_hw_phy_cfg()
7916 ocp_reg_write(tp, 0xa5ea, data); in r8156b_hw_phy_cfg()
7917 tp->ups_info.lite_mode = 0; in r8156b_hw_phy_cfg()
7942 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); in r8156_init()
7950 for (i = 0; i < 500; i++) { in r8156_init()
7960 data = r8153_phy_status(tp, 0); in r8156_init()
7962 data = ocp_reg_read(tp, 0xa468); in r8156_init()
7964 ocp_reg_write(tp, 0xa468, data); in r8156_init()
7978 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8156_init()
7979 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8156_init()
8037 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); in r8156b_init()
8058 for (i = 0; i < 500; i++) { in r8156b_init()
8068 data = r8153_phy_status(tp, 0); in r8156b_init()
8070 data = ocp_reg_read(tp, 0xa468); in r8156b_init()
8072 ocp_reg_write(tp, 0xa468, data); in r8156b_init()
8074 data = ocp_reg_read(tp, 0xa466); in r8156b_init()
8075 data &= ~BIT(0); in r8156b_init()
8076 ocp_reg_write(tp, 0xa466, data); in r8156b_init()
8089 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8156b_init()
8090 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8156b_init()
8158 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) { in rtl_check_vendor_ok()
8201 for (i = 0; i < num_configs; (i++, c++)) { in rtl_vendor_mode()
8204 if (c->desc.bNumInterfaces > 0) in rtl_vendor_mode()
8205 desc = &c->intf_cache[0]->altsetting->desc; in rtl_vendor_mode()
8227 return 0; in rtl8152_pre_reset()
8231 return 0; in rtl8152_pre_reset()
8245 return 0; in rtl8152_pre_reset()
8255 return 0; in rtl8152_post_reset()
8258 if (determine_ethernet_addr(tp, &sa) >= 0) { in rtl8152_post_reset()
8266 return 0; in rtl8152_post_reset()
8285 return 0; in rtl8152_post_reset()
8347 return 0; in rtl8152_runtime_resume()
8363 return 0; in rtl8152_system_resume()
8369 int ret = 0; in rtl8152_runtime_suspend()
8378 u32 rcr = 0; in rtl8152_runtime_suspend()
8443 return 0; in rtl8152_system_suspend()
8486 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); in rtl8152_reset_resume()
8495 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_wol()
8499 wol->supported = 0; in rtl8152_get_wol()
8500 wol->wolopts = 0; in rtl8152_get_wol()
8523 if (ret < 0) in rtl8152_set_wol()
8577 if (ret < 0) in rtl8152_get_link_ksettings()
8612 u32 advertising = 0; in rtl8152_set_link_ksettings()
8616 if (ret < 0) in rtl8152_set_link_ksettings()
8698 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_ethtool_stats()
8705 data[0] = le64_to_cpu(tally.tx_packets); in rtl8152_get_ethtool_stats()
8731 u32 lp, adv, supported = 0; in r8152_get_eee()
8749 return 0; in r8152_get_eee()
8761 return 0; in r8152_set_eee()
8766 u32 lp, adv, supported = 0; in r8153_get_eee()
8784 return 0; in r8153_get_eee()
8799 if (ret < 0) in rtl_ethtool_get_eee()
8826 if (ret < 0) in rtl_ethtool_set_eee()
8849 if (ret < 0) in rtl8152_nway_reset()
8882 return 0; in rtl8152_get_coalesce()
8906 if (ret < 0) in rtl8152_set_coalesce()
8947 return 0; in rtl8152_get_tunable()
8982 return 0; in rtl8152_set_tunable()
9014 return 0; in rtl8152_set_ringparam()
9023 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_pauseparam()
9037 pause->autoneg = 0; in rtl8152_get_pauseparam()
9038 pause->rx_pause = 0; in rtl8152_get_pauseparam()
9039 pause->tx_pause = 0; in rtl8152_get_pauseparam()
9058 u8 cap = 0; in rtl8152_set_pauseparam()
9062 if (ret < 0) in rtl8152_set_pauseparam()
9126 if (res < 0) in rtl8152_ioctl()
9170 return 0; in rtl8152_change_mtu()
9176 if (ret < 0) in rtl8152_change_mtu()
9250 int ret = 0; in rtl_ops_init()
9442 return 0; in rtl_fw_init()
9448 u32 ocp_data = 0; in rtl8152_get_version()
9455 return 0; in rtl8152_get_version()
9457 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), in rtl8152_get_version()
9460 if (ret > 0) in rtl8152_get_version()
9466 case 0x4c00: in rtl8152_get_version()
9469 case 0x4c10: in rtl8152_get_version()
9472 case 0x5c00: in rtl8152_get_version()
9475 case 0x5c10: in rtl8152_get_version()
9478 case 0x5c20: in rtl8152_get_version()
9481 case 0x5c30: in rtl8152_get_version()
9484 case 0x4800: in rtl8152_get_version()
9487 case 0x6000: in rtl8152_get_version()
9490 case 0x6010: in rtl8152_get_version()
9493 case 0x7010: in rtl8152_get_version()
9496 case 0x7020: in rtl8152_get_version()
9499 case 0x7030: in rtl8152_get_version()
9502 case 0x7400: in rtl8152_get_version()
9505 case 0x7410: in rtl8152_get_version()
9508 case 0x6400: in rtl8152_get_version()
9511 case 0x7420: in rtl8152_get_version()
9516 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); in rtl8152_get_version()
9520 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); in rtl8152_get_version()
9550 tp->msg_enable = 0x7FFF; in rtl8152_probe()
9557 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0); in rtl8152_probe()
9558 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0); in rtl8152_probe()
9567 tp->mii.supports_gmii = 0; in rtl8152_probe()
9614 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && in rtl8152_probe()
9656 tp->mii.phy_id_mask = 0x3f; in rtl8152_probe()
9657 tp->mii.reg_num_mask = 0x1f; in rtl8152_probe()
9682 __rtl_set_wol(tp, 0); in rtl8152_probe()
9691 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); in rtl8152_probe()
9702 if (ret != 0) { in rtl8152_probe()
9714 return 0; in rtl8152_probe()
9753 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
9754 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
9755 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
9756 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
9757 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
9758 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
9761 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
9762 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
9763 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
9764 REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
9765 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f),
9766 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062),
9767 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069),
9768 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082),
9769 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205),
9770 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c),
9771 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214),
9772 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e),
9773 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387),
9774 REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
9775 REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff),
9776 REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601),