Lines Matching refs:MDIO_MMD_VEND1
223 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_gettimex64()
225 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
227 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
229 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
231 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
255 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_NSEC_0, in _nxp_c45_ptp_settime64()
257 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_NSEC_1, in _nxp_c45_ptp_settime64()
259 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_SEC_0, in _nxp_c45_ptp_settime64()
261 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_SEC_1, in _nxp_c45_ptp_settime64()
263 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_settime64()
294 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_RATE_ADJ_SUBNS_0, in nxp_c45_ptp_adjfine()
301 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_RATE_ADJ_SUBNS_1, in nxp_c45_ptp_adjfine()
349 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
351 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0); in nxp_c45_get_hwtxts()
359 hwts->sequence_id = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_hwtxts()
361 hwts->nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_hwtxts()
363 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_3); in nxp_c45_get_hwtxts()
543 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
545 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
549 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
551 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_PTP_CONTROL, in nxp_c45_hwtstamp()
559 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
562 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
589 { "phy_symbol_error_cnt", MDIO_MMD_VEND1,
591 { "phy_link_status_drop_cnt", MDIO_MMD_VEND1,
593 { "phy_link_availability_drop_cnt", MDIO_MMD_VEND1,
595 { "phy_link_loss_cnt", MDIO_MMD_VEND1,
597 { "phy_link_failure_cnt", MDIO_MMD_VEND1,
599 { "r_good_frame_cnt", MDIO_MMD_VEND1,
601 { "r_bad_frame_cnt", MDIO_MMD_VEND1,
603 { "r_rxer_frame_cnt", MDIO_MMD_VEND1,
605 { "rx_preamble_count", MDIO_MMD_VEND1,
607 { "tx_preamble_count", MDIO_MMD_VEND1,
609 { "rx_ipg_length", MDIO_MMD_VEND1,
611 { "tx_ipg_length", MDIO_MMD_VEND1,
650 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable()
655 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable()
657 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable()
659 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, in nxp_c45_config_enable()
667 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_start_op()
674 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
677 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
688 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_STATUS); in nxp_c45_handle_interrupt()
690 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt()
700 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_IRQ_STATUS); in nxp_c45_handle_interrupt()
715 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_soft_reset()
720 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in nxp_c45_soft_reset()
728 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST, in nxp_c45_cable_test_start()
738 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST); in nxp_c45_cable_test_get_status()
765 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST, in nxp_c45_cable_test_get_status()
841 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY); in nxp_c45_get_sqi()
883 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE); in nxp_c45_disable_delays()
884 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE); in nxp_c45_disable_delays()
897 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
900 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
907 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
910 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
959 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); in nxp_c45_set_phy_mode()
968 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
979 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
992 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1000 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1008 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1016 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1041 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init()
1042 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init()
1044 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, in nxp_c45_config_init()
1047 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER, in nxp_c45_config_init()
1049 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT, in nxp_c45_config_init()
1051 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT, in nxp_c45_config_init()
1053 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH, in nxp_c45_config_init()
1055 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH, in nxp_c45_config_init()
1064 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK_PERIOD, in nxp_c45_config_init()
1066 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_HW_LTC_LOCK_CTRL, in nxp_c45_config_init()
1068 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL, in nxp_c45_config_init()
1070 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in nxp_c45_config_init()
1095 ptp_ability = phy_read_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_probe()