Lines Matching +full:10 +full:gbase +full:- +full:kr
1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
87 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
91 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
92 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
150 return phydev->drv->driver_data; in to_mv3310_chip()
188 temp = chip->hwmon_read_temp_reg(phydev); in mv3310_hwmon_read()
192 *value = ((temp & 0xff) - 75) * 1000; in mv3310_hwmon_read()
197 return -EOPNOTSUPP; in mv3310_hwmon_read()
241 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) in mv3310_hwmon_config()
257 struct device *dev = &phydev->mdio.dev; in mv3310_hwmon_probe()
258 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_hwmon_probe()
261 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); in mv3310_hwmon_probe()
262 if (!priv->hwmon_name) in mv3310_hwmon_probe()
263 return -ENODEV; in mv3310_hwmon_probe()
265 for (i = j = 0; priv->hwmon_name[i]; i++) { in mv3310_hwmon_probe()
266 if (isalnum(priv->hwmon_name[i])) { in mv3310_hwmon_probe()
268 priv->hwmon_name[j] = priv->hwmon_name[i]; in mv3310_hwmon_probe()
272 priv->hwmon_name[j] = '\0'; in mv3310_hwmon_probe()
278 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, in mv3310_hwmon_probe()
279 priv->hwmon_name, phydev, in mv3310_hwmon_probe()
282 return PTR_ERR_OR_ZERO(priv->hwmon_dev); in mv3310_hwmon_probe()
304 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_power_up()
310 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || in mv3310_power_up()
311 priv->firmware_ver < 0x00030000) in mv3310_power_up()
375 return -EINVAL; in mv3310_set_edpd()
392 sfp_parse_support(phydev->sfp_bus, id, support); in mv3310_sfp_insert()
393 iface = sfp_select_interface(phydev->sfp_bus, support); in mv3310_sfp_insert()
396 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); in mv3310_sfp_insert()
397 return -EINVAL; in mv3310_sfp_insert()
415 if (!phydev->is_c45 || in mv3310_probe()
416 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in mv3310_probe()
417 return -ENODEV; in mv3310_probe()
424 dev_warn(&phydev->mdio.dev, in mv3310_probe()
426 return -ENODEV; in mv3310_probe()
429 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in mv3310_probe()
431 return -ENOMEM; in mv3310_probe()
433 dev_set_drvdata(&phydev->mdio.dev, priv); in mv3310_probe()
439 priv->firmware_ver = ret << 16; in mv3310_probe()
445 priv->firmware_ver |= ret; in mv3310_probe()
448 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, in mv3310_probe()
449 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); in mv3310_probe()
460 chip->init_supported_interfaces(priv->supported_interfaces); in mv3310_probe()
495 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) in mv3310_has_pma_ngbaset_quirk()
499 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_has_pma_ngbaset_quirk()
527 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv2110_init_interface()
529 priv->rate_match = false; in mv2110_init_interface()
532 priv->rate_match = true; in mv2110_init_interface()
535 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; in mv2110_init_interface()
537 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; in mv2110_init_interface()
540 priv->const_interface = PHY_INTERFACE_MODE_NA; in mv2110_init_interface()
542 return -EINVAL; in mv2110_init_interface()
549 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_init_interface()
551 priv->rate_match = false; in mv3310_init_interface()
556 priv->rate_match = true; in mv3310_init_interface()
559 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; in mv3310_init_interface()
563 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; in mv3310_init_interface()
566 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; in mv3310_init_interface()
569 priv->const_interface = PHY_INTERFACE_MODE_XAUI; in mv3310_init_interface()
571 return -EINVAL; in mv3310_init_interface()
578 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3340_init_interface()
581 priv->rate_match = false; in mv3340_init_interface()
584 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; in mv3340_init_interface()
593 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_config_init()
598 if (!test_bit(phydev->interface, priv->supported_interfaces)) in mv3310_config_init()
599 return -ENODEV; in mv3310_config_init()
601 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in mv3310_config_init()
608 mactype = chip->get_mactype(phydev); in mv3310_config_init()
612 err = chip->init_interface(phydev, mactype); in mv3310_config_init()
618 /* Enable EDPD mode - saving 600mW */ in mv3310_config_init()
637 phydev->supported, in mv3310_get_features()
641 phydev->supported, in mv3310_get_features()
653 switch (phydev->mdix_ctrl) { in mv3310_config_mdix()
664 return -EINVAL; in mv3310_config_mdix()
685 if (phydev->autoneg == AUTONEG_DISABLE) in mv3310_config_aneg()
697 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in mv3310_config_aneg()
724 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_update_interface()
726 if (!phydev->link) in mv3310_update_interface()
730 * at 10Gb. The PHY adapts the rate to actual wire speed with help of in mv3310_update_interface()
735 if (priv->rate_match || in mv3310_update_interface()
736 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { in mv3310_update_interface()
737 phydev->interface = priv->const_interface; in mv3310_update_interface()
742 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / in mv3310_update_interface()
744 * Florian suggests setting phydev->interface to communicate this to the in mv3310_update_interface()
747 switch (phydev->speed) { in mv3310_update_interface()
749 phydev->interface = priv->const_interface; in mv3310_update_interface()
752 phydev->interface = PHY_INTERFACE_MODE_5GBASER; in mv3310_update_interface()
755 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in mv3310_update_interface()
760 phydev->interface = PHY_INTERFACE_MODE_SGMII; in mv3310_update_interface()
767 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
770 phydev->link = 1; in mv3310_read_status_10gbaser()
771 phydev->speed = SPEED_10000; in mv3310_read_status_10gbaser()
772 phydev->duplex = DUPLEX_FULL; in mv3310_read_status_10gbaser()
773 phydev->port = PORT_FIBRE; in mv3310_read_status_10gbaser()
796 phydev->link = 0; in mv3310_read_status_copper()
807 phydev->speed = SPEED_10000; in mv3310_read_status_copper()
811 phydev->speed = SPEED_5000; in mv3310_read_status_copper()
815 phydev->speed = SPEED_2500; in mv3310_read_status_copper()
819 phydev->speed = SPEED_1000; in mv3310_read_status_copper()
823 phydev->speed = SPEED_100; in mv3310_read_status_copper()
827 phydev->speed = SPEED_10; in mv3310_read_status_copper()
831 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? in mv3310_read_status_copper()
833 phydev->port = PORT_TP; in mv3310_read_status_copper()
834 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? in mv3310_read_status_copper()
847 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in mv3310_read_status_copper()
860 phydev->speed = SPEED_UNKNOWN; in mv3310_read_status()
861 phydev->duplex = DUPLEX_UNKNOWN; in mv3310_read_status()
862 linkmode_zero(phydev->lp_advertising); in mv3310_read_status()
863 phydev->link = 0; in mv3310_read_status()
864 phydev->pause = 0; in mv3310_read_status()
865 phydev->asym_pause = 0; in mv3310_read_status()
866 phydev->mdix = ETH_TP_MDI_INVALID; in mv3310_read_status()
879 if (phydev->link) in mv3310_read_status()
888 switch (tuna->id) { in mv3310_get_tunable()
892 return -EOPNOTSUPP; in mv3310_get_tunable()
899 switch (tuna->id) { in mv3310_set_tunable()
903 return -EOPNOTSUPP; in mv3310_set_tunable()
1001 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_match_phy_device()
1010 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3340_match_phy_device()
1021 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv211x_match_phy_device()
1047 wol->supported = WAKE_MAGIC; in mv3110_get_wol()
1048 wol->wolopts = 0; in mv3110_get_wol()
1055 wol->wolopts |= WAKE_MAGIC; in mv3110_get_wol()
1063 if (wol->wolopts & WAKE_MAGIC) { in mv3110_set_wol()
1074 ((phydev->attached_dev->dev_addr[5] << 8) | in mv3110_set_wol()
1075 phydev->attached_dev->dev_addr[4])); in mv3110_set_wol()
1081 ((phydev->attached_dev->dev_addr[3] << 8) | in mv3110_set_wol()
1082 phydev->attached_dev->dev_addr[2])); in mv3110_set_wol()
1088 ((phydev->attached_dev->dev_addr[1] << 8) | in mv3110_set_wol()
1089 phydev->attached_dev->dev_addr[0])); in mv3110_set_wol()
1110 /* Reset the clear WOL status bit as it does not self-clear */ in mv3110_set_wol()
1205 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");