185 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)  in xpcs_write()  function
202 	return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);  in xpcs_write_vendor()
248 	ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);  in xpcs_soft_reset()
395 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);  in xpcs_config_usxgmii()
431 	ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);  in _xpcs_config_aneg_c73()
444 	ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);  in _xpcs_config_aneg_c73()
455 	return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);  in _xpcs_config_aneg_c73()
473 	return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);  in xpcs_config_aneg_c73()
686 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);  in xpcs_config_eee()
699 	return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);  in xpcs_config_eee()
728 		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,  in xpcs_config_aneg_c37_sgmii()
745 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);  in xpcs_config_aneg_c37_sgmii()
758 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);  in xpcs_config_aneg_c37_sgmii()
763 		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,  in xpcs_config_aneg_c37_sgmii()
778 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);  in xpcs_config_2500basex()
788 	return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);  in xpcs_config_2500basex()
975 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);  in xpcs_link_up_sgmii()