Lines Matching +full:0 +full:x4000
53 #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */
60 (0x0000c020 + 0x1000 * (ee))
65 (0x0000c024 + 0x1000 * (ee))
71 GSI_CHANNEL_TYPE_MHI = 0x0,
72 GSI_CHANNEL_TYPE_XHCI = 0x1,
73 GSI_CHANNEL_TYPE_GPI = 0x2,
74 GSI_CHANNEL_TYPE_XDCI = 0x3,
75 GSI_CHANNEL_TYPE_WDI2 = 0x4,
76 GSI_CHANNEL_TYPE_GCI = 0x5,
77 GSI_CHANNEL_TYPE_WDI3 = 0x6,
78 GSI_CHANNEL_TYPE_MHIP = 0x7,
79 GSI_CHANNEL_TYPE_AQC = 0x8,
80 GSI_CHANNEL_TYPE_11AD = 0x9,
86 (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch))
87 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
117 (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch))
123 return u32_encode_bits(length, GENMASK(15, 0)); in r_length_encoded()
124 return u32_encode_bits(length, GENMASK(19, 0)); in r_length_encoded()
130 (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch))
135 (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch))
140 (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch))
141 #define WRR_WEIGHT_FMASK GENMASK(3, 0)
144 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */
154 GSI_USE_PREFETCH_BUFS = 0x0,
155 GSI_ESCAPE_BUF_ONLY = 0x1,
156 GSI_SMART_PREFETCH = 0x2,
157 GSI_FREE_PREFETCH = 0x3,
163 (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch))
168 (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch))
173 (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch))
178 (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch))
183 (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev))
185 #define EV_CHTYPE_FMASK GENMASK(3, 0)
195 (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev))
200 return u32_encode_bits(length, GENMASK(15, 0)); in ev_r_length_encoded()
201 return u32_encode_bits(length, GENMASK(19, 0)); in ev_r_length_encoded()
207 (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev))
212 (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev))
217 (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev))
222 (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev))
223 #define MODT_FMASK GENMASK(15, 0)
230 (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev))
235 (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev))
240 (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev))
245 (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev))
250 (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev))
255 (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev))
260 (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev))
265 (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch))
270 (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev))
275 (0x0001f000 + 0x4000 * (ee))
276 #define ENABLED_FMASK GENMASK(0, 0)
281 (0x0001f008 + 0x4000 * (ee))
282 #define CH_CHID_FMASK GENMASK(7, 0)
287 GSI_CH_ALLOCATE = 0x0,
288 GSI_CH_START = 0x1,
289 GSI_CH_STOP = 0x2,
290 GSI_CH_RESET = 0x9,
291 GSI_CH_DE_ALLOC = 0xa,
292 GSI_CH_DB_STOP = 0xb,
298 (0x0001f010 + 0x4000 * (ee))
299 #define EV_CHID_FMASK GENMASK(7, 0)
304 GSI_EVT_ALLOCATE = 0x0,
305 GSI_EVT_RESET = 0x9,
306 GSI_EVT_DE_ALLOC = 0xa,
312 (0x0001f018 + 0x4000 * (ee))
313 #define GENERIC_OPCODE_FMASK GENMASK(4, 0)
319 GSI_GENERIC_HALT_CHANNEL = 0x1,
320 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2,
327 (0x0001f040 + 0x4000 * (ee))
328 #define IRAM_SIZE_FMASK GENMASK(2, 0)
333 /* Fields below are present for IPA v4.0 and above */
344 IRAM_SIZE_ONE_KB = 0x0,
345 IRAM_SIZE_TWO_KB = 0x1,
346 /* The next two values are available for IPA v4.0 and above */
347 IRAM_SIZE_TWO_N_HALF_KB = 0x2,
348 IRAM_SIZE_THREE_KB = 0x3,
350 IRAM_SIZE_THREE_N_HALF_KB = 0x4,
351 IRAM_SIZE_FOUR_KB = 0x5,
358 (0x0001f080 + 0x4000 * (ee))
362 (0x0001f088 + 0x4000 * (ee))
366 GSI_CH_CTRL = 0x0, /* channel allocation, etc. */
367 GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */
368 GSI_GLOB_EE = 0x2, /* global/general event */
369 GSI_IEOB = 0x3, /* TRE completion */
370 GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */
371 GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */
372 GSI_GENERAL = 0x6, /* general-purpose event */
378 (0x0001f090 + 0x4000 * (ee))
383 (0x0001f094 + 0x4000 * (ee))
388 (0x0001f098 + 0x4000 * (ee))
393 (0x0001f09c + 0x4000 * (ee))
398 (0x0001f0a0 + 0x4000 * (ee))
403 (0x0001f0a4 + 0x4000 * (ee))
408 (0x0001f0b0 + 0x4000 * (ee))
413 (0x0001f0b8 + 0x4000 * (ee))
418 (0x0001f0c0 + 0x4000 * (ee))
423 (0x0001f100 + 0x4000 * (ee))
427 (0x0001f108 + 0x4000 * (ee))
431 (0x0001f110 + 0x4000 * (ee))
434 ERROR_INT = 0x0,
435 GP_INT1 = 0x1,
436 GP_INT2 = 0x2,
437 GP_INT3 = 0x3,
443 (0x0001f118 + 0x4000 * (ee))
447 (0x0001f120 + 0x4000 * (ee))
451 (0x0001f128 + 0x4000 * (ee))
454 BREAK_POINT = 0x0,
455 BUS_ERROR = 0x1,
456 CMD_FIFO_OVRFLOW = 0x2,
457 MCS_STACK_OVRFLOW = 0x3,
463 (0x0001f180 + 0x4000 * (ee))
464 #define INTYPE_FMASK GENMASK(0, 0)
469 (0x0001f200 + 0x4000 * (ee))
472 #define ERR_ARG3_FMASK GENMASK(3, 0)
482 GSI_INVALID_TRE = 0x1,
483 GSI_OUT_OF_BUFFERS = 0x2,
484 GSI_OUT_OF_RESOURCES = 0x3,
485 GSI_UNSUPPORTED_INTER_EE_OP = 0x4,
486 GSI_EVT_RING_EMPTY = 0x5,
487 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6,
489 GSI_HWO_1 = 0x8,
494 GSI_ERR_TYPE_GLOB = 0x1,
495 GSI_ERR_TYPE_CHAN = 0x2,
496 GSI_ERR_TYPE_EVT = 0x3,
502 (0x0001f210 + 0x4000 * (ee))
507 (0x0001f400 + 0x4000 * (ee))
508 #define INTER_EE_RESULT_FMASK GENMASK(2, 0)
513 GENERIC_EE_SUCCESS = 0x1,
514 GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2,
515 GENERIC_EE_INCORRECT_DIRECTION = 0x3,
516 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4,
517 GENERIC_EE_INCORRECT_CHANNEL = 0x5,
518 GENERIC_EE_RETRY = 0x6,
519 GENERIC_EE_NO_RESOURCES = 0x7,