221 static void write_scc(struct scc_priv *priv, int reg, int val);
283 		write_scc(&info->priv[0], R9, FHWRES);  in dmascc_exit()
486 	write_scc(priv, R9, FHWRES | MIE | NV);  in setup_adapter()
489 	write_scc(priv, R15, SHDLCE);  in setup_adapter()
504 	write_scc(priv, R15, 0);  in setup_adapter()
517 		write_scc(priv, R15, CTSIE);  in setup_adapter()
518 		write_scc(priv, R0, RES_EXT_INT);  in setup_adapter()
519 		write_scc(priv, R1, EXT_INT_ENAB);  in setup_adapter()
535 		write_scc(priv, R1, 0);  in setup_adapter()
536 		write_scc(priv, R15, 0);  in setup_adapter()
537 		write_scc(priv, R0, RES_EXT_INT);  in setup_adapter()
603 	write_scc(&info->priv[0], R9, FHWRES);  in setup_adapter()
616 static void write_scc(struct scc_priv *priv, int reg, int val)  in write_scc()  function
750 	write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);  in scc_open()
752 	write_scc(priv, R4, SDLC | X1CLK);  in scc_open()
754 	write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in scc_open()
756 	write_scc(priv, R3, Rx8);  in scc_open()
758 	write_scc(priv, R5, Tx8);  in scc_open()
760 	write_scc(priv, R6, 0);  in scc_open()
762 	write_scc(priv, R7, FLAG);  in scc_open()
766 		write_scc(priv, R15, SHDLCE);  in scc_open()
768 		write_scc(priv, R7, AUTOEOM);  in scc_open()
769 		write_scc(priv, R15, 0);  in scc_open()
773 		write_scc(priv, R15, SHDLCE);  in scc_open()
795 				write_scc(priv, R7, AUTOEOM | TXFIFOE);  in scc_open()
797 				write_scc(priv, R7, AUTOEOM);  in scc_open()
799 			write_scc(priv, R7, AUTOEOM | RXFIFOH);  in scc_open()
801 		write_scc(priv, R15, 0);  in scc_open()
805 	write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));  in scc_open()
810 		write_scc(priv, R12, priv->param.brg_tc & 0xFF);  in scc_open()
811 		write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);  in scc_open()
814 		write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);  in scc_open()
816 		write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);  in scc_open()
819 		write_scc(priv, R14, DTRREQ | BRSRC);  in scc_open()
829 	write_scc(priv, R11, priv->param.clocks);  in scc_open()
848 	write_scc(priv, R15, DCDIE);  in scc_open()
872 	write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);  in scc_close()
944 		write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);  in scc_send_packet()
945 		write_scc(priv, R15, 0);  in scc_send_packet()
981 		write_scc(priv, R15, TxUIE);  in tx_on()
988 			write_scc(priv, R1,  in tx_on()
999 		write_scc(priv, R15, TxUIE);  in tx_on()
1000 		write_scc(priv, R1,  in tx_on()
1006 		write_scc(priv, R0, RES_EOM_L);  in tx_on()
1034 		write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |  in rx_on()
1040 		write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |  in rx_on()
1043 	write_scc(priv, R0, ERR_RES);  in rx_on()
1044 	write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);  in rx_on()
1051 	write_scc(priv, R3, Rx8);  in rx_off()
1056 		write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in rx_off()
1072 			write_scc(priv, R15, r15 | CTSIE);  in start_timer()
1104 		write_scc(&info->priv[0], R0, RES_H_IUS);  in z8530_isr()
1159 		write_scc(priv, R0, ERR_RES);  in rx_isr()
1191 			write_scc(priv, R0, ERR_RES);  in special_condition()
1290 		write_scc(priv, R0, RES_Tx_P);  in tx_isr()
1301 		write_scc(priv, R0, RES_EOM_L);  in tx_isr()
1314 	write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1336 			write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);  in es_isr()
1342 			write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1343 			write_scc(priv, R0, RES_EXT_INT);  in es_isr()
1355 		write_scc(priv, R15, 0);  in es_isr()
1373 				write_scc(priv, R15, 0);  in es_isr()
1381 				write_scc(priv, R15, 0);  in es_isr()
1403 		write_scc(priv, R5, TxCRC_ENAB | Tx8);  in tm_isr()
1406 			write_scc(priv, R15, 0);  in tm_isr()
1410 		write_scc(priv, R15, DCDIE);  in tm_isr()
1425 			write_scc(priv, R5,  in tm_isr()
1427 			write_scc(priv, R15, 0);  in tm_isr()
1432 				write_scc(priv, R15, DCDIE);  in tm_isr()
1437 		write_scc(priv, R15, DCDIE);  in tm_isr()