310 #define PutByte(reg,value) outb((value), ioaddr+(reg))  macro
356     PutByte(XIRCREG2_GPR2, 0x04|0); /* drive MDCK low */  in mii_idle()
358     PutByte(XIRCREG2_GPR2, 0x04|1); /* and drive MDCK high */  in mii_idle()
370 	PutByte(XIRCREG2_GPR2, 0x0c|2|0); /* set MDIO */  in mii_putbit()
372 	PutByte(XIRCREG2_GPR2, 0x0c|2|1); /* and drive MDCK high */  in mii_putbit()
375 	PutByte(XIRCREG2_GPR2, 0x0c|0|0); /* clear MDIO */  in mii_putbit()
377 	PutByte(XIRCREG2_GPR2, 0x0c|0|1); /* and drive MDCK high */  in mii_putbit()
403     PutByte(XIRCREG2_GPR2, 4|0); /* drive MDCK low */  in mii_getbit()
406     PutByte(XIRCREG2_GPR2, 4|1); /* drive MDCK high again */  in mii_getbit()
991 	PutByte(XIRCREG_CR, 0);  in xirc2ps_interrupt()
1011     PutByte(XIRCREG40_RXST0, (~rx_status & 0xff));  in xirc2ps_interrupt()
1014     PutByte(XIRCREG40_TXST0, 0);  in xirc2ps_interrupt()
1015     PutByte(XIRCREG40_TXST1, 0);  in xirc2ps_interrupt()
1125 	PutByte(XIRCREG_CR, ClearRxOvrun);  in xirc2ps_interrupt()
1146 	PutByte(XIRCREG_CR, RestartTx);  /* restart transmitter process */  in xirc2ps_interrupt()
1181     PutByte(XIRCREG_CR, EnableIntr);  /* re-enable interrupts */  in xirc2ps_interrupt()
1256 	PutByte(XIRCREG_EDP, skb->data[pktlen-1]);  in do_start_xmit()
1259 	PutByte(XIRCREG_CR, TransmitPacket|EnableIntr);  in do_start_xmit()
1286 			PutByte(sa_info->reg_nr++, addr[5 - i]);  in set_address()
1288 			PutByte(sa_info->reg_nr++, addr[i]);  in set_address()
1342 	PutByte(XIRCREG42_SWC1, value | 0x06); /* set MPE and PME */  in set_multicast_list()
1344 	PutByte(XIRCREG42_SWC1, value | 0x02); /* set MPE */  in set_multicast_list()
1347 	PutByte(XIRCREG42_SWC1, value | 0x01);  in set_multicast_list()
1349 	PutByte(XIRCREG40_CMD0, Offline);  in set_multicast_list()
1352 	PutByte(XIRCREG40_CMD0, EnableRecv | Online);  in set_multicast_list()
1354 	PutByte(XIRCREG42_SWC1, value | 0x00);  in set_multicast_list()
1458     PutByte(XIRCREG4_GPR1, 0);	     /* clear bit 0: power down */  in hardreset()
1461 	PutByte(XIRCREG4_GPR1, 1);	 /* set bit 0: power up */  in hardreset()
1463 	PutByte(XIRCREG4_GPR1, 1 | 4);	 /* set bit 0: power up, bit 2: AIC */  in hardreset()
1477     PutByte(XIRCREG_CR, SoftReset); /* set */  in do_reset()
1479     PutByte(XIRCREG_CR, 0);	     /* clear */  in do_reset()
1487 	PutByte(XIRCREG4_GPR0, 0x0e);  in do_reset()
1500 	    PutByte(XIRCREG4_GPR0, 4);  in do_reset()
1505 	PutByte(XIRCREG42_SWC1, 0xC0);  in do_reset()
1508 	PutByte(XIRCREG42_SWC1, 0x80);  in do_reset()
1522     PutByte(XIRCREG1_IMR0, 0xff); /* allow all ints */  in do_reset()
1523     PutByte(XIRCREG1_IMR1, 1	); /* and Set TxUnderrunDetect */  in do_reset()
1528     PutByte(XIRCREG1_ECR, value);  in do_reset()
1533     PutByte(XIRCREG42_SWC0, 0x20); /* disable source insertion */  in do_reset()
1557     PutByte(XIRCREG40_RMASK0, 0xff); /* ROK, RAB, rsv, RO, CRC, AE, PTL, MP */  in do_reset()
1558     PutByte(XIRCREG40_TMASK0, 0xff); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */  in do_reset()
1559     PutByte(XIRCREG40_TMASK1, 0xb0); /* rsv, rsv, PTD, EXT, rsv,rsv,rsv, rsv*/  in do_reset()
1560     PutByte(XIRCREG40_RXST0,  0x00); /* ROK, RAB, REN, RO, CRC, AE, PTL, MP */  in do_reset()
1561     PutByte(XIRCREG40_TXST0,  0x00); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */  in do_reset()
1562     PutByte(XIRCREG40_TXST1,  0x00); /* TEN, rsv, PTD, EXT, retry_counter:4  */  in do_reset()
1568 	    PutByte(XIRCREG2_MSR, GetByte(XIRCREG2_MSR) | 0x08);  in do_reset()
1574 		PutByte(XIRCREG42_SWC1, 0xC0);  in do_reset()
1576 		PutByte(XIRCREG42_SWC1, 0x80);  in do_reset()
1580 	    PutByte(XIRCREG1_ECR, GetByte(XIRCREG1_ECR | FullDuplex));  in do_reset()
1590 	PutByte(XIRCREG2_LED, 0x3b);  in do_reset()
1592 	PutByte(XIRCREG2_LED, 0x3a);  in do_reset()
1595 	PutByte(0x0b, 0x04); /* 100 Mbit LED */  in do_reset()
1601 	PutByte(XIRCREG40_CMD0, EnableRecv | Online);  in do_reset()
1606     PutByte(XIRCREG1_IMR0, 0xff);  in do_reset()
1609     PutByte(XIRCREG_CR, EnableIntr);  in do_reset()
1612 	    PutByte(0x10, 0x11); /* unmask master-int bit */  in do_reset()
1707     PutByte(XIRCREG4_GPR1, 0);	     /* clear bit 0: power down */  in do_powerdown()
1726     PutByte(XIRCREG_CR, 0);  /* disable interrupts */  in do_stop()
1728     PutByte(XIRCREG1_IMR0, 0x00); /* forbid all ints */  in do_stop()
1730     PutByte(XIRCREG4_GPR1, 0);	/* clear bit 0: power down */  in do_stop()