Lines Matching +full:1 +full:- +full:4
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
63 /* MCDI version 1
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
98 #define MCDI_HEADER_RESYNC_WIDTH 1
102 #define MCDI_HEADER_SEQ_WIDTH 4
104 #define MCDI_HEADER_RSVD_WIDTH 1
106 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1
108 #define MCDI_HEADER_ERROR_WIDTH 1
110 #define MCDI_HEADER_RESPONSE_WIDTH 1
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
139 * - LEVEL==INFO Command succeeded
140 * - LEVEL==ERR Command failed
151 * non-existent MCDI command MC_CMD_DEBUG_LOG.
156 * Since the event is written in big-endian byte order, this works
157 * providing bits 56-63 of the event are 0xc0.
169 #define MC_CMD_ERR_EPERM 1
170 /* Non-existent command target */
173 #define MC_CMD_ERR_EINTR 4
192 /* Read-only */
196 /* Non-recursive resource is already acquired */
217 /* V-adaptor not found. */
221 /* V-switch not found. */
229 /* Invalid v-switch type. */
231 /* Invalid v-port type. */
253 * This error code is followed by a 32-bit handle that
256 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
266 * an operation failed due to lack of SR-IOV privilege.
275 * May also returned for other operations such as sub-variant switching. */
315 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
316 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
317 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
319 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
320 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
321 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
323 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
324 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
325 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
328 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
332 (1 << MC_CMD_READ32) | \
333 (1 << MC_CMD_WRITE32) | \
334 (1 << MC_CMD_COPYCODE) | \
335 (1 << MC_CMD_GET_VERSION), \
356 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
357 * stack ID (which must be in the range 1-255) along with an EVB port ID.
363 * may be followed by the (0-based) number of the first argument that
366 #define MC_CMD_ERR_ARG_OFST 4
374 #define MCDI_EVENT_CONT_WIDTH 1
386 #define MCDI_EVENT_DATA_LEN 4
401 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
406 /* enum: 1Gbs */
420 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
449 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
467 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
485 /* enum: AOE failed to load - no valid image? */
493 /* enum: Generic AOE fault - likely to have been reported via other means too
523 /* enum: FPGA boot-flash contains an invalid image header */
579 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
585 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
595 /* enum: MUM failed to load - no valid image? */
629 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
634 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1
659 #define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1
661 #define MCDI_EVENT_EV_CODE_WIDTH 4
759 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
764 * SF-122927-TC for details.
770 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
773 * SF-122927-TC for details.
781 #define MCDI_EVENT_CMDDONE_DATA_LEN 4
785 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
789 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4
793 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
797 #define MCDI_EVENT_TX_ERR_DATA_LEN 4
804 #define MCDI_EVENT_PTP_SECONDS_LEN 4
811 #define MCDI_EVENT_PTP_MAJOR_LEN 4
818 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
825 #define MCDI_EVENT_PTP_MINOR_LEN 4
831 #define MCDI_EVENT_PTP_UUID_LEN 4
835 #define MCDI_EVENT_RX_ERR_DATA_LEN 4
839 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4
843 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
847 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
852 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
855 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
867 #define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
872 #define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
873 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
884 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
888 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
892 * should resend it. A non-zero value means that the authorization has been
898 #define MCDI_EVENT_DBRET_DATA_LEN 4
902 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
906 #define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
911 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
916 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
921 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
928 #define MCDI_EVENT_DESC_PROXY_DATA_LEN 4
933 #define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
936 /* Virtio features negotiated with the host driver. First event (CONT=1)
940 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
947 #define FCDI_EVENT_CONT_WIDTH 1
959 #define FCDI_EVENT_DATA_LEN 4
962 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
970 #define FCDI_EVENT_EV_CODE_WIDTH 4
991 /* enum: Port id config to map MC-FC port idx */
1000 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
1008 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
1012 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4
1016 #define FCDI_EVENT_PTP_STATE_LEN 4
1025 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
1033 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
1037 #define FCDI_EVENT_BOOT_RESULT_LEN 4
1045 * such that bits 32-63 containing | event code, level, source etc remain the
1053 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
1056 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
1061 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
1066 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
1074 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
1083 #define MUM_EVENT_CONT_WIDTH 1
1095 #define MUM_EVENT_DATA_LEN 4
1106 #define MUM_EVENT_PORT_PHY_READY_WIDTH 1
1108 #define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
1109 #define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
1112 #define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
1115 #define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
1117 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
1118 #define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
1121 #define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
1124 #define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
1130 #define MUM_EVENT_EV_CODE_WIDTH 4
1142 #define MUM_EVENT_SENSOR_DATA_LEN 4
1146 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4
1150 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
1154 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4
1158 #define MUM_EVENT_PORT_PHY_TECH_LEN 4
1170 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1177 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1182 * Read multiple 32byte words from MC memory. Note - this command really
1194 #define MC_CMD_READ32_IN_ADDR_LEN 4
1195 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1196 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1199 #define MC_CMD_READ32_OUT_LENMIN 4
1202 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1203 #define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1205 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
1206 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
1224 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1225 #define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
1227 #define MC_CMD_WRITE32_IN_ADDR_LEN 4
1228 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1229 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1230 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
1240 * Copy MC code between two locations and jump. Note - this command really
1258 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
1272 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
1275 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
1278 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
1280 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
1281 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
1284 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
1287 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
1289 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
1290 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
1292 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
1295 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4
1305 * Select function for function-specific commands.
1313 #define MC_CMD_SET_FUNC_IN_LEN 4
1316 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4
1338 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
1341 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1342 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1343 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
1345 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
1346 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
1347 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
1348 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
1349 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
1351 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
1366 #define MC_CMD_GET_ASSERTS_IN_LEN 4
1369 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
1375 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
1378 /* enum: A system-level assertion has failed. */
1380 /* enum: A thread-level assertion has failed. */
1387 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1388 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
1391 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1399 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
1401 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
1409 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
1412 /* enum: A system-level assertion has failed. */
1414 /* enum: A thread-level assertion has failed. */
1421 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
1422 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
1425 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
1433 #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
1435 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
1438 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
1447 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
1450 /* enum: A system-level assertion has failed. */
1452 /* enum: A thread-level assertion has failed. */
1459 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
1460 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
1463 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
1471 #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
1473 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
1476 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
1478 /* MC firmware unique build ID (as binary SHA-1 value) */
1493 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
1494 /* MC firmware extra version info (as null-terminated US-ASCII string) */
1497 /* MC firmware build name (as null-terminated US-ASCII string) */
1516 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
1522 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
1523 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
1542 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4
1545 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
1548 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
1550 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
1563 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1566 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
1567 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
1579 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1582 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
1583 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
1603 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1606 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
1607 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
1620 #define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
1623 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
1625 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
1626 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
1629 #define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
1632 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
1634 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
1635 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
1636 /* MC firmware unique build ID (as binary SHA-1 value) */
1641 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
1642 /* MC firmware build name (as null-terminated US-ASCII string) */
1645 /* The SUC firmware version as four numbers - a.b.c.d */
1647 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
1648 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
1649 /* SUC firmware build date (as 64-bit Unix timestamp) */
1655 * indicates family, memory sizes etc. See SF-116728-SW for further details.
1658 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
1659 /* The CMC firmware version as four numbers - a.b.c.d */
1661 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
1662 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
1663 /* CMC firmware build date (as 64-bit Unix timestamp) */
1670 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
1671 * => B, ...) FPGA_VERSION[2]: Sub-revision number
1674 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
1676 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
1679 /* Board name / adapter model (as null-terminated US-ASCII string) */
1684 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
1685 /* Board serial number (as null-terminated US-ASCII string) */
1700 #define MC_CMD_PTP_IN_LEN 1
1703 #define MC_CMD_PTP_IN_OP_LEN 1
1761 /* enum: Get the clock attributes. NOTE- extended version of
1789 #define MC_CMD_PTP_IN_CMD_LEN 4
1790 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
1791 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
1794 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
1797 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
1798 /* enum: PTP, version 1 */
1800 /* enum: PTP, version 1, with VLAN headers - deprecated */
1804 /* enum: PTP, version 2, with VLAN headers - deprecated */
1814 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1815 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1816 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1822 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
1823 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
1825 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1826 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1827 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1830 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
1833 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
1834 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
1841 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1842 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1843 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1848 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1849 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1850 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1855 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1856 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1857 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1862 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1863 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1864 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1879 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
1882 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
1885 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
1888 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
1893 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1894 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1895 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1910 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
1913 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
1916 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
1919 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
1922 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
1927 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1928 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1929 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1932 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
1944 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1945 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1946 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1951 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1952 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1953 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1956 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
1961 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1962 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1963 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1968 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1969 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1970 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1973 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
1978 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1979 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1980 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1982 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
1984 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
1990 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
1991 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
1993 /* MC_CMD_PTP_IN_CMD_LEN 4 */
1994 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1995 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1997 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
1999 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
2000 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
2007 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2008 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2009 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2012 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
2015 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
2018 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
2021 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
2026 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2027 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2028 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2031 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
2034 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
2037 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
2040 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
2043 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
2048 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2049 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2050 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2062 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2063 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2064 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2067 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
2070 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
2076 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2077 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2078 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2079 /* 1 to enable UUID filtering, 0 to disable */
2081 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
2091 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2092 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2093 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2094 /* 1 to enable Domain filtering, 0 to disable */
2096 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
2099 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
2104 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2105 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2106 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2109 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
2118 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2119 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2120 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2125 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2127 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
2128 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
2135 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
2140 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2141 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2142 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2147 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2148 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2149 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2154 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2155 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2156 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2161 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2162 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2163 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2166 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
2172 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
2177 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2178 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2179 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2182 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
2189 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
2194 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2195 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2196 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2197 /* 1 to enable PPS test mode, 0 to disable and return result. */
2199 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
2204 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2205 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2206 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2207 /* NIC - Host System Clock Synchronization status */
2209 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
2218 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
2220 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
2222 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
2231 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
2234 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
2236 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
2237 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
2239 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
2240 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
2252 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
2255 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
2257 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
2258 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
2260 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
2261 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
2267 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
2270 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
2272 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
2273 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
2275 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
2276 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
2279 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
2285 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
2287 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
2288 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
2291 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
2294 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
2297 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
2300 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
2303 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
2306 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
2309 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
2312 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
2315 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
2318 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
2321 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
2324 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
2327 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
2330 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
2337 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
2341 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
2346 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
2348 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
2349 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
2351 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
2352 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
2355 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
2358 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
2361 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
2364 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
2370 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
2393 /* enum: PPS time event period not sufficiently close to 1s. */
2402 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
2403 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
2409 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
2411 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
2412 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
2415 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
2418 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
2421 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2422 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
2424 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
2425 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
2430 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
2434 * be assumed. Note this enum is deprecated. Do not add to it- use the
2438 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
2443 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2454 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
2459 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2471 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
2472 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
2475 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
2478 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
2480 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
2481 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
2484 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
2487 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
2489 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
2491 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
2493 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
2499 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
2501 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
2502 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
2505 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
2508 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
2514 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
2516 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
2517 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
2520 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
2523 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
2524 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
2526 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
2527 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
2529 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
2532 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
2535 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
2556 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4
2557 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
2558 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4
2560 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
2563 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
2566 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2567 #define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
2570 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
2571 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
2589 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
2590 #define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
2593 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
2594 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
2595 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
2597 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
2598 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
2603 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
2605 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
2620 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
2622 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
2627 #define MC_CMD_HP_IN_SUBCMD_LEN 4
2628 /* enum: OCSD (Option Card Sensor Data) sub-command. */
2630 /* enum: Last known valid HP sub-command. */
2632 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
2634 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
2636 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
2638 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
2642 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
2645 #define MC_CMD_HP_OUT_LEN 4
2647 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
2673 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
2677 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
2697 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4
2703 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
2704 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
2707 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
2714 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4
2720 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
2724 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
2725 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
2745 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
2751 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
2752 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
2755 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
2762 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
2765 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
2768 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
2773 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
2792 #define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
2798 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
2808 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
2811 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
2812 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
2813 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4
2816 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4
2818 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
2819 #define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4
2821 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
2825 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
2832 * Read a 32-bit register from the indirect port register map. The port to
2838 #define MC_CMD_PORT_READ32_IN_LEN 4
2841 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4
2847 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
2849 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
2850 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
2855 * Write a 32-bit register to the indirect port register map. The port to
2864 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
2866 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
2867 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
2870 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
2873 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
2878 * Read a 128-bit register from the indirect port register map. The port to
2884 #define MC_CMD_PORT_READ128_IN_LEN 4
2887 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4
2896 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
2901 * Write a 128-bit register to the indirect port register map. The port to
2910 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
2912 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
2916 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
2919 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
2922 #define MC_CMD_CAPABILITIES_LEN 4
2925 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
2927 #define MC_CMD_CAPABILITIES_TURBO_LBN 1
2928 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1
2931 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
2934 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1
2936 #define MC_CMD_CAPABILITIES_AOE_LBN 4
2937 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1
2940 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
2943 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
2965 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
2967 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
2968 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
2974 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
2979 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
2994 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
2999 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
3004 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
3009 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
3010 /* Siena only. This field contains a 16-bit value for each of the types of
3025 * Read DBI register(s) -- extended functionality
3037 #define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
3042 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
3043 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
3048 #define MC_CMD_DBI_READX_OUT_LENMIN 4
3051 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
3052 #define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
3055 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
3056 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
3063 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
3066 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
3067 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
3068 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4
3071 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4
3073 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
3074 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4
3076 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
3083 * Set the 16byte seed for the MC pseudo-random generator.
3113 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
3114 #define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
3115 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
3117 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
3139 /* new state to set if UPDATE=1 */
3141 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
3144 #define MC_CMD_DRV_ATTACH_WIDTH 1
3147 #define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
3149 #define MC_CMD_DRV_PREBOOT_LBN 1
3150 #define MC_CMD_DRV_PREBOOT_WIDTH 1
3152 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
3153 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
3156 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
3159 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
3161 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
3162 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1
3165 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
3168 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1
3169 /* 1 to set new state, or 0 to just report the existing state */
3170 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
3171 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
3174 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
3193 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3200 * (i.e. non-production) builds.
3203 /* enum: Only this option is allowed for non-admin functions */
3210 /* new state to set if UPDATE=1 */
3212 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
3215 /* MC_CMD_DRV_ATTACH_WIDTH 1 */
3218 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1
3220 /* MC_CMD_DRV_PREBOOT_LBN 1 */
3221 /* MC_CMD_DRV_PREBOOT_WIDTH 1 */
3223 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1
3224 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1
3227 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1
3230 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1
3232 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
3233 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1
3236 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
3239 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1
3240 /* 1 to set new state, or 0 to just report the existing state */
3241 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
3242 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
3245 #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
3264 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3271 * (i.e. non-production) builds.
3274 /* enum: Only this option is allowed for non-admin functions */
3276 /* Version of the driver to be reported by management protocols (e.g. NC-SI)
3277 * handled by the NIC. This is a zero-terminated ASCII string.
3283 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
3286 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
3292 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
3294 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
3295 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
3296 /* enum: Labels the lowest-numbered function visible to the OS */
3315 /* enum: If set, indicates that TX only spreading is enabled. Even-numbered
3316 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
3317 * also has the effect that only even-numbered RXQs will receive traffic.
3329 #define MC_CMD_SHMUART_IN_LEN 4
3332 #define MC_CMD_SHMUART_IN_FLAG_LEN 4
3340 * Generic per-port reset. There is no equivalent for per-board reset. Locks
3341 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
3358 * Generic per-resource reset. There is no equivalent for per-board reset.
3366 #define MC_CMD_ENTITY_RESET_IN_LEN 4
3371 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
3374 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
3390 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
3392 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
3393 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
3401 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
3424 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4
3425 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
3426 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
3428 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
3433 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
3434 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
3435 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
3437 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
3439 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
3441 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
3443 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
3445 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
3447 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
3449 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
3451 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
3453 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
3455 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
3457 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
3459 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
3461 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
3463 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
3465 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
3467 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
3469 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
3471 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
3487 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
3488 #define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
3490 #define MC_CMD_PUTS_IN_DEST_LEN 4
3493 #define MC_CMD_PUTS_IN_UART_WIDTH 1
3495 #define MC_CMD_PUTS_IN_PORT_LBN 1
3496 #define MC_CMD_PUTS_IN_PORT_WIDTH 1
3497 #define MC_CMD_PUTS_IN_DHOST_OFST 4
3500 #define MC_CMD_PUTS_IN_STRING_LEN 1
3501 #define MC_CMD_PUTS_IN_STRING_MINNUM 1
3526 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
3529 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
3531 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
3532 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
3535 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
3538 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
3540 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
3541 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
3544 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
3547 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
3549 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
3550 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
3553 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
3555 #define MC_CMD_PHY_CAP_10HDX_LBN 1
3556 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1
3559 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1
3562 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1
3564 #define MC_CMD_PHY_CAP_100FDX_LBN 4
3565 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1
3568 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
3571 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
3574 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
3577 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
3580 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1
3583 #define MC_CMD_PHY_CAP_AN_WIDTH 1
3586 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
3589 #define MC_CMD_PHY_CAP_DDM_WIDTH 1
3592 #define MC_CMD_PHY_CAP_100000FDX_WIDTH 1
3595 #define MC_CMD_PHY_CAP_25000FDX_WIDTH 1
3598 #define MC_CMD_PHY_CAP_50000FDX_WIDTH 1
3601 #define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
3604 #define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
3607 #define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
3610 #define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
3613 #define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
3616 #define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
3619 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
3622 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
3625 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
3631 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
3647 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
3676 #define MC_CMD_START_BIST_IN_LEN 4
3679 #define MC_CMD_START_BIST_IN_TYPE_LEN 4
3722 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
3729 /* enum: Timed-out. */
3731 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
3732 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
3738 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3741 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
3742 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
3744 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
3746 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
3748 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
3751 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
3756 /* enum: Intra-pair short. */
3758 /* enum: Inter-pair short. */
3764 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
3769 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
3774 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
3782 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3785 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
3786 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
3810 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3813 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
3814 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
3817 /* enum: RAM test - walk ones. */
3819 /* enum: RAM test - walk zeros. */
3821 /* enum: RAM test - walking inversions zeros/ones. */
3823 /* enum: RAM test - walking inversions checkerboard. */
3825 /* enum: Register test - set / clear individual bits. */
3831 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
3834 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
3855 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
3858 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
3861 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
3864 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
3867 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
3882 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
3885 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3886 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
3888 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
3889 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
3915 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
3950 /* enum: PMA-PMD. */
3952 /* enum: Cross-Port. */
3954 /* enum: XGMII-Wireside. */
3970 /* enum: PMA lanes MAC-Serdes. */
3976 /* enum: PMA lanes MAC-Serdes Wireside. */
4031 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
4066 /* enum: PMA-PMD. */
4068 /* enum: Cross-Port. */
4070 /* enum: XGMII-Wireside. */
4086 /* enum: PMA lanes MAC-Serdes. */
4092 /* enum: PMA lanes MAC-Serdes Wireside. */
4160 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
4161 #define AN_TYPE_LEN 4
4163 #define AN_TYPE_TYPE_LEN 4
4166 /* enum: Clause 28 - BASE-T */
4168 /* enum: Clause 37 - BASE-X */
4170 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
4171 * assemblies. Includes Clause 72/Clause 92 link-training.
4179 #define FEC_TYPE_LEN 4
4181 #define FEC_TYPE_TYPE_LEN 4
4184 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
4186 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */
4207 /* Near-side advertised capabilities. Refer to
4211 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4
4212 /* Link-partner advertised capabilities. Refer to
4215 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
4216 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
4218 * reads non-zero.
4221 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
4224 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
4228 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
4231 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
4233 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
4234 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
4237 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
4240 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
4243 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
4246 #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
4249 #define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1
4252 #define MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1
4255 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
4259 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
4262 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
4264 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
4265 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
4268 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
4271 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
4275 /* Near-side advertised capabilities. Refer to
4279 #define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
4280 /* Link-partner advertised capabilities. Refer to
4283 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
4284 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
4286 * reads non-zero.
4289 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
4292 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
4296 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
4299 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
4301 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
4302 #define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
4305 #define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
4308 #define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
4311 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
4314 #define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
4317 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1
4320 #define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1
4323 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
4327 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
4330 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
4332 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
4333 /* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
4336 /* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
4339 /* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
4341 * e.g. plugged-in module). In general, subset of
4344 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
4348 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
4349 /* Auto-negotiation type used on the link */
4351 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
4356 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
4360 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
4363 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
4365 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
4366 #define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
4369 #define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
4372 #define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
4374 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
4375 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
4378 #define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
4381 #define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
4384 #define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
4387 #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
4390 #define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1
4405 /* Near-side advertised capabilities. Refer to
4409 #define MC_CMD_SET_LINK_IN_CAP_LEN 4
4411 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
4412 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
4413 #define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
4415 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
4416 #define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
4417 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
4418 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
4419 #define MC_CMD_SET_LINK_IN_TXDIS_OFST 4
4421 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
4422 #define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
4424 #define MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1
4427 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
4434 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
4441 /* Near-side advertised capabilities. Refer to
4445 #define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
4447 #define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
4448 #define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
4449 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
4451 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1
4452 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
4453 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1
4454 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1
4455 #define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
4457 #define MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1
4458 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
4460 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1
4463 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
4470 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
4472 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1
4478 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1
4494 #define MC_CMD_SET_ID_LED_IN_LEN 4
4497 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
4521 #define MC_CMD_SET_MAC_IN_MTU_LEN 4
4522 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
4523 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
4529 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4
4532 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
4534 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
4535 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
4537 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
4551 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
4554 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
4562 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
4563 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
4564 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
4570 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
4573 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
4575 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
4576 #define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
4578 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
4592 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
4595 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
4602 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
4605 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
4607 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
4608 #define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
4611 #define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
4614 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
4616 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
4617 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
4623 #define MC_CMD_SET_MAC_V2_OUT_LEN 4
4629 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
4638 * statistics are dmad to that (page-aligned location). Locks required: None.
4652 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
4660 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
4664 /* enum: PMA-PMD Link Up. */
4666 /* enum: PMA-PMD RX Fault. */
4668 /* enum: PMA-PMD TX Fault. */
4670 /* enum: PMA-PMD Signal */
4672 /* enum: PMA-PMD SNR A. */
4674 /* enum: PMA-PMD SNR B. */
4676 /* enum: PMA-PMD SNR C. */
4678 /* enum: PMA-PMD SNR D. */
4700 /* enum: AN link-up. */
4706 /* enum: Clause 22 Link-Up. */
4719 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
4734 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
4736 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4
4739 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
4741 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
4742 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
4745 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
4748 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
4750 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
4751 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
4754 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
4764 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
4767 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
4777 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
4876 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
4917 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
4919 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
4920 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
4933 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
4937 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
4940 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
4943 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
4945 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
4947 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
4949 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
4966 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
5001 * or not 32-bit aligned
5040 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
5073 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4
5074 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
5075 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4
5077 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
5082 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
5083 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
5084 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
5090 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
5093 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
5094 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
5104 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
5115 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
5147 #define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
5151 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
5171 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
5174 /* A type value of 1 is unused. */
5175 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
5176 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
5192 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
5198 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5199 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5200 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5209 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5210 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5211 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5213 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
5215 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
5224 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5225 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5226 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5239 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5240 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5241 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5247 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
5249 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
5251 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
5256 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5257 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5258 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5260 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
5263 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
5265 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
5266 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
5269 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
5271 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
5284 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
5286 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
5303 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
5305 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
5344 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
5347 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
5403 #define MC_CMD_NVRAM_INFO_IN_LEN 4
5405 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
5412 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
5415 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
5416 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
5418 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
5420 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
5423 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
5425 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
5426 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
5429 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
5432 #define MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1
5435 #define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
5438 #define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
5441 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
5443 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
5445 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
5450 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
5453 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
5454 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
5456 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
5458 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
5461 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
5463 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
5464 #define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
5467 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
5470 #define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
5473 #define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
5475 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
5477 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
5481 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
5502 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
5504 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
5515 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
5518 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
5519 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
5520 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
5522 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
5542 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
5545 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
5546 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
5549 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
5554 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
5557 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
5558 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
5561 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
5565 * from. This allows it to perform a read-modify-write-verify with the write
5571 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
5581 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
5587 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1
5590 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
5591 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
5593 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
5594 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
5614 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
5615 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
5617 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
5620 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
5621 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
5623 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
5625 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
5626 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
5648 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
5651 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
5652 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
5654 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
5680 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
5683 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
5684 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
5693 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
5696 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
5697 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
5699 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
5702 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
5704 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1
5705 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1
5708 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
5727 * per-partition nvram lock in firmware is only released after the verification
5730 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
5733 * the field are marked with a prefix 'Internal-error'.
5736 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
5737 /* enum: Invalid return code; only non-zero values are defined. Defined as
5749 /* enum: Error in message digest calculated over the reflash-header, payload
5750 * and reflash-trailer.
5767 /* enum: The image contains a test-signed certificate, but the adapter accepts
5773 /* enum: Internal-error. The signed image is missing the 'contents' section,
5777 /* enum: Internal-error. The bundle header is invalid. */
5779 /* enum: Internal-error. The bundle does not have a valid reflash image layout.
5782 /* enum: Internal-error. The bundle has an inconsistent layout of components or
5786 /* enum: Internal-error. The bundle manifest is inconsistent with components in
5790 /* enum: Internal-error. The number of components in a bundle do not match the
5794 /* enum: Internal-error. The bundle contains too many components for the MC
5798 /* enum: Internal-error. The bundle manifest has an invalid/inconsistent
5802 /* enum: Internal-error. The hash of a component does not match the hash stored
5806 /* enum: Internal-error. Component hash calculation failed. */
5808 /* enum: Internal-error. The component does not have a valid reflash image
5816 /* enum: The update operation is in-progress. */
5829 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
5835 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
5844 #define MC_CMD_REBOOT_IN_LEN 4
5846 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4
5868 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
5871 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
5872 #define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
5874 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
5875 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
5891 #define MC_CMD_REBOOT_MODE_IN_LEN 4
5893 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
5896 /* enum: Power-on Reset. */
5904 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
5907 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
5909 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
5952 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
5957 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
5960 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
5968 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
5971 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
5973 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
5974 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
5975 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
5977 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1
5980 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
5983 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
5984 #define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
5986 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
5997 /* enum: Phy 1 temperature: degC */
5999 /* enum: Phy 1 cooling: bool */
6027 /* enum: Fan 1 speed: RPM */
6033 /* enum: Fan 4 speed: RPM */
6079 /* enum: Port 0 PHY power switch over-current: bool */
6081 /* enum: Port 1 PHY power switch over-current: bool */
6083 /* enum: Mop-up microcontroller reference voltage: mV */
6097 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
6099 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */
6101 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
6103 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */
6137 /* enum: Temperature of SODIMM 1 (if installed): degC */
6141 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
6161 /* enum: Engineering sensor 1 */
6167 /* enum: Engineering sensor 4 */
6180 #define MC_CMD_SENSOR_ENTRY_OFST 4
6182 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
6189 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
6192 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
6193 #define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
6195 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
6200 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
6202 /* MC_CMD_SENSOR_ENTRY_OFST 4 */
6204 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
6220 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
6254 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6262 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
6266 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6274 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
6277 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
6281 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6289 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
6292 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
6295 #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
6298 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1
6307 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
6313 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
6329 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
6351 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
6353 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
6362 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
6389 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
6391 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
6396 * Add a protocol offload to NIC for lights-out state. Locks required: None.
6408 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
6409 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
6411 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
6414 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
6415 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
6416 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
6423 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
6424 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
6427 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
6432 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
6433 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
6441 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
6443 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
6448 * Remove a protocol offload from NIC for lights-out state. Locks required:
6459 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
6460 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
6461 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
6482 * Deliberately trigger an assert-detonation in the firmware for testing
6498 #define MC_CMD_TESTASSERT_V2_IN_LEN 4
6501 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
6524 * understand the given workaround number - which should not be treated as a
6526 * workaround, that's between the driver and the mcfw on a per-workaround
6538 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
6548 * - before adding code that queries this workaround, remember that there's
6563 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
6566 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
6567 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
6575 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
6577 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
6580 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
6585 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
6588 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
6589 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
6598 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
6600 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
6606 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
6607 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
6610 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
6611 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
6612 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
6613 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
6629 #define MC_CMD_NVRAM_TEST_IN_LEN 4
6631 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
6636 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
6638 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
6657 /* 0-6 low->high de-emph. */
6659 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
6660 /* 0-8 low->high ref.V */
6661 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
6662 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
6663 /* 0-8 0-8 low->high boost */
6665 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
6666 /* 0-8 low->high ref.V */
6668 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
6677 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
6679 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
6680 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
6683 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
6692 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
6704 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
6707 /* interpretation is is sensor-specific. */
6708 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
6709 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
6710 /* interpretation is is sensor-specific. */
6712 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
6713 /* interpretation is is sensor-specific. */
6715 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
6716 /* interpretation is is sensor-specific. */
6718 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
6735 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
6736 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
6737 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
6739 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
6741 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
6758 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
6761 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
6762 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
6765 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
6767 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
6768 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
6785 #define MC_CMD_NVRAM_METADATA_IN_LEN 4
6788 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
6794 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
6795 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
6798 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
6799 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
6800 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
6801 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
6803 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
6804 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
6805 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
6806 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
6807 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
6809 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
6812 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
6813 /* 1st component of W.X.Y.Z version number for content of this partition */
6822 /* 4th component of W.X.Y.Z version number for content of this partition */
6825 /* Zero-terminated string describing the content of this partition */
6827 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
6855 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
6858 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
6863 * Perform a CLP related operation, see SF-110495-PS for details of CLP
6865 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,
6866 * SF-120509-TC and SF-117282-PS.
6874 #define MC_CMD_CLP_IN_LEN 4
6877 #define MC_CMD_CLP_IN_OP_LEN 4
6893 #define MC_CMD_CLP_IN_DEFAULT_LEN 4
6895 /* MC_CMD_CLP_IN_OP_LEN 4 */
6903 /* MC_CMD_CLP_IN_OP_LEN 4 */
6905 * restores the permanent (factory-programmed) MAC address associated with the
6906 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
6908 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
6920 /* MC_CMD_CLP_IN_OP_LEN 4 */
6922 * restores the permanent (factory-programmed) MAC address associated with the
6923 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
6925 #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4
6931 #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4
6934 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1
6937 #define MC_CMD_CLP_IN_GET_MAC_LEN 4
6939 /* MC_CMD_CLP_IN_OP_LEN 4 */
6944 /* MC_CMD_CLP_IN_OP_LEN 4 */
6945 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4
6946 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4
6947 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4
6949 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1
6963 /* MC_CMD_CLP_IN_OP_LEN 4 */
6965 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
6966 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
6972 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4
6974 /* MC_CMD_CLP_IN_OP_LEN 4 */
6977 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4
6980 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
6982 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
6996 #define MC_CMD_MUM_IN_LEN 4
6998 #define MC_CMD_MUM_IN_OP_HDR_LEN 4
7036 #define MC_CMD_MUM_IN_NULL_LEN 4
7039 #define MC_CMD_MUM_IN_CMD_LEN 4
7042 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4
7045 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7051 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7053 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4
7054 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4
7057 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
7059 /* 32-bit address to read from */
7061 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4
7064 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
7070 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
7071 #define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
7074 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7076 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
7077 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
7080 /* 32-bit address to write to */
7082 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
7085 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
7086 #define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
7094 #define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
7095 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
7098 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7100 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
7101 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
7104 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
7107 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
7110 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
7111 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
7119 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7120 #define MC_CMD_MUM_IN_LOG_OP_OFST 4
7121 #define MC_CMD_MUM_IN_LOG_OP_LEN 4
7127 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7128 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */
7129 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */
7132 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
7138 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7139 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4
7140 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4
7141 #define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4
7154 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7155 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
7156 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
7161 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7162 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
7163 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
7164 /* The first 32-bit word to be written to the GPIO OUT register. */
7166 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
7167 /* The second 32-bit word to be written to the GPIO OUT register. */
7169 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
7174 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7175 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
7176 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
7181 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7182 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
7183 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
7184 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
7186 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
7187 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
7189 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
7194 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7195 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
7196 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
7201 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7202 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
7203 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
7204 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4
7211 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4
7218 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7219 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
7220 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
7225 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7226 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
7227 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
7228 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4
7235 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7236 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
7237 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
7238 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4
7245 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7246 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
7247 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
7248 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4
7256 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7257 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
7258 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
7259 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4
7262 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4
7270 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7271 /* Bit-mask of clocks to be programmed */
7272 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
7273 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
7279 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
7282 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
7284 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
7285 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
7288 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
7294 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7296 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
7297 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
7300 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
7303 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7309 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7310 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4
7311 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4
7312 #define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4
7314 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
7322 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4
7327 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7328 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
7329 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
7331 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
7333 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
7338 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7339 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
7340 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
7342 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
7344 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
7346 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
7348 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
7353 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7354 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
7355 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
7357 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
7362 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7363 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
7364 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
7366 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
7368 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
7373 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7374 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
7375 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
7377 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
7382 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7383 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
7384 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
7386 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
7389 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
7392 /* MC_CMD_MUM_IN_CMD_LEN 4 */
7403 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
7404 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
7406 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
7410 #define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
7413 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
7414 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
7417 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
7418 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
7423 #define MC_CMD_MUM_OUT_READ_LENMIN 4
7426 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
7427 #define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
7429 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
7430 #define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
7445 /* The first 32-bit word read from the GPIO IN register. */
7447 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
7448 /* The second 32-bit word read from the GPIO IN register. */
7449 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
7450 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
7457 /* The first 32-bit word read from the GPIO OUT register. */
7459 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
7460 /* The second 32-bit word read from the GPIO OUT register. */
7461 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
7462 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
7470 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
7471 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
7472 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
7475 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
7477 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
7489 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
7492 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
7493 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
7495 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
7496 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
7510 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
7512 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
7518 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
7520 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
7528 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
7529 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
7530 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
7531 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4
7533 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
7534 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4
7535 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
7536 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
7539 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
7541 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
7547 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
7548 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
7551 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
7552 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
7553 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
7554 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
7561 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
7562 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
7563 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
7566 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
7568 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
7575 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
7578 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
7586 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
7587 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
7599 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
7610 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
7613 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
7618 /* enum: Values 5-15 are reserved for future usage */
7628 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
7654 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
7658 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
7659 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
7664 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
7669 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
7674 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
7679 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
7692 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
7695 /* A human-readable name for the sensor (zero terminated string, max 32 bytes)
7697 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
7705 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
7731 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
7735 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
7736 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
7741 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
7765 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
7800 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
7801 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
7806 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
7810 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
7811 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
7814 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
7842 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
7843 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
7846 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
7856 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
7891 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
7892 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
7895 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
7905 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
7928 #define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
7929 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
7932 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
7954 #define EVB_PORT_ID_LEN 4
7956 #define EVB_PORT_ID_PORT_ID_LEN 4
7963 /* enum: External network port 1 */
7978 #define EVB_VLAN_TAG_MODE_WIDTH 4
7996 /* the raw 64-bit address field from the SMC, not adjusted for page size */
7997 #define BUFTBL_ENTRY_RAWADDR_OFST 4
7999 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
8022 /* enum: Expansion ROM configuration data for port 1 */
8028 /* enum: Non-volatile log output partition */
8030 /* enum: Non-volatile log output of second core on dual-core device */
8048 /* enum: Non-volatile log output partition for FC */
8056 /* enum: MUM Non-volatile log output partition. */
8080 /* enum: Spare partition 4 */
8101 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
8111 /* enum: Bundle update non-volatile log output partition */
8127 #define LICENSED_APP_ID_LEN 4
8129 #define LICENSED_APP_ID_ID_LEN 4
8154 /* enum: Capture SolarSystem 1G */
8171 #define LICENSED_FEATURES_MASK_HI_OFST 4
8174 #define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
8176 #define LICENSED_FEATURES_PIO_LBN 1
8177 #define LICENSED_FEATURES_PIO_WIDTH 1
8180 #define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
8183 #define LICENSED_FEATURES_CLOCK_WIDTH 1
8185 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
8186 #define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
8189 #define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
8192 #define LICENSED_FEATURES_RX_SNIFF_WIDTH 1
8195 #define LICENSED_FEATURES_TX_SNIFF_WIDTH 1
8198 #define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
8201 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
8211 #define LICENSED_V3_APPS_MASK_HI_OFST 4
8214 #define LICENSED_V3_APPS_ONLOAD_WIDTH 1
8216 #define LICENSED_V3_APPS_PTP_LBN 1
8217 #define LICENSED_V3_APPS_PTP_WIDTH 1
8220 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
8223 #define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
8225 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4
8226 #define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
8229 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
8232 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
8235 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
8238 #define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
8241 #define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
8244 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
8247 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
8250 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
8253 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1
8256 #define LICENSED_V3_APPS_DSHBRD_WIDTH 1
8259 #define LICENSED_V3_APPS_SCATRD_WIDTH 1
8269 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4
8272 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
8274 #define LICENSED_V3_FEATURES_PIO_LBN 1
8275 #define LICENSED_V3_FEATURES_PIO_WIDTH 1
8278 #define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
8281 #define LICENSED_V3_FEATURES_CLOCK_WIDTH 1
8283 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
8284 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
8287 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
8290 #define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
8293 #define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
8296 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
8299 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
8313 #define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
8335 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
8341 #define RSS_MODE_LEN 1
8342 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
8343 * be considered as 4 bits selecting which fields are included in the hash. (A
8346 * but only 4 bits are relevant.
8349 #define RSS_MODE_HASH_SELECTOR_LEN 1
8352 #define RSS_MODE_HASH_SRC_ADDR_WIDTH 1
8354 #define RSS_MODE_HASH_DST_ADDR_LBN 1
8355 #define RSS_MODE_HASH_DST_ADDR_WIDTH 1
8358 #define RSS_MODE_HASH_SRC_PORT_WIDTH 1
8361 #define RSS_MODE_HASH_DST_PORT_WIDTH 1
8366 #define CTPIO_STATS_MAP_LEN 4
8396 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
8400 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4
8407 * end with an address for each 4k of host memory required to back the EVQ.
8419 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
8422 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
8426 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
8427 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
8431 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
8432 /* The reload value is ignored in one-shot modes */
8434 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
8437 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
8440 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
8442 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
8443 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
8446 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
8449 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
8451 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
8452 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
8455 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
8458 #define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
8460 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
8467 /* enum: Hold-off */
8471 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
8477 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
8480 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
8491 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
8492 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8497 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
8502 #define MC_CMD_INIT_EVQ_OUT_LEN 4
8505 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
8512 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
8515 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
8519 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
8520 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
8524 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
8525 /* The reload value is ignored in one-shot modes */
8527 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
8530 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
8533 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
8535 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
8536 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
8539 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
8542 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
8544 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
8545 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
8548 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
8551 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
8554 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
8558 * over-ridden by firmware based on licenses and firmware variant in order to
8564 * over-ridden by firmware based on licenses and firmware variant in order to
8569 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
8576 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 1
8578 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
8585 /* enum: Hold-off */
8589 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
8595 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
8598 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
8609 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
8610 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8615 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
8623 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
8625 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
8626 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
8627 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
8629 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
8630 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
8631 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
8632 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
8633 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
8635 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
8636 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
8638 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
8641 #define QUEUE_CRC_MODE_LEN 1
8643 #define QUEUE_CRC_MODE_MODE_WIDTH 4
8656 #define QUEUE_CRC_MODE_SPARE_LBN 4
8657 #define QUEUE_CRC_MODE_SPARE_WIDTH 4
8663 * arguments end with an address for each 4k of host memory required to back
8678 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
8681 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
8684 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
8685 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
8688 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
8693 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
8696 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
8699 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
8701 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
8702 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
8705 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
8708 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
8711 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
8714 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
8717 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8720 #define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
8723 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
8724 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8726 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
8727 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8732 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
8742 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
8746 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
8747 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
8753 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
8758 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
8761 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
8764 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
8766 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
8767 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
8770 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
8773 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
8776 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
8779 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
8782 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8785 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
8791 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
8792 * multiple fixed-size packet buffers within each bucket. For a full
8793 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
8801 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
8812 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
8815 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
8818 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1
8821 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
8822 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8824 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
8825 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8833 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
8839 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
8843 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
8844 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
8850 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
8855 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
8858 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
8861 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
8863 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
8864 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
8867 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
8870 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
8873 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
8876 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
8879 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8882 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
8888 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
8889 * multiple fixed-size packet buffers within each bucket. For a full
8890 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
8898 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
8909 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
8912 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
8915 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1
8918 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
8919 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
8921 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
8922 /* 64-bit address of 4k of 4k-aligned host memory buffer */
8930 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
8936 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
8943 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
8949 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
8957 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
8965 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
8969 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
8970 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
8976 #define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
8981 #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
8984 #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
8987 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1
8989 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1
8990 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1
8993 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1
8996 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
8999 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1
9002 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1
9005 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1
9008 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
9014 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
9015 * multiple fixed-size packet buffers within each bucket. For a full
9016 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
9024 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
9035 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
9038 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
9041 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1
9044 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
9045 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
9047 #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
9048 /* 64-bit address of 4k of 4k-aligned host memory buffer */
9056 #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
9062 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
9069 #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
9075 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
9083 #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
9086 #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
9088 * to zero if using this message on non-QDMA based platforms. Currently in
9090 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
9096 #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
9104 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
9108 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
9109 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
9115 #define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
9120 #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
9123 #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
9126 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1
9128 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1
9129 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1
9132 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1
9135 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
9138 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1
9141 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1
9144 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1
9147 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
9153 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
9154 * multiple fixed-size packet buffers within each bucket. For a full
9155 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
9163 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
9174 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
9177 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
9180 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
9183 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
9184 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
9186 #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
9187 /* 64-bit address of 4k of 4k-aligned host memory buffer */
9195 #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
9201 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
9208 #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
9214 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
9222 #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
9225 #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
9227 * to zero if using this message on non-QDMA based platforms. Currently in
9229 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
9235 #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
9242 #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
9275 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
9278 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
9282 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
9283 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
9286 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
9291 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
9294 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
9297 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
9299 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
9300 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
9303 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
9306 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
9308 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
9309 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
9312 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
9315 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
9318 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
9321 #define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
9324 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
9325 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
9327 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
9328 /* 64-bit address of 4k of 4k-aligned host memory buffer */
9333 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
9343 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
9347 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
9348 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
9351 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
9356 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
9359 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
9362 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
9364 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
9365 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
9368 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
9371 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
9373 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
9374 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
9377 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
9380 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
9383 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
9386 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
9389 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
9392 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
9395 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1
9398 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 1
9401 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 1
9404 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
9405 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
9407 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
9408 /* 64-bit address of 4k of 4k-aligned host memory buffer */
9413 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
9418 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
9421 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
9423 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
9443 #define MC_CMD_FINI_EVQ_IN_LEN 4
9448 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
9464 #define MC_CMD_FINI_RXQ_IN_LEN 4
9467 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
9483 #define MC_CMD_FINI_TXQ_IN_LEN 4
9486 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
9505 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
9506 /* Bits 0 - 63 of event */
9507 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
9509 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
9529 #define MC_CMD_PROXY_CMD_IN_LEN 4
9532 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
9550 #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4
9556 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4
9581 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4
9599 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4
9602 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_WIDTH 1
9606 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
9608 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
9612 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
9622 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
9633 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
9636 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4
9644 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4
9647 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1
9651 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
9653 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
9657 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
9667 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
9678 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
9681 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4
9686 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4
9707 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4
9708 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4
9709 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4
9725 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4
9746 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
9750 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
9751 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
9756 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
9757 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
9758 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
9761 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
9778 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)
9780 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
9782 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
9783 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
9786 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
9792 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
9809 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
9811 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
9830 #define MC_CMD_FILTER_OP_IN_OP_LEN 4
9831 /* enum: single-recipient filter insert */
9833 /* enum: single-recipient filter remove */
9835 /* enum: multi-recipient filter subscribe */
9837 /* enum: multi-recipient filter unsubscribe */
9839 /* enum: replace one recipient with another (warning - the filter handle may
9844 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
9846 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
9848 /* The port ID associated with the v-adaptor which should contain this filter.
9851 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
9854 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
9857 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
9859 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
9860 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
9863 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
9866 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
9868 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
9869 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
9872 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
9875 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
9878 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
9881 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
9884 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
9887 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
9890 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
9893 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
9896 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
9899 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
9908 /* enum: loop back to TXDP 1 */
9912 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
9915 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
9920 /* enum: receive to multiple queues using .1p mapping */
9925 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
9930 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
9933 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
9939 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
9944 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
9946 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
9947 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
9974 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
9975 /* Firmware defined register 1 to match (reserved; set to 0) */
9977 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
9996 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
10000 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
10002 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
10004 /* The port ID associated with the v-adaptor which should contain this filter.
10007 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
10010 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
10013 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
10015 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
10016 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
10019 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
10022 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
10024 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
10025 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
10028 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
10031 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
10034 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
10037 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
10040 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
10043 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
10046 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
10049 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
10052 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
10055 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
10058 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
10061 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
10064 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
10067 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
10070 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
10073 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
10076 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
10079 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
10082 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
10085 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
10088 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
10091 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
10094 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
10097 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
10106 /* enum: loop back to TXDP 1 */
10110 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
10113 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
10118 /* enum: receive to multiple queues using .1p mapping */
10123 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
10128 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
10131 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
10137 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
10142 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
10144 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
10145 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
10172 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
10175 * VXLAN/NVGRE, or 1 for Geneve)
10178 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
10248 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
10249 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
10253 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
10274 #define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
10278 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
10280 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
10282 /* The port ID associated with the v-adaptor which should contain this filter.
10285 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
10288 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
10291 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
10293 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
10294 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
10297 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
10300 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
10302 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
10303 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
10306 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
10309 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
10312 #define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
10315 #define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
10318 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
10321 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
10324 #define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
10327 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
10330 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
10333 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
10336 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
10339 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
10342 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
10345 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
10348 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
10351 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
10354 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
10357 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
10360 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
10363 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
10366 #define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
10369 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
10372 #define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
10375 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
10384 /* enum: loop back to TXDP 1 */
10388 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
10391 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
10396 /* enum: receive to multiple queues using .1p mapping */
10401 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
10406 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
10409 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
10415 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
10420 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
10422 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
10423 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
10450 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
10453 * VXLAN/NVGRE, or 1 for Geneve)
10456 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
10526 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
10527 /* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
10531 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
10544 * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything
10549 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
10567 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
10573 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4
10580 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
10582 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
10593 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
10600 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
10602 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
10610 * Get information related to the parser-dispatcher subsystem
10618 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
10621 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
10628 /* enum: read properties relating to security rules (Medford-only; for use by
10629 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
10646 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
10647 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
10650 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
10654 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
10655 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
10660 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
10669 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
10673 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
10674 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
10675 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
10677 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
10688 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
10689 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
10692 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
10696 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
10697 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
10702 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
10710 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
10726 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4
10746 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
10747 #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
10754 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
10760 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4
10763 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4
10768 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4
10769 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
10771 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4
10772 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
10774 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4
10777 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4
10786 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4
10790 /* up to 8 32-bit words of additional soft state from the LUE manager (the
10791 * exact content is firmware-dependent and intended only for debug use)
10797 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
10798 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
10816 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1
10819 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
10829 #define MC_CMD_SET_PF_COUNT_IN_LEN 4
10832 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4
10851 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
10854 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
10867 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
10870 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
10889 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
10891 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
10892 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
10894 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
10900 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
10904 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
10905 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
10911 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
10915 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
10916 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
10919 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
10955 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
10957 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
10958 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
10960 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
10963 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
10966 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
10969 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
10985 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
10987 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
10988 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
10990 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
10993 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
10998 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
11003 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
11026 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
11030 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
11031 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
11034 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
11047 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4
11050 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
11061 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
11084 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
11176 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
11179 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
11192 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
11195 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
11211 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
11214 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
11217 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
11218 /* Transaction processing steering hint 1 for use with the Rx Queue. */
11220 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
11222 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
11223 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
11226 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
11229 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
11232 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
11235 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
11237 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
11253 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
11254 /* Transaction processing steering hint 1 for use with the Rx Queue. */
11255 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
11256 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
11259 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
11262 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
11265 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
11268 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
11271 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
11272 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
11273 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
11289 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
11291 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
11304 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4
11308 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
11309 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4
11310 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4
11312 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
11313 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4
11314 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
11316 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4
11318 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
11319 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 4
11320 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
11321 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
11322 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 4
11324 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
11325 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4
11327 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
11328 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4
11329 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
11331 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4
11333 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
11334 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 4
11335 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
11336 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
11337 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4
11339 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
11340 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4
11343 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4
11346 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 4
11349 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 4
11350 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
11352 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 4
11355 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4
11358 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4
11375 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
11379 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
11380 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4
11381 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 4
11383 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
11384 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 4
11386 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
11387 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 4
11388 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
11389 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
11390 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 4
11392 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
11393 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 4
11395 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
11396 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 4
11398 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
11399 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 4
11400 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
11401 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
11402 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 4
11404 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
11405 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 4
11408 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 4
11411 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 4
11412 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
11414 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 4
11417 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4
11420 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4
11440 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
11442 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
11444 * be a checksum (a simple 32-bit sum) of the transferred data. An individual
11447 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
11450 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
11458 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
11459 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4)
11464 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4
11473 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
11474 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4
11507 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
11511 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4
11518 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4
11521 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
11522 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
11530 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4
11532 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
11533 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4
11571 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
11574 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
11576 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
11577 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
11580 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
11583 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
11586 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
11589 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
11592 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
11595 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
11598 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
11601 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
11604 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
11607 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
11610 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
11613 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
11616 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
11619 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
11622 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
11625 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
11628 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
11631 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
11634 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
11637 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
11640 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
11643 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
11646 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
11649 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
11652 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
11655 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
11658 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
11660 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
11674 /* enum: RXDP Test firmware image 1 */
11680 /* enum: RXDP Test firmware image 4 */
11709 /* enum: TXDP Test firmware image 1 */
11722 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
11723 /* enum: reserved value - do not use (may indicate alternative interpretation
11734 /* enum: RX PD firmware with approximately Siena-compatible behaviour
11756 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11773 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
11774 /* enum: reserved value - do not use (may indicate alternative interpretation
11785 /* enum: TX PD firmware with approximately Siena-compatible behaviour
11804 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11812 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
11815 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
11824 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
11827 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
11829 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
11830 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
11833 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
11836 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
11839 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
11842 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
11845 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
11848 …efine MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
11851 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
11854 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
11857 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
11860 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
11863 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
11866 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
11869 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
11872 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
11875 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
11878 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
11881 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
11884 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
11887 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
11890 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
11893 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
11896 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
11899 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
11902 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
11905 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
11908 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
11911 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
11913 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
11927 /* enum: RXDP Test firmware image 1 */
11933 /* enum: RXDP Test firmware image 4 */
11962 /* enum: TXDP Test firmware image 1 */
11975 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
11976 /* enum: reserved value - do not use (may indicate alternative interpretation
11987 /* enum: RX PD firmware with approximately Siena-compatible behaviour
12009 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12026 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
12027 /* enum: reserved value - do not use (may indicate alternative interpretation
12038 /* enum: TX PD firmware with approximately Siena-compatible behaviour
12057 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12065 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
12068 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
12071 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
12074 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
12076 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
12077 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
12080 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
12083 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
12085 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
12086 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
12089 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
12092 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
12095 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
12098 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
12101 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
12104 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
12107 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
12110 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
12113 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
12116 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
12119 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
12122 #define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1
12125 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1
12128 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
12131 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
12134 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
12137 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
12140 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
12143 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
12146 #define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
12149 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
12152 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
12155 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1
12158 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
12161 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
12164 #define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1
12167 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1
12170 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1
12173 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
12175 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
12184 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
12203 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
12212 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
12217 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
12222 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
12234 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
12237 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
12239 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
12240 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
12243 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
12246 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
12249 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
12252 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
12255 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
12258 …efine MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
12261 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
12264 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
12267 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
12270 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
12273 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
12276 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
12279 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
12282 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
12285 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
12288 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
12291 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
12294 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
12297 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
12300 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
12303 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
12306 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
12309 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
12312 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
12315 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
12318 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
12321 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
12323 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
12337 /* enum: RXDP Test firmware image 1 */
12343 /* enum: RXDP Test firmware image 4 */
12372 /* enum: TXDP Test firmware image 1 */
12385 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
12386 /* enum: reserved value - do not use (may indicate alternative interpretation
12397 /* enum: RX PD firmware with approximately Siena-compatible behaviour
12419 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12436 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
12437 /* enum: reserved value - do not use (may indicate alternative interpretation
12448 /* enum: TX PD firmware with approximately Siena-compatible behaviour
12467 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12475 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
12478 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
12481 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
12484 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
12486 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
12487 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
12490 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
12493 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
12495 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
12496 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
12499 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
12502 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
12505 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
12508 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
12511 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
12514 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
12517 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
12520 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
12523 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
12526 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
12529 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
12532 #define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1
12535 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1
12538 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
12541 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
12544 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
12547 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
12550 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
12553 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
12556 #define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
12559 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
12562 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
12565 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1
12568 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
12571 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
12574 #define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1
12577 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1
12580 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1
12583 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
12585 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
12594 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
12613 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
12622 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
12627 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1
12632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1
12641 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
12645 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1
12646 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
12650 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
12652 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
12655 * (SF-115995-SW) in the present configuration of firmware and port mode.
12658 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
12660 * (SF-115995-SW) in the present configuration of firmware and port mode.
12669 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
12672 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
12674 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
12675 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
12678 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
12681 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
12684 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
12687 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
12690 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
12693 …efine MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
12696 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
12699 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
12702 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
12705 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
12708 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
12711 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
12714 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
12717 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
12720 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
12723 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
12726 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
12729 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
12732 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
12735 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
12738 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
12741 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
12744 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
12747 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
12750 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
12753 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
12756 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
12758 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
12772 /* enum: RXDP Test firmware image 1 */
12778 /* enum: RXDP Test firmware image 4 */
12807 /* enum: TXDP Test firmware image 1 */
12820 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
12821 /* enum: reserved value - do not use (may indicate alternative interpretation
12832 /* enum: RX PD firmware with approximately Siena-compatible behaviour
12854 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12871 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
12872 /* enum: reserved value - do not use (may indicate alternative interpretation
12883 /* enum: TX PD firmware with approximately Siena-compatible behaviour
12902 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12910 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
12913 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
12916 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
12919 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
12921 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
12922 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
12925 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
12928 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
12930 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
12931 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
12934 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
12937 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
12940 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
12943 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
12946 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
12949 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
12952 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
12955 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
12958 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
12961 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
12964 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
12967 #define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1
12970 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1
12973 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
12976 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
12979 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
12982 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
12985 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
12988 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
12991 #define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
12994 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
12997 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
13000 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1
13003 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
13006 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
13009 #define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1
13012 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1
13015 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1
13018 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
13020 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
13029 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
13048 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
13057 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
13062 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1
13067 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1
13076 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13080 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1
13081 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13085 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13087 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13090 * (SF-115995-SW) in the present configuration of firmware and port mode.
13093 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
13095 * (SF-115995-SW) in the present configuration of firmware and port mode.
13101 * hold at least this many 64-bit stats values, if they wish to receive all
13112 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
13115 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1
13117 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
13118 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1
13121 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1
13124 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13127 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13130 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13133 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1
13136 …efine MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13139 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13142 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13145 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13148 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1
13151 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13154 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1
13157 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1
13160 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1
13163 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1
13166 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1
13169 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1
13172 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1
13175 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1
13178 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1
13181 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1
13184 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13187 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13190 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1
13193 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13196 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1
13199 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1
13201 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
13215 /* enum: RXDP Test firmware image 1 */
13221 /* enum: RXDP Test firmware image 4 */
13250 /* enum: TXDP Test firmware image 1 */
13263 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13264 /* enum: reserved value - do not use (may indicate alternative interpretation
13275 /* enum: RX PD firmware with approximately Siena-compatible behaviour
13297 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13314 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13315 /* enum: reserved value - do not use (may indicate alternative interpretation
13326 /* enum: TX PD firmware with approximately Siena-compatible behaviour
13345 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13353 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
13356 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
13359 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
13362 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1
13364 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1
13365 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1
13368 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1
13371 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1
13373 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
13374 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1
13377 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
13380 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
13383 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
13386 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1
13389 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
13392 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1
13395 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1
13398 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1
13401 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
13404 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1
13407 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1
13410 #define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1
13413 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1
13416 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1
13419 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
13422 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1
13425 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1
13428 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
13431 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
13434 #define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1
13437 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
13440 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1
13443 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1
13446 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
13449 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
13452 #define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1
13455 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1
13458 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1
13461 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
13463 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
13472 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
13491 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1
13500 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
13505 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1
13510 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1
13519 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13523 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1
13524 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13528 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13530 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13533 * (SF-115995-SW) in the present configuration of firmware and port mode.
13536 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
13538 * (SF-115995-SW) in the present configuration of firmware and port mode.
13544 * hold at least this many 64-bit stats values, if they wish to receive all
13551 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
13554 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
13560 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
13563 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1
13565 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
13566 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1
13569 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1
13572 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13575 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13578 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13581 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1
13584 …efine MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13587 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13590 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13593 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13596 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1
13599 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13602 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1
13605 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1
13608 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1
13611 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1
13614 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1
13617 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1
13620 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1
13623 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1
13626 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1
13629 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1
13632 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13635 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13638 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1
13641 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13644 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1
13647 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1
13649 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
13663 /* enum: RXDP Test firmware image 1 */
13669 /* enum: RXDP Test firmware image 4 */
13698 /* enum: TXDP Test firmware image 1 */
13711 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13712 /* enum: reserved value - do not use (may indicate alternative interpretation
13723 /* enum: RX PD firmware with approximately Siena-compatible behaviour
13745 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13762 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13763 /* enum: reserved value - do not use (may indicate alternative interpretation
13774 /* enum: TX PD firmware with approximately Siena-compatible behaviour
13793 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13801 #define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
13804 #define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
13807 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
13810 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1
13812 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1
13813 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1
13816 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1
13819 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1
13821 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
13822 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1
13825 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
13828 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
13831 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
13834 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1
13837 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
13840 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1
13843 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1
13846 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1
13849 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
13852 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1
13855 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1
13858 #define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1
13861 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1
13864 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1
13867 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
13870 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1
13873 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1
13876 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
13879 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
13882 #define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1
13885 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
13888 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1
13891 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1
13894 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
13897 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
13900 #define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1
13903 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1
13906 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1
13909 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
13911 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
13920 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
13939 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 1
13948 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
13953 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 1
13958 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 1
13967 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13971 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 1
13972 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13976 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13978 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13981 * (SF-115995-SW) in the present configuration of firmware and port mode.
13984 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
13986 * (SF-115995-SW) in the present configuration of firmware and port mode.
13992 * hold at least this many 64-bit stats values, if they wish to receive all
13999 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14002 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14012 #define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14019 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
14022 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 1
14024 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
14025 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 1
14028 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 1
14031 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14034 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14037 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14040 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 1
14043 …efine MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14046 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14049 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14052 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14055 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 1
14058 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14061 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 1
14064 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 1
14067 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 1
14070 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 1
14073 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 1
14076 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 1
14079 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 1
14082 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 1
14085 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 1
14088 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 1
14091 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14094 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14097 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 1
14100 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14103 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 1
14106 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 1
14108 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
14122 /* enum: RXDP Test firmware image 1 */
14128 /* enum: RXDP Test firmware image 4 */
14157 /* enum: TXDP Test firmware image 1 */
14170 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14171 /* enum: reserved value - do not use (may indicate alternative interpretation
14182 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14204 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14221 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14222 /* enum: reserved value - do not use (may indicate alternative interpretation
14233 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14252 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14260 #define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
14263 #define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
14266 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
14269 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 1
14271 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 1
14272 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14275 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 1
14278 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 1
14280 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
14281 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 1
14284 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14287 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14290 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14293 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 1
14296 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14299 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 1
14302 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 1
14305 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 1
14308 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14311 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 1
14314 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 1
14317 #define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 1
14320 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 1
14323 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 1
14326 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14329 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 1
14332 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 1
14335 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14338 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14341 #define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 1
14344 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14347 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 1
14350 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 1
14353 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14356 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14359 #define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 1
14362 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 1
14365 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 1
14368 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14370 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14379 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14398 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 1
14407 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
14412 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 1
14417 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 1
14426 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14430 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 1
14431 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14435 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14437 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14440 * (SF-115995-SW) in the present configuration of firmware and port mode.
14443 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14445 * (SF-115995-SW) in the present configuration of firmware and port mode.
14451 * hold at least this many 64-bit stats values, if they wish to receive all
14458 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14461 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14471 #define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14475 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
14478 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 1
14480 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 1
14481 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 1
14484 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
14487 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 1
14489 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
14490 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 1
14493 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
14496 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
14499 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
14505 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
14508 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 1
14510 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
14511 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 1
14514 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 1
14517 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14520 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14523 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14526 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 1
14529 …efine MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14532 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14535 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14538 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14541 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 1
14544 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14547 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 1
14550 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 1
14553 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 1
14556 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 1
14559 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 1
14562 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 1
14565 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 1
14568 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 1
14571 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 1
14574 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 1
14577 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14580 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14583 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 1
14586 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14589 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 1
14592 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 1
14594 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
14608 /* enum: RXDP Test firmware image 1 */
14614 /* enum: RXDP Test firmware image 4 */
14643 /* enum: TXDP Test firmware image 1 */
14656 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14657 /* enum: reserved value - do not use (may indicate alternative interpretation
14668 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14690 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14707 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14708 /* enum: reserved value - do not use (may indicate alternative interpretation
14719 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14738 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14746 #define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
14749 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
14752 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
14755 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 1
14757 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 1
14758 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14761 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 1
14764 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 1
14766 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
14767 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 1
14770 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14773 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14776 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14779 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 1
14782 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14785 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 1
14788 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 1
14791 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 1
14794 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14797 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 1
14800 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 1
14803 #define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 1
14806 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 1
14809 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 1
14812 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14815 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 1
14818 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 1
14821 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14824 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14827 #define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 1
14830 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14833 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 1
14836 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 1
14839 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14842 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14845 #define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 1
14848 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 1
14851 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 1
14854 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14856 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14865 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14884 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 1
14893 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
14898 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 1
14903 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 1
14912 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14916 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 1
14917 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14921 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14923 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14926 * (SF-115995-SW) in the present configuration of firmware and port mode.
14929 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14931 * (SF-115995-SW) in the present configuration of firmware and port mode.
14937 * hold at least this many 64-bit stats values, if they wish to receive all
14944 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14947 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14957 #define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14961 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
14964 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 1
14966 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 1
14967 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 1
14970 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
14973 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 1
14975 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
14976 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 1
14979 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
14982 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
14985 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
14986 /* These bits are reserved for communicating test-specific capabilities to
14987 * host-side test software. All production drivers should treat this field as
14999 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
15002 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 1
15004 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
15005 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 1
15008 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 1
15011 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
15014 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
15017 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
15020 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 1
15023 …efine MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
15026 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15029 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
15032 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
15035 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 1
15038 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
15041 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 1
15044 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 1
15047 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 1
15050 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 1
15053 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 1
15056 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 1
15059 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 1
15062 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 1
15065 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 1
15068 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 1
15071 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15074 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15077 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 1
15080 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15083 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 1
15086 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 1
15088 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
15102 /* enum: RXDP Test firmware image 1 */
15108 /* enum: RXDP Test firmware image 4 */
15137 /* enum: TXDP Test firmware image 1 */
15150 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15151 /* enum: reserved value - do not use (may indicate alternative interpretation
15162 /* enum: RX PD firmware with approximately Siena-compatible behaviour
15184 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15201 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15202 /* enum: reserved value - do not use (may indicate alternative interpretation
15213 /* enum: TX PD firmware with approximately Siena-compatible behaviour
15232 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15240 #define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
15243 #define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
15246 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
15249 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 1
15251 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 1
15252 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 1
15255 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 1
15258 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 1
15260 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
15261 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 1
15264 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
15267 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
15270 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
15273 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 1
15276 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
15279 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 1
15282 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 1
15285 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 1
15288 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15291 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 1
15294 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 1
15297 #define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 1
15300 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 1
15303 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 1
15306 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15309 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 1
15312 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 1
15315 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15318 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15321 #define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 1
15324 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15327 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 1
15330 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 1
15333 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15336 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15339 #define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 1
15342 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 1
15345 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 1
15348 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15350 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15359 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15378 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 1
15387 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
15392 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 1
15397 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 1
15406 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15410 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 1
15411 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15415 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15417 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15420 * (SF-115995-SW) in the present configuration of firmware and port mode.
15423 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
15425 * (SF-115995-SW) in the present configuration of firmware and port mode.
15431 * hold at least this many 64-bit stats values, if they wish to receive all
15438 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
15441 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
15451 #define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
15455 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
15458 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 1
15460 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 1
15461 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 1
15464 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
15467 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 1
15469 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
15470 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 1
15473 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
15476 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
15479 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
15480 /* These bits are reserved for communicating test-specific capabilities to
15481 * host-side test software. All production drivers should treat this field as
15493 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
15499 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
15505 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
15506 /* The maximum number of queues that can be used by an RSS context in even-
15507 * spreading mode. In even-spreading mode the context has no indirection table
15511 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
15517 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
15522 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
15532 #define MC_CMD_V2_EXTN_IN_LEN 4
15537 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
15547 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
15569 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
15572 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4
15585 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
15588 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4
15607 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4
15609 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
15610 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4
15616 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4
15618 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4
15619 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4
15622 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4
15641 #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4
15643 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
15644 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4
15647 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4
15650 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
15652 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_LBN 1
15653 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_NORMAL_WIDTH 1
15656 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_LOW_WIDTH 1
15659 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4
15664 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4
15669 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4
15672 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4
15678 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4
15680 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4
15681 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4
15684 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4
15687 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_WIDTH 1
15689 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_LBN 1
15690 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_NORMAL_WIDTH 1
15693 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_LOW_WIDTH 1
15696 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4
15701 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4
15706 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4
15709 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4
15712 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4
15731 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
15733 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
15734 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
15750 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
15753 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
15761 * allocate and initialise a v-switch.
15770 /* The port to connect to the v-switch's upstream port. */
15772 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15773 /* The type of v-switch to create. */
15774 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
15775 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
15786 /* Flags controlling v-port creation */
15788 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
15791 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
15792 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
15793 * this must be one or greated, and the attached v-ports must have exactly this
15794 * number of tags. For other v-switch types, this must be zero of greater, and
15795 * is an upper limit on the number of VLAN tags for attached v-ports. An error
15797 * v-ports with this number of tags.
15800 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
15808 * de-allocate a v-switch.
15816 #define MC_CMD_VSWITCH_FREE_IN_LEN 4
15817 /* The port to which the v-switch is connected. */
15819 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
15827 * read some config of v-switch. For now this command is an empty placeholder.
15828 * It may be used to check if a v-switch is connected to a given EVB port (if
15837 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4
15838 /* The port to which the v-switch is connected. */
15840 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
15848 * allocate a v-port.
15857 /* The port to which the v-switch is connected. */
15859 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15860 /* The type of the new v-port. */
15861 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
15862 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
15869 /* enum: A normal v-port receives packets which match a specified MAC and/or
15873 /* enum: An expansion v-port packets traffic which don't match any other
15874 * v-port.
15877 /* enum: An test v-port receives packets which match any filters installed by
15881 /* Flags controlling v-port creation */
15883 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
15886 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
15888 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
15889 #define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
15892 * v-switch.
15895 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
15898 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
15907 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4
15908 /* The handle of the new v-port */
15910 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
15915 * de-allocate a v-port.
15923 #define MC_CMD_VPORT_FREE_IN_LEN 4
15924 /* The handle of the v-port */
15926 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
15934 * allocate a v-adaptor.
15943 /* The port to connect to the v-adaptor's port. */
15945 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15946 /* Flags controlling v-adaptor creation */
15948 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
15951 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
15953 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
15954 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15957 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
15960 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
15963 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
15970 /* The MAC address to assign to this v-adaptor */
15982 * de-allocate a v-adaptor.
15990 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4
15991 /* The port to which the v-adaptor is connected. */
15993 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
16001 * assign a new MAC address to a v-adaptor.
16010 /* The port to which the v-adaptor is connected. */
16012 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
16013 /* The new MAC address to assign to this v-adaptor */
16014 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
16023 * read the MAC address assigned to a v-adaptor.
16031 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
16032 /* The port to which the v-adaptor is connected. */
16034 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
16038 /* The MAC address assigned to this v-adaptor */
16045 * read some config of v-adaptor.
16053 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
16054 /* The port to which the v-adaptor is connected. */
16056 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
16062 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
16063 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
16064 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
16065 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
16068 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
16084 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
16086 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
16087 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
16088 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
16091 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
16111 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
16112 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
16113 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
16115 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
16117 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
16118 /* Write enable bits 0-3, set to write, clear to read. */
16120 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
16122 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
16129 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
16130 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
16131 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
16133 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
16135 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
16148 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
16151 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
16154 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
16157 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
16170 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
16173 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
16192 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
16194 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
16195 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
16201 * queues, but the key and indirection table are pre-configured and may not be
16202 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
16211 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
16214 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
16215 * spreading contexts this must be in the range 1 to
16217 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
16221 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
16227 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
16229 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
16230 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
16236 * queues, but the key and indirection table are pre-configured and may not be
16237 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
16246 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
16249 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
16250 * spreading contexts this must be in the range 1 to
16252 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
16256 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
16265 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
16268 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
16274 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
16289 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
16292 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
16311 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
16312 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
16313 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
16330 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
16333 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
16337 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
16338 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
16357 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
16358 /* The 128-byte indirection table (1 byte per entry) */
16359 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
16378 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
16381 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
16385 /* The 128-byte indirection table (1 byte per entry) */
16386 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
16392 * Write a portion of a selectable-size indirection table for an RSS context.
16405 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))
16406 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)
16409 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4
16410 /* An array of index-value pairs to be written to the table. Structure is
16413 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4
16414 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4
16415 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 1
16423 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4
16438 * Read a portion of a selectable-size indirection table for an RSS context.
16451 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))
16452 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)
16455 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4
16457 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4
16459 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 1
16468 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)
16472 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 1
16490 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
16493 * in this case, the MODE fields may be set to non-zero values, and will take
16503 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
16504 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
16505 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
16507 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
16508 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
16509 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
16510 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
16511 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
16513 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
16514 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
16516 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
16517 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
16518 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
16519 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
16520 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
16522 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
16523 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
16525 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
16526 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
16528 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
16529 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
16531 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
16532 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
16534 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
16535 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
16537 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
16553 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
16556 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
16562 * capability), the _EN bits report the state. If any _MODE bits are non-zero
16565 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
16573 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
16574 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
16575 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
16577 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
16578 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
16579 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
16580 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
16581 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
16583 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
16584 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
16586 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
16587 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
16588 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
16589 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
16590 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
16592 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
16593 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
16595 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
16596 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
16598 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
16599 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
16601 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
16602 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
16604 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
16605 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
16607 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
16612 * Allocate a .1p mapping.
16623 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
16624 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed
16625 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
16628 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
16629 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4
16632 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
16633 /* The handle of the new .1p mapping. This should be considered opaque to the
16638 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4
16639 /* enum: guaranteed invalid .1p mapping handle value */
16645 * Free a .1p mapping.
16653 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
16654 /* The handle of the .1p mapping */
16656 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4
16664 * Set the mapping table for a .1p mapping.
16673 /* The handle of the .1p mapping */
16675 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
16676 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
16679 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
16688 * Get the mapping table for a .1p mapping.
16696 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
16697 /* The handle of the .1p mapping */
16699 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
16703 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
16706 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
16726 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4
16728 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
16729 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4
16732 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4
16750 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4
16752 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
16753 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4
16756 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4
16764 * Add a MAC address to a v-port
16773 /* The handle of the v-port */
16775 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
16777 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
16786 * Delete a MAC address from a v-port
16795 /* The handle of the v-port */
16797 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
16799 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
16808 * Delete a MAC address from a v-port
16816 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
16817 /* The handle of the v-port */
16819 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
16822 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
16825 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
16826 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
16829 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
16831 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
16840 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
16841 * has already been passed to another function (v-port's user), then that
16851 /* The handle of the v-port */
16853 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
16855 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
16856 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
16857 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
16859 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
16860 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
16861 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
16862 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
16865 * v-switch.
16868 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
16871 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
16880 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
16884 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
16887 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
16889 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
16892 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
16897 * read some config of v-port.
16905 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4
16906 /* The handle of the v-port */
16908 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
16914 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
16915 /* The number of VLAN tags that may be used on a v-adaptor connected to this
16918 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
16919 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
16938 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
16940 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
16941 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
16948 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12)
16952 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
16967 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
16969 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4
16972 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
16974 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
17000 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
17002 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4
17005 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
17007 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1
17029 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
17031 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
17032 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
17048 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4
17051 /* Requested frequency in MHz for inter-core clock domain */
17052 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
17053 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4
17054 /* enum: Leave the inter-core clock domain frequency unchanged */
17058 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4
17063 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4
17068 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4
17073 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4
17078 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4
17086 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4
17089 /* Resulting inter-core frequency in MHz */
17090 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
17091 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4
17092 /* enum: The inter-core clock domain doesn't exist / isn't used */
17096 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4
17101 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4
17106 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4
17111 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4
17116 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4
17133 #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4
17150 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
17153 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
17155 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_OFST 4
17167 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_OFST 4
17170 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_OFST 4
17173 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_OFST 4
17176 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_OFST 4
17179 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_OFST 4
17187 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_OFST 4
17190 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_OFST 4
17193 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_OFST 4
17196 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_OFST 4
17202 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_OFST 4
17207 /* Register data to write. Only valid in write/write-read. */
17209 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4
17212 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4
17217 #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4
17219 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
17221 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_OFST 4
17224 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_OFST 4
17230 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4
17232 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4
17234 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4
17236 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4
17249 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
17252 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
17268 #define MC_CMD_SHMBOOT_OP_IN_LEN 4
17271 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
17291 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4
17292 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
17293 #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4
17295 #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4
17302 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8)
17306 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
17307 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1
17324 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4
17325 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
17326 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
17330 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
17336 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
17338 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
17340 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
17342 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
17344 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
17347 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
17349 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
17352 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
17358 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
17360 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
17364 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
17368 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
17370 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
17372 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
17374 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
17376 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
17378 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
17380 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
17382 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
17384 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
17387 #define MC_CMD_DUMP_DO_OUT_LEN 4
17389 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
17404 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
17405 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
17406 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
17410 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
17414 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
17416 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
17418 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
17420 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
17422 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
17424 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
17426 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
17428 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
17430 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
17432 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
17436 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
17440 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
17442 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
17444 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
17446 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
17448 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
17450 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
17452 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
17454 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
17456 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
17461 * Adjusts power supply parameters. This is a warranty-voiding operation.
17473 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4
17475 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4
17476 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4
17481 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4
17502 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
17503 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
17504 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
17528 * should we wish to make this reliable; currently requests are fire-and-
17540 #define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num))
17541 #define MC_CMD_UART_SEND_DATA_OUT_DATA_NUM(len) (((len)-16)/1)
17544 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
17546 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
17547 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4
17550 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4
17553 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4
17555 #define MC_CMD_UART_SEND_DATA_OUT_DATA_LEN 1
17578 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4
17580 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
17581 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4
17584 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4
17587 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4
17593 #define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num))
17594 #define MC_CMD_UART_RECV_DATA_IN_DATA_NUM(len) (((len)-16)/1)
17597 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
17599 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
17600 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4
17603 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4
17606 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4
17608 #define MC_CMD_UART_RECV_DATA_IN_DATA_LEN 1
17616 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
17627 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
17629 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
17630 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
17633 #define MC_CMD_READ_FUSES_OUT_LENMIN 4
17636 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
17637 #define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)
17640 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
17642 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
17643 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1
17659 #define MC_CMD_KR_TUNE_IN_LENMIN 4
17662 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
17663 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4)
17666 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
17693 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
17696 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
17697 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
17706 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
17709 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
17711 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
17715 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
17718 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
17719 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
17722 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
17723 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
17729 /* enum: Attenuation (0-15, Huntington) */
17731 /* enum: CTLE Boost (0-15, Huntington) */
17733 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
17734 * positive, Medford - 0-31)
17737 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
17738 * positive, Medford - 0-31)
17741 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
17742 * positive, Medford - 0-16)
17745 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
17746 * positive, Medford - 0-16)
17749 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
17750 * positive, Medford - 0-16)
17753 /* enum: Edge DFE DLEV (0-128 for Medford) */
17755 /* enum: Variable Gain Amplifier (0-15, Medford) */
17757 /* enum: CTLE EQ Capacitor (0-15, Medford) */
17759 /* enum: CTLE EQ Resistor (0-7, Medford) */
17761 /* enum: CTLE gain (0-31, Medford2) */
17763 /* enum: CTLE pole (0-31, Medford2) */
17765 /* enum: CTLE peaking (0-31, Medford2) */
17767 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
17769 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
17771 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
17773 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
17775 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
17777 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
17779 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
17781 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
17783 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
17785 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
17787 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
17789 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
17791 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
17793 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
17796 * (Medford2 - 6 bit signed (-29 - +29)))
17800 * (Medford2 - 6 bit signed (-29 - +29)))
17804 * (Medford2 - 6 bit signed (-29 - +29)))
17808 * (Medford2 - 6 bit signed (-29 - +29)))
17815 /* enum: CTLE Boost stages - retimer lineside (Medford2 with DS250x retimer - 4
17819 /* enum: DFE Tap1 - retimer lineside (Medford2 with DS250x retimer (-31 - 31))
17822 /* enum: DFE Tap2 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
17825 /* enum: DFE Tap3 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
17828 /* enum: DFE Tap4 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
17831 /* enum: DFE Tap5 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
17834 /* enum: CTLE Boost stages - retimer hostside (Medford2 with DS250x retimer - 4
17838 /* enum: DFE Tap1 - retimer hostside (Medford2 with DS250x retimer (-31 - 31))
17841 /* enum: DFE Tap2 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
17844 /* enum: DFE Tap3 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
17847 /* enum: DFE Tap4 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
17850 /* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
17863 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
17866 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
17878 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
17879 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
17882 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
17884 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
17887 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
17888 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
17889 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
17892 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
17897 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
17902 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
17904 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
17905 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
17907 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
17908 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
17911 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
17919 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
17922 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
17924 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
17928 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
17931 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
17932 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
17935 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
17936 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
17944 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
17946 /* enum: De-Emphasis Tap1 Fine */
17948 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
17950 /* enum: De-Emphasis Tap2 Fine (Huntington) */
17952 /* enum: Pre-Emphasis Magnitude (Huntington) */
17954 /* enum: Pre-Emphasis Fine (Huntington) */
17964 /* enum: Pre-cursor Tap (Medford, Medford2) */
17966 /* enum: Post-cursor Tap (Medford, Medford2) */
17970 /* enum: Pre-cursor Tap (Retimer Lineside) */
17972 /* enum: Post-cursor Tap (Retimer Lineside) */
17976 /* enum: Pre-cursor Tap (Retimer Hostside) */
17978 /* enum: Post-cursor Tap (Retimer Hostside) */
18002 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
18003 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
18006 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
18008 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
18011 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
18012 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
18013 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
18016 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4
18021 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4
18026 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4
18029 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4
18032 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4
18040 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
18043 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
18045 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
18055 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
18057 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
18059 /* Port-relative lane to scan eye on */
18060 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
18061 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
18067 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1
18069 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1
18071 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
18072 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
18073 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4
18076 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4
18078 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1
18081 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
18087 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
18090 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
18092 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
18100 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
18111 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1
18113 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1
18115 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
18116 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
18117 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4
18120 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4
18122 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1
18125 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
18127 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
18133 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1
18135 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1
18137 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
18138 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
18146 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1
18148 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1
18150 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
18151 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
18154 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
18157 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
18158 /* C(-1) request */
18160 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
18166 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
18169 /* C(+1) request */
18171 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
18177 /* C(-1) status */
18179 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
18185 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
18186 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
18189 /* C(+1) status */
18191 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
18194 /* C(-1) value */
18196 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
18199 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
18200 /* C(+1) status */
18202 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
18215 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4
18218 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
18219 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_NUM(len) (((len)-4)/4)
18222 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
18241 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
18244 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
18245 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
18254 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
18257 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
18259 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
18263 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
18266 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
18267 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
18270 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
18271 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
18277 /* enum: Attenuation (0-15) */
18279 /* enum: CTLE Boost (0-15) */
18281 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
18283 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
18285 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
18287 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
18289 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
18321 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
18333 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
18334 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
18337 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1
18339 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1
18342 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4
18343 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
18344 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
18347 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
18352 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
18357 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
18359 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
18360 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
18363 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
18366 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
18374 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
18377 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
18379 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
18383 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
18386 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
18387 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
18390 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
18391 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
18401 /* enum: De-emphasis coefficient C(-1) (PIPE) */
18403 /* enum: De-emphasis coefficient C(0) (PIPE) */
18405 /* enum: De-emphasis coefficient C(+1) (PIPE) */
18409 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
18423 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
18425 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
18427 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
18428 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
18434 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
18437 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_LEN 1
18439 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_RSVD_OFST 1
18447 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
18464 * - not used for V3 licensing
18472 #define MC_CMD_LICENSING_IN_LEN 4
18475 #define MC_CMD_LICENSING_IN_OP_LEN 4
18476 /* enum: re-read and apply licenses after a license key partition update; note
18477 * that this operation returns a zero-length response
18487 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
18491 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
18492 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
18495 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
18498 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
18502 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
18507 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
18508 /* licensing subsystem self-test report (for manftest) */
18510 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
18511 /* enum: licensing subsystem self-test failed */
18513 /* enum: licensing subsystem self-test passed */
18520 * - V3 licensing (Medford)
18528 #define MC_CMD_LICENSING_V3_IN_LEN 4
18531 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4
18532 /* enum: re-read and apply licenses after a license key partition update; note
18533 * that this operation returns a zero-length response
18545 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
18549 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
18550 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
18553 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
18556 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
18561 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
18562 /* licensing subsystem self-test report (for manftest) */
18564 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
18565 /* enum: licensing subsystem self-test failed */
18567 /* enum: licensing subsystem self-test passed */
18590 * partition - V3 licensing (Medford)
18604 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
18605 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)
18608 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
18610 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
18611 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
18614 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
18622 * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
18623 * This will fail on a single-core system.
18649 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
18652 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
18655 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
18658 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
18684 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
18687 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
18690 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
18716 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
18720 /* states of these features - bit set for licensed, clear for not licensed */
18724 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
18729 * Perform an action for an individual licensed application - not used for V3
18741 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
18742 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)
18745 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
18747 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
18748 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
18755 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
18764 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
18765 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
18768 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
18777 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
18779 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
18780 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
18789 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
18791 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
18798 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
18800 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
18801 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
18804 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
18812 * Perform validation for an individual licensed application - V3 licensing
18834 * of two 384-bit integers, r and s, in big-endian order. The signature signs a
18835 * SHA-384 digest of a message constructed from the concatenation of the input
18837 * bytes] ... expiry_time[4 bytes] ...
18843 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
18846 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
18857 /* MAC address of v-adaptor associated with the client. If no such v-adapator
18866 * Mask features - V3 licensing (Medford)
18879 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
18882 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
18896 * SF-116124-SW for an overview of how this could be used. The license is
18906 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
18909 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
18927 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
18929 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
18933 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
18935 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
18938 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
18940 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
18946 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
18956 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
18958 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
18966 * configuration. A copy of all traffic delivered to the host (non-promiscuous
18979 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
18982 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
18984 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_LBN 1
18985 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_WIDTH 1
18987 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
18988 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
18991 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
19001 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
19025 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
19028 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
19030 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_LBN 1
19031 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_WIDTH 1
19033 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
19034 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
19037 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
19044 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
19049 * Change configuration related to the parser-dispatcher subsystem.
19060 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
19061 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
19064 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
19065 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
19069 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
19077 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
19078 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
19083 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
19084 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
19094 * Read configuration related to the parser-dispatcher subsystem.
19105 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
19111 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
19112 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
19115 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
19118 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
19119 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
19124 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
19125 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
19149 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
19152 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_WIDTH 1
19154 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
19155 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
19158 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
19168 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
19192 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
19195 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_WIDTH 1
19197 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
19198 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
19201 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
19208 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
19224 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4
19225 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
19226 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4
19227 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_OFST 4
19229 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_WIDTH 1
19234 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4
19235 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4
19236 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4
19238 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4
19240 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4
19259 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4
19261 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4
19262 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4
19263 /* The maximum number of MSI-X vectors the device can provide in total */
19265 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4
19266 /* the number of MSI-X vectors the device will allocate by default to each PF
19269 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4
19270 /* the number of MSI-X vectors the device will allocate by default to each VF
19273 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4
19274 /* the maximum number of MSI-X vectors the device can allocate to any one PF */
19276 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4
19277 /* the maximum number of MSI-X vectors the device can allocate to any one VF */
19279 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4
19300 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
19302 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
19303 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
19306 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
19314 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4
19316 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4
19317 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4
19320 #define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4
19331 #define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4
19350 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4
19353 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 1
19355 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4
19356 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4
19374 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4
19378 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
19379 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4
19381 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4
19383 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4
19386 #define MC_CMD_READ_ATB_OUT_LEN 4
19388 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4
19406 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
19407 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
19408 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
19418 * - before adding code that queries this workaround, remember that there's
19441 * 1,3 = 0x00030001
19444 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
19453 * set to 1.
19455 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
19456 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
19488 * administrator-level operations that are not allowed from the local host once
19490 * SF-117064-DG for background).
19499 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
19502 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
19517 * e.g. VF 1,3 = 0x00030001
19520 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
19528 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
19529 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
19538 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
19540 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
19560 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4
19562 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4
19563 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4
19582 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
19584 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
19585 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
19588 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
19591 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
19592 /* Total number of mismatched bits between pairs in area 1 */
19594 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
19595 /* Total number of unexpectedly clear (set in B but not A) bits in area 1 */
19597 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
19598 /* Total number of unexpectedly clear (set in A but not B) bits in area 1 */
19600 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
19601 /* Checksum of data after logical OR of pairs in area 1 */
19603 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
19606 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
19609 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
19612 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
19615 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
19621 * only effects non-admin functions unless the admin privilege itself is
19633 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
19641 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
19642 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
19643 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4
19646 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4
19653 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
19658 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
19677 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4
19679 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4
19680 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4
19686 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
19687 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1)
19690 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_LEN 1
19709 #define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num))
19710 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_NUM(len) (((len)-8)/1)
19713 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
19715 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4
19716 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4
19719 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_LEN 1
19741 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4
19743 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4
19744 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4
19747 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
19750 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
19751 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_NUM(len) (((len)-4)/1)
19754 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
19761 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
19762 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
19781 #define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num))
19782 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_NUM(len) (((len)-12)/1)
19785 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
19789 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_LEN 1
19790 #define MC_CMD_XPM_WRITE_SECTOR_IN_RESERVED_OFST 1
19793 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4
19794 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4
19799 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4
19802 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_LEN 1
19808 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
19811 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4
19824 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4
19827 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4
19835 * Blank-check XPM memory and report bad locations
19846 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4
19848 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4
19849 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4
19852 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
19855 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
19856 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_NUM(len) (((len)-4)/2)
19857 /* Total number of bad (non-blank) locations */
19859 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
19863 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4
19872 * Blank-check and repair XPM memory
19883 #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4
19885 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4
19886 #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4
19947 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4
19949 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4
19950 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4
19953 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4
19974 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4
19977 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4
19984 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
20008 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
20019 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
20022 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
20023 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
20029 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
20036 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
20037 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
20049 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
20068 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4
20070 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4
20071 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4
20074 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4
20077 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4
20097 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num))
20098 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_NUM(len) (((len)-8)/1)
20101 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
20103 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4
20104 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4
20107 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_LEN 1
20108 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_MINNUM 1
20128 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4
20131 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4
20137 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num))
20138 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_NUM(len) (((len)-12)/1)
20141 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
20143 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4
20144 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4
20147 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4
20150 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_LEN 1
20172 /* Function-relative queue instance */
20174 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
20176 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
20177 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
20180 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
20183 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
20193 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
20195 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
20196 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
20215 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
20221 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
20222 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
20227 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
20233 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
20238 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
20243 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
20251 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
20257 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
20264 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
20283 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
20284 /* Will the common pool be used as TX_vFIFO_ULL (1) */
20285 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
20286 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4
20292 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4
20295 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4
20297 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
20300 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4
20302 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
20309 /* enum: To enable Switch loopback with Rx engine 1 */
20313 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
20316 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4
20334 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4
20336 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
20337 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4
20339 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
20346 /* enum: To enable Switch loopback with Rx engine 1 */
20350 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4
20355 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4
20358 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4
20360 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
20366 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4
20368 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4
20369 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4
20375 * ready to be re-used.
20383 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
20386 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4
20395 * it ready to be re-used.
20403 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
20406 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4
20429 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4
20431 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4
20432 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4
20449 /* The SUC firmware version as four numbers - a.b.c.d */
20451 #define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4
20452 #define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4
20457 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4
20459 * indicates family, memory sizes etc. See SF-116728-SW for further details.
20462 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4
20467 #define MC_CMD_SUC_BOOT_VERSION_IN_LEN 4
20469 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4
20474 #define MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4
20477 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4
20485 * combination of fields, then this command returns a list of prefix-ids,
20488 * supported, returns ENOTSUP. If the firmware can't create any new prefix-ids
20502 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
20505 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_WIDTH 1
20507 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_LBN 1
20508 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_WIDTH 1
20511 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_WIDTH 1
20514 #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_WIDTH 1
20516 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4
20517 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_WIDTH 1
20520 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_WIDTH 1
20523 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_WIDTH 1
20526 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_WIDTH 1
20529 #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_WIDTH 1
20532 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_WIDTH 1
20538 #define MC_CMD_GET_RX_PREFIX_ID_OUT_LEN(num) (4+4*(num))
20539 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_NUM(len) (((len)-4)/4)
20540 /* Number of prefix-ids returned */
20542 #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_LEN 4
20546 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_OFST 4
20547 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_LEN 4
20548 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_MINNUM 1
20555 #define RX_PREFIX_FIELD_INFO_LEN 4
20563 #define RX_PREFIX_FIELD_INFO_WIDTH_BITS_LEN 1
20570 #define RX_PREFIX_FIELD_INFO_TYPE_LEN 1
20587 #define RX_PREFIX_FIXED_RESPONSE_LENMIN 4
20590 #define RX_PREFIX_FIXED_RESPONSE_LEN(num) (4+4*(num))
20591 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_NUM(len) (((len)-4)/4)
20594 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LEN 1
20598 #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_OFST 1
20599 #define RX_PREFIX_FIXED_RESPONSE_FIELD_COUNT_LEN 1
20607 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_OFST 4
20608 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_LEN 4
20628 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_LEN 4
20631 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_LEN 4
20634 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMIN 4
20637 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LEN(num) (4+1*(num))
20638 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_NUM(len) (((len)-4)/1)
20641 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_LEN 1
20644 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESERVED_OFST 1
20647 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_OFST 4
20648 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_LEN 1
20656 * A command to perform various bundle-related operations on insecure cards.
20664 #define MC_CMD_BUNDLE_IN_LEN 4
20665 /* Sub-command code */
20667 #define MC_CMD_BUNDLE_IN_OP_LEN 4
20678 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_LEN 4
20679 /* Sub-command code. Must be OP_COMPONENT_ACCESS_GET. */
20681 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_LEN 4
20686 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_LEN 4
20689 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_LEN 4
20690 /* enum: Component partitions are read-only from the host. */
20692 /* enum: Component partitions can read read-from written-to by the host. */
20697 * read-only on firmware built with bundle support. This command marks these
20703 /* Sub-command code. Must be OP_COMPONENT_ACCESS_SET. */
20705 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_LEN 4
20707 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_OFST 4
20708 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_LEN 4
20726 #define MC_CMD_GET_VPD_IN_LEN 4
20731 #define MC_CMD_GET_VPD_IN_ADDR_LEN 4
20737 #define MC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num))
20738 #define MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1)
20741 #define MC_CMD_GET_VPD_OUT_DATA_LEN 1
20749 * Provide information about the NC-SI stack
20760 #define MC_CMD_GET_NCSI_INFO_IN_OP_LEN 4
20765 /* The NC-SI channel on which the operation is to be performed */
20766 #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_OFST 4
20767 #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_LEN 4
20773 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_LEN 4
20775 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_OFST 4
20776 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_LEN 4
20779 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4
20785 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ENABLE_WIDTH 1
20788 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_NETWORK_TX_WIDTH 1
20790 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4
20791 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_WIDTH 1
20795 /* The number of NC-SI commands received. */
20797 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_LEN 4
20798 /* The number of NC-SI commands dropped. */
20799 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_OFST 4
20800 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_LEN 4
20801 /* The number of invalid NC-SI commands received. */
20803 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_LEN 4
20806 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_LEN 4
20807 /* The number of NC-SI requests received. */
20809 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_LEN 4
20810 /* The number of NC-SI responses sent (includes AENs) */
20812 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_LEN 4
20813 /* The number of NC-SI AENs sent */
20815 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4
20844 #define CLOCK_INFO_SETTABLE_WIDTH 1
20848 #define CLOCK_INFO_FREQUENCY_OFST 4
20850 #define CLOCK_INFO_FREQUENCY_LO_OFST 4
20854 /* Human-readable ASCII name for clock, with NUL termination */
20856 #define CLOCK_INFO_NAME_LEN 1
20879 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28)
20890 …- on TX the send descriptor explicitly specifies encapsulation. These rules are per-VNIC, i.e. onl…
20901 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4
20902 /* Any non-zero bits other than the ones named below or an unsupported
20906 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4
20907 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4
20908 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4
20910 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 1
20911 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4
20912 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 1
20913 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 1
20914 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4
20916 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 1
20917 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4
20919 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 1
20920 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4
20921 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4
20922 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 1
20940 * case of IPv4, the IP should be in the first 4 bytes and all other bytes
20947 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 1
20950 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 1
20953 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 1
20959 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4
20962 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4
20965 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4
20978 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4
20981 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4
20987 * defined in SF-120734-TC with more information in SF-122717-TC.
20989 #define FUNCTION_PERSONALITY_LEN 4
20991 #define FUNCTION_PERSONALITY_ID_LEN 4
20994 /* enum: Function has an EF100-style function control window and VI windows
21006 /* enum: Function is a Xilinx acceleration device - management function */
21008 /* enum: Function is a Xilinx acceleration device - user function */
21024 #define MC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4
21029 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4
21041 * specification ( https://docs.oasis-
21042 * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf )
21047 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
21067 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4
21070 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4
21071 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4
21102 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_LEN 1
21109 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_OFST 1
21110 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_LEN 1
21118 /* Desired instance. This is the function-local index of the associated VI, not
21121 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4
21122 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4
21125 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4
21128 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4
21131 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_WIDTH 1
21151 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4
21163 * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per-
21179 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4
21186 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4
21192 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4
21211 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_LEN 1
21214 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_OFST 1
21215 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_LEN 1
21224 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4
21225 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4
21231 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4
21233 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4
21234 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4
21253 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_LEN 1
21256 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_OFST 1
21257 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_LEN 1
21266 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4
21267 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4
21273 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4
21275 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4
21276 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4
21279 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4
21282 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4
21313 #define PCIE_FUNCTION_INTF_OFST 4
21314 #define PCIE_FUNCTION_INTF_LEN 4
21328 * embedded Application Processor), via EF100 descriptor proxy, memory-to-
21329 * memory and descriptor-to-completion mechanisms. Primary user is Virtio-blk
21330 * subsystem, see SF-122927-TC. This function allocates a new descriptor proxy
21331 * function on the host and assigns a user-defined label. The actual function
21350 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4
21352 * SF-120734-TC with more information in SF-122717-TC. At present, we only
21356 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_LEN 4
21359 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
21369 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_LEN 4
21371 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4
21373 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4
21391 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
21398 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_LEN 4
21406 * Virtio specification v1.1, Sections 5.2.3 and 6 for definition of feature
21407 * bits. See Virtio specification v1.1, Section 5.2.4 (struct
21415 #define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4
21418 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_WIDTH 1
21420 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_LBN 1
21421 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_WIDTH 1
21424 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_WIDTH 1
21426 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_LBN 4
21427 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_WIDTH 1
21430 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_WIDTH 1
21433 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_WIDTH 1
21436 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_WIDTH 1
21439 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_WIDTH 1
21442 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_WIDTH 1
21445 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_WIDTH 1
21448 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_WIDTH 1
21451 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_WIDTH 1
21454 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_WIDTH 1
21457 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_WIDTH 1
21460 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_WIDTH 1
21463 #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_WIDTH 1
21466 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_WIDTH 1
21469 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_WIDTH 1
21472 #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_WIDTH 1
21475 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_WIDTH 1
21478 #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_WIDTH 1
21481 #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_WIDTH 1
21484 /* The capacity of the device (expressed in 512-byte sectors) */
21495 #define VIRTIO_BLK_CONFIG_SIZE_MAX_LEN 4
21502 #define VIRTIO_BLK_CONFIG_SEG_MAX_LEN 4
21505 /* Disk-style geometry - cylinders. Only valid when VIRTIO_BLK_F_GEOMETRY is
21512 /* Disk-style geometry - heads. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
21515 #define VIRTIO_BLK_CONFIG_HEADS_LEN 1
21518 /* Disk-style geometry - sectors. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
21521 #define VIRTIO_BLK_CONFIG_SECTORS_LEN 1
21526 #define VIRTIO_BLK_CONFIG_BLK_SIZE_LEN 4
21529 /* Block topology - number of logical blocks per physical block (log2). Only
21533 #define VIRTIO_BLK_CONFIG_PHYSICAL_BLOCK_EXP_LEN 1
21536 /* Block topology - offset of first aligned logical block. Only valid when
21540 #define VIRTIO_BLK_CONFIG_ALIGNMENT_OFFSET_LEN 1
21543 /* Block topology - suggested minimum I/O size in blocks. Only valid when
21550 /* Block topology - optimal (suggested maximum) I/O size in blocks. Only valid
21554 #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LEN 4
21570 /* Maximum discard sectors size, in 512-byte units. Only valid if
21574 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LEN 4
21580 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LEN 4
21583 /* Discard sector alignment, in 512-byte units. Only valid if
21587 #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LEN 4
21590 /* Maximum write zeroes sectors size, in 512-byte units. Only valid if
21594 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LEN 4
21601 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LEN 4
21608 #define VIRTIO_BLK_CONFIG_WRITE_ZEROES_MAY_UNMAP_LEN 1
21633 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_LEN(num) (20+1*(num))
21634 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_NUM(len) (((len)-20)/1)
21639 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_LEN 4
21641 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_OFST 4
21648 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_LEN 1
21659 * Commit function configuration to non-volatile or volatile store. Once
21675 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_LEN 4
21676 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_OFST 4
21677 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_LEN 4
21678 /* enum: Store into non-volatile (dynamic) config */
21684 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_LEN 4
21688 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_LEN 4
21694 * integer handle, valid until function is deallocated, MC rebooted or power-
21704 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
21714 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LEN(num) (40+1*(num))
21715 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_NUM(len) (((len)-40)/1)
21718 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_LEN 4
21720 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4
21722 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4
21726 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4
21731 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_LEN 4
21740 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_LEN 4
21748 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_LEN 1
21769 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_LEN 4
21772 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_LEN 4
21783 #define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4
21788 #define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4
21793 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
21812 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_LEN 4
21817 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_LEN 4
21820 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMIN 4
21823 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LEN(num) (4+52*(num))
21824 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_NUM(len) (((len)-4)/52)
21826 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_LEN 4
21829 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_WIDTH 1
21831 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_OFST 4
21834 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM 4
21856 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_LEN 4
21860 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_OFST 4
21861 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_LEN 4
21867 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_LEN 4
21869 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_OFST 4
21870 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_LEN 4
21883 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_LEN 4
21888 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_LEN 4
21897 * target. See SF-120734-TC for details on ADDR_SPC_IDs and mem2mem
21909 #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_LEN 4
21936 /* enum: Address space ID for DMA to/from other SmartNIC memory (on-chip, DDR)
21942 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4
21944 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4
21948 #define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4
21951 #define MC_CMD_GET_ADDR_SPC_ID_IN_VI_LEN 4
21954 #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_OFST 4
21955 #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_LEN 4
21965 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4