349 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)  in sh_eth_write()  function
374 	sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,  in sh_eth_modify()
440 	sh_eth_write(ndev, value, RMII_MII);  in sh_eth_select_mii()
487 	sh_eth_write(ndev, EDSR_ENALL, EDSR);  in sh_eth_soft_reset_gether()
495 	sh_eth_write(ndev, 0, TDLAR);  in sh_eth_soft_reset_gether()
496 	sh_eth_write(ndev, 0, TDFAR);  in sh_eth_soft_reset_gether()
497 	sh_eth_write(ndev, 0, TDFXR);  in sh_eth_soft_reset_gether()
498 	sh_eth_write(ndev, 0, TDFFR);  in sh_eth_soft_reset_gether()
499 	sh_eth_write(ndev, 0, RDLAR);  in sh_eth_soft_reset_gether()
500 	sh_eth_write(ndev, 0, RDFAR);  in sh_eth_soft_reset_gether()
501 	sh_eth_write(ndev, 0, RDFXR);  in sh_eth_soft_reset_gether()
502 	sh_eth_write(ndev, 0, RDFFR);  in sh_eth_soft_reset_gether()
506 		sh_eth_write(ndev, 0, CSMR);  in sh_eth_soft_reset_gether()
524 		sh_eth_write(ndev, GECMR_10, GECMR);  in sh_eth_set_rate_gether()
527 		sh_eth_write(ndev, GECMR_100, GECMR);  in sh_eth_set_rate_gether()
530 		sh_eth_write(ndev, GECMR_1000, GECMR);  in sh_eth_set_rate_gether()
847 		sh_eth_write(ndev, 0, RTRATE);  in sh_eth_set_rate_sh7757()
850 		sh_eth_write(ndev, 1, RTRATE);  in sh_eth_set_rate_sh7757()
921 		sh_eth_write(ndev, 0x00000000, GECMR);  in sh_eth_set_rate_giga()
924 		sh_eth_write(ndev, 0x00000010, GECMR);  in sh_eth_set_rate_giga()
927 		sh_eth_write(ndev, 0x00000020, GECMR);  in sh_eth_set_rate_giga()
1139 	sh_eth_write(ndev,  in update_mac_address()
1142 	sh_eth_write(ndev,  in update_mac_address()
1365 			sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);  in sh_eth_ring_format()
1367 				sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);  in sh_eth_ring_format()
1387 			sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);  in sh_eth_ring_format()
1389 				sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);  in sh_eth_ring_format()
1458 		sh_eth_write(ndev, 0x1, RMIIMODE);  in sh_eth_dev_init()
1463 		sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);  in sh_eth_dev_init()
1466 	sh_eth_write(ndev, 0, EESIPR);  in sh_eth_dev_init()
1470 		sh_eth_write(ndev, EDMR_EL, EDMR);  in sh_eth_dev_init()
1473 		sh_eth_write(ndev, 0, EDMR);  in sh_eth_dev_init()
1476 	sh_eth_write(ndev, mdp->cd->fdr_value, FDR);  in sh_eth_dev_init()
1477 	sh_eth_write(ndev, 0, TFTR);  in sh_eth_dev_init()
1480 	sh_eth_write(ndev, RMCR_RNC, RMCR);  in sh_eth_dev_init()
1482 	sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);  in sh_eth_dev_init()
1490 		sh_eth_write(ndev, 0x800, BCULR);  in sh_eth_dev_init()
1492 	sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);  in sh_eth_dev_init()
1495 		sh_eth_write(ndev, 0, TRIMD);  in sh_eth_dev_init()
1498 	sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,  in sh_eth_dev_init()
1503 	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);  in sh_eth_dev_init()
1506 	sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |  in sh_eth_dev_init()
1514 	sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);  in sh_eth_dev_init()
1517 	sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);  in sh_eth_dev_init()
1524 		sh_eth_write(ndev, 1, APR);  in sh_eth_dev_init()
1526 		sh_eth_write(ndev, 1, MPR);  in sh_eth_dev_init()
1528 		sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);  in sh_eth_dev_init()
1531 	sh_eth_write(ndev, EDRRR_R, EDRRR);  in sh_eth_dev_init()
1551 	sh_eth_write(ndev, 0, EDRRR);  in sh_eth_dev_exit()
1564 		sh_eth_write(ndev, 0x1, RMIIMODE);  in sh_eth_dev_exit()
1712 		sh_eth_write(ndev, EDRRR_R, EDRRR);  in sh_eth_rx()
1740 	sh_eth_write(ndev, felic_stat, ECSR);	/* clear int */  in sh_eth_emac_interrupt()
1833 			sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);  in sh_eth_error()
1867 		sh_eth_write(ndev, 0, EESIPR);  in sh_eth_interrupt()
1874 			sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,  in sh_eth_interrupt()
1887 		sh_eth_write(ndev, intr_status & cd->tx_check, EESR);  in sh_eth_interrupt()
1899 		sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);  in sh_eth_interrupt()
1923 		sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);  in sh_eth_poll()
1933 		sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);  in sh_eth_poll()
2333 		sh_eth_write(ndev, 0x0000, EESIPR);  in sh_eth_set_ringparam()
2540 		sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);  in sh_eth_start_xmit()
2557 		sh_eth_write(ndev, 0, reg);  in sh_eth_update_stat()
2602 	sh_eth_write(ndev, 0x0000, EESIPR);  in sh_eth_close()
2907 	sh_eth_write(ndev, ecmr_bits, ECMR);  in sh_eth_set_rx_mode()
3360 		sh_eth_write(ndev, 0x1, RMIIMODE);  in sh_eth_drv_probe()
3425 	sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);  in sh_eth_wol_setup()