Lines Matching +full:0 +full:x349
65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
74 #define OCP_STD_PHY_BASE 0xa400
155 { PCI_VDEVICE(REALTEK, 0x2502) },
156 { PCI_VDEVICE(REALTEK, 0x2600) },
157 { PCI_VDEVICE(REALTEK, 0x8129) },
158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
159 { PCI_VDEVICE(REALTEK, 0x8161) },
160 { PCI_VDEVICE(REALTEK, 0x8162) },
161 { PCI_VDEVICE(REALTEK, 0x8167) },
162 { PCI_VDEVICE(REALTEK, 0x8168) },
163 { PCI_VDEVICE(NCUBE, 0x8168) },
164 { PCI_VDEVICE(REALTEK, 0x8169) },
165 { PCI_VENDOR_ID_DLINK, 0x4300,
166 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
167 { PCI_VDEVICE(DLINK, 0x4300) },
168 { PCI_VDEVICE(DLINK, 0x4302) },
169 { PCI_VDEVICE(AT, 0xc107) },
170 { PCI_VDEVICE(USR, 0x0116) },
171 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
172 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
173 { PCI_VDEVICE(REALTEK, 0x8125) },
174 { PCI_VDEVICE(REALTEK, 0x3000) },
181 MAC0 = 0, /* Ethernet hardware address. */
184 CounterAddrLow = 0x10,
185 CounterAddrHigh = 0x14,
186 TxDescStartAddrLow = 0x20,
187 TxDescStartAddrHigh = 0x24,
188 TxHDescStartAddrLow = 0x28,
189 TxHDescStartAddrHigh = 0x2c,
190 FLASH = 0x30,
191 ERSR = 0x36,
192 ChipCmd = 0x37,
193 TxPoll = 0x38,
194 IntrMask = 0x3c,
195 IntrStatus = 0x3e,
197 TxConfig = 0x40,
201 RxConfig = 0x44,
212 Cfg9346 = 0x50,
213 Config0 = 0x51,
214 Config1 = 0x52,
215 Config2 = 0x53,
218 Config3 = 0x54,
219 Config4 = 0x55,
220 Config5 = 0x56,
221 PHYAR = 0x60,
222 PHYstatus = 0x6c,
223 RxMaxSize = 0xda,
224 CPlusCmd = 0xe0,
225 IntrMitigate = 0xe2,
230 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
232 #define RTL_COALESCE_T_MAX 0x0fU
235 RxDescAddrLow = 0xe4,
236 RxDescAddrHigh = 0xe8,
237 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
239 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
241 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
244 #define EarlySize 0x27
246 FuncEvent = 0xf0,
247 FuncEventMask = 0xf4,
248 FuncPresetState = 0xf8,
249 IBCR0 = 0xf8,
250 IBCR2 = 0xf9,
251 IBIMR0 = 0xfa,
252 IBISR0 = 0xfb,
253 FuncForceEvent = 0xfc,
257 CSIDR = 0x64,
258 CSIAR = 0x68,
259 #define CSIAR_FLAG 0x80000000
260 #define CSIAR_WRITE_CMD 0x80000000
261 #define CSIAR_BYTE_ENABLE 0x0000f000
262 #define CSIAR_ADDR_MASK 0x00000fff
263 PMCH = 0x6f,
267 EPHYAR = 0x80,
268 #define EPHYAR_FLAG 0x80000000
269 #define EPHYAR_WRITE_CMD 0x80000000
270 #define EPHYAR_REG_MASK 0x1f
272 #define EPHYAR_DATA_MASK 0xffff
273 DLLPR = 0xd0,
276 DBG_REG = 0xd1,
279 TWSI = 0xd2,
280 MCU = 0xd3,
288 EFUSEAR = 0xdc,
289 #define EFUSEAR_FLAG 0x80000000
290 #define EFUSEAR_WRITE_CMD 0x80000000
291 #define EFUSEAR_READ_CMD 0x00000000
292 #define EFUSEAR_REG_MASK 0x03ff
294 #define EFUSEAR_DATA_MASK 0xff
295 MISC_1 = 0xf2,
300 LED_FREQ = 0x1a,
301 EEE_LED = 0x1b,
302 ERIDR = 0x70,
303 ERIAR = 0x74,
304 #define ERIAR_FLAG 0x80000000
305 #define ERIAR_WRITE_CMD 0x80000000
306 #define ERIAR_READ_CMD 0x00000000
309 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
310 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
311 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
312 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
314 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
315 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
316 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
317 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
318 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
319 EPHY_RXER_NUM = 0x7c,
320 OCPDR = 0xb0, /* OCP GPHY access */
321 #define OCPDR_WRITE_CMD 0x80000000
322 #define OCPDR_READ_CMD 0x00000000
323 #define OCPDR_REG_MASK 0x7f
325 #define OCPDR_DATA_MASK 0xffff
326 OCPAR = 0xb4,
327 #define OCPAR_FLAG 0x80000000
328 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
329 #define OCPAR_GPHY_READ_CMD 0x0000f060
330 GPHY_OCP = 0xb8,
331 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
332 MISC = 0xf0, /* 8168e only. */
341 IntrMask_8125 = 0x38,
342 IntrStatus_8125 = 0x3c,
343 TxPoll_8125 = 0x90,
344 MAC0_BKP = 0x19e0,
345 EEE_TXIDLE_TIMER_8125 = 0x6048,
356 SYSErr = 0x8000,
357 PCSTimeout = 0x4000,
358 SWInt = 0x0100,
359 TxDescUnavail = 0x0080,
360 RxFIFOOver = 0x0040,
361 LinkChg = 0x0020,
362 RxOverflow = 0x0010,
363 TxErr = 0x0008,
364 TxOK = 0x0004,
365 RxErr = 0x0002,
366 RxOK = 0x0001,
375 StopReq = 0x80,
376 CmdReset = 0x10,
377 CmdRxEnb = 0x08,
378 CmdTxEnb = 0x04,
379 RxBufEmpty = 0x01,
382 HPQ = 0x80, /* Poll cmd on the high prio queue */
383 NPQ = 0x40, /* Poll cmd on the low prio queue */
384 FSWInt = 0x01, /* Forced software interrupt */
387 Cfg9346_Lock = 0x00,
388 Cfg9346_Unlock = 0xc0,
391 AcceptErr = 0x20,
392 AcceptRunt = 0x10,
393 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
394 AcceptBroadcast = 0x08,
395 AcceptMulticast = 0x04,
396 AcceptMyPhys = 0x02,
397 AcceptAllPhys = 0x01,
398 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
399 #define RX_CONFIG_ACCEPT_MASK 0x3f
403 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
412 PMEnable = (1 << 0), /* Power Management Enable */
417 PCI_Clock_66MHz = 0x01,
418 PCI_Clock_33MHz = 0x00,
425 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
436 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
437 ASPM_en = (1 << 0), /* ASPM enable */
450 Mac_dbgo_sel = 0x001c, // 8168
455 #define INTT_MASK GENMASK(1, 0)
459 TBI_Enable = 0x80,
460 TxFlowCtrl = 0x40,
461 RxFlowCtrl = 0x20,
462 _1000bpsF = 0x10,
463 _100bps = 0x08,
464 _10bps = 0x04,
465 LinkStatus = 0x02,
466 FullDup = 0x01,
469 CounterReset = 0x1,
472 CounterDump = 0x8,
490 #define TD_MSS_MAX 0x07ffu /* MSS value */
511 #define GTTCPHO_MAX 0x7f
515 #define TCPHO_MAX 0x3ff
526 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
589 RTL_FLAG_TASK_ENABLED = 0,
713 for (i = 0; i < ETH_ALEN; i++) in rtl_read_mac_from_reg()
727 for (i = 0; i < n; i++) { in rtl_loop_wait()
769 *cmd |= 0xf70 << 18; in r8168fp_adjust_ocp_cmd()
782 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) in _rtl_eri_write()
806 RTL_R32(tp, ERIDR) : ~0; in _rtl_eri_read()
823 rtl_w0w1_eri(tp, addr, p, 0); in rtl_eri_set_bits()
828 rtl_w0w1_eri(tp, addr, 0, m); in rtl_eri_clear_bits()
833 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); in rtl_ocp_reg_failure()
854 return 0; in r8168_phy_ocp_read()
859 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; in r8168_phy_ocp_read()
873 return 0; in r8168_mac_ocp_read()
898 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
900 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
909 if (reg == 0x1f) { in r8168g_mdio_write()
915 reg -= 0x10; in r8168g_mdio_write()
925 if (reg == 0x1f) in r8168g_mdio_read()
926 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; in r8168g_mdio_read()
929 reg -= 0x10; in r8168g_mdio_read()
936 if (reg == 0x1f) { in mac_mcu_write()
951 return RTL_R32(tp, PHYAR) & 0x80000000; in DECLARE_RTL_COND()
956 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
970 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
973 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; in r8169_mdio_read()
993 RTL_W32(tp, EPHY_RXER_NUM, 0); in r8168dp_1_mdio_access()
1010 RTL_W32(tp, EPHY_RXER_NUM, 0); in r8168dp_1_mdio_read()
1016 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1020 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
1025 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1043 return 0xc912; in r8168dp_2_mdio_read()
1108 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; in rtl_ephy_read()
1113 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1115 RTL_R32(tp, OCPDR) : ~0; in r8168dp_ocp_read()
1127 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1134 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, in r8168ep_ocp_write()
1140 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); in r8168dp_oob_notify()
1142 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); in r8168dp_oob_notify()
1145 #define OOB_CMD_RESET 0x00
1146 #define OOB_CMD_DRIVER_START 0x05
1147 #define OOB_CMD_DRIVER_STOP 0x06
1151 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; in rtl8168_get_ocp_reg()
1160 return r8168dp_ocp_read(tp, reg) & 0x00000800; in DECLARE_RTL_COND()
1165 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; in DECLARE_RTL_COND()
1170 return RTL_R8(tp, IBISR0) & 0x20; in DECLARE_RTL_COND()
1175 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); in rtl8168ep_stop_cmac()
1177 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); in rtl8168ep_stop_cmac()
1178 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); in rtl8168ep_stop_cmac()
1189 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); in rtl8168ep_driver_start()
1190 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_start()
1211 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); in rtl8168ep_driver_stop()
1212 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_stop()
1233 return r8168ep_ocp_read(tp, 0x128) & BIT(0); in r8168ep_check_dash()
1269 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1270 rtl_eri_set_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1283 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; in rtl8168d_efuse_read()
1305 RTL_W32(tp, IntrMask_8125, 0); in rtl_irq_disable()
1307 RTL_W16(tp, IntrMask, 0); in rtl_irq_disable()
1321 rtl_ack_events(tp, 0xffffffff); in rtl8169_irq_mask_and_ack()
1332 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1333 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1335 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1336 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1338 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1339 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1345 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1346 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1348 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1349 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1353 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); in rtl_link_chg_patch()
1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); in rtl_link_chg_patch()
1356 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_link_chg_patch()
1393 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1395 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1399 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); in __rtl8169_set_wol()
1401 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); in __rtl8169_set_wol()
1404 for (i = 0; i < tmp; i++) { in __rtl8169_set_wol()
1434 tp->dev->wol_enabled = wolopts ? 1 : 0; in __rtl8169_set_wol()
1447 return 0; in rtl8169_set_wol()
1526 return 0; in rtl8169_set_features()
1532 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; in rtl8169_tx_vlan_tag()
1540 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); in rtl8169_rx_vlan_tag()
1551 for (i = 0; i < R8169_REGS_SIZE; i += 4) in rtl8169_get_regs()
1604 * is disabled. If 0xff chip may be in a PCI power-save state. in rtl8169_update_counters()
1606 if (val & CmdRxEnb && val != 0xff) in rtl8169_update_counters()
1654 data[0] = le64_to_cpu(counters->tx_packets); in rtl8169_get_ethtool_stats()
1681 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1689 * (0xe0) bit 1 and bit 0.
1692 * bit[1:0] \ speed 1000M 100M 10M
1693 * 0 0 320ns 2.56us 40.96us
1694 * 0 1 2.56us 20.48us 327.7us
1695 * 1 0 5.12us 40.96us 655.4us
1699 * bit[1:0] \ speed 1000M 100M 10M
1700 * 0 0 5us 2.56us 40.96us
1701 * 0 1 40us 20.48us 327.7us
1702 * 1 0 80us 40.96us 655.4us
1706 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1719 { 0 },
1726 { 0 },
1766 memset(ec, 0, sizeof(*ec)); in rtl_get_coalesce()
1768 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ in rtl_get_coalesce()
1781 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ in rtl_get_coalesce()
1790 return 0; in rtl_get_coalesce()
1793 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1804 for (i = 0; i < 4; i++) { in rtl_coalesce_choose_scale()
1823 u16 w = 0, cp01 = 0; in rtl_set_coalesce()
1834 if (scale < 0) in rtl_set_coalesce()
1838 * not only when usecs=0 because of e.g. the following scenario: in rtl_set_coalesce()
1840 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) in rtl_set_coalesce()
1841 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 in rtl_set_coalesce()
1845 * if we want to ignore rx_frames then it has to be set to 0. in rtl_set_coalesce()
1848 rx_fr = 0; in rtl_set_coalesce()
1850 tx_fr = 0; in rtl_set_coalesce()
1880 return 0; in rtl_set_coalesce()
1927 data->tx_pause = tx_pause ? 1 : 0; in rtl8169_get_pauseparam()
1928 data->rx_pause = rx_pause ? 1 : 0; in rtl8169_get_pauseparam()
1941 return 0; in rtl8169_set_pauseparam()
1975 if (tp->eee_adv >= 0) in rtl_enable_eee()
1980 if (adv >= 0) in rtl_enable_eee()
1991 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be in rtl8169_get_mac_version()
1995 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec in rtl8169_get_mac_version()
2003 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, in rtl8169_get_mac_version()
2006 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, in rtl8169_get_mac_version()
2007 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, in rtl8169_get_mac_version()
2010 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, in rtl8169_get_mac_version()
2011 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, in rtl8169_get_mac_version()
2014 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, in rtl8169_get_mac_version()
2015 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, in rtl8169_get_mac_version()
2016 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, in rtl8169_get_mac_version()
2019 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, in rtl8169_get_mac_version()
2020 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, in rtl8169_get_mac_version()
2023 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, in rtl8169_get_mac_version()
2024 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, in rtl8169_get_mac_version()
2025 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, in rtl8169_get_mac_version()
2026 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, in rtl8169_get_mac_version()
2029 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, in rtl8169_get_mac_version()
2030 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, in rtl8169_get_mac_version()
2031 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, in rtl8169_get_mac_version()
2034 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, in rtl8169_get_mac_version()
2035 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, in rtl8169_get_mac_version()
2036 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, in rtl8169_get_mac_version()
2039 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, in rtl8169_get_mac_version()
2040 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, in rtl8169_get_mac_version()
2046 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, in rtl8169_get_mac_version()
2048 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, in rtl8169_get_mac_version()
2049 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, in rtl8169_get_mac_version()
2052 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, in rtl8169_get_mac_version()
2053 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, in rtl8169_get_mac_version()
2054 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, in rtl8169_get_mac_version()
2055 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, in rtl8169_get_mac_version()
2056 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, in rtl8169_get_mac_version()
2057 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, in rtl8169_get_mac_version()
2058 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, in rtl8169_get_mac_version()
2061 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, in rtl8169_get_mac_version()
2062 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, in rtl8169_get_mac_version()
2063 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, in rtl8169_get_mac_version()
2066 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, in rtl8169_get_mac_version()
2067 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, in rtl8169_get_mac_version()
2068 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, in rtl8169_get_mac_version()
2069 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, in rtl8169_get_mac_version()
2070 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
2071 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
2072 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
2073 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
2074 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, in rtl8169_get_mac_version()
2075 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, in rtl8169_get_mac_version()
2076 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, in rtl8169_get_mac_version()
2077 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, in rtl8169_get_mac_version()
2078 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
2079 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
2080 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, in rtl8169_get_mac_version()
2084 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, in rtl8169_get_mac_version()
2085 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, in rtl8169_get_mac_version()
2089 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, in rtl8169_get_mac_version()
2090 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, in rtl8169_get_mac_version()
2091 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, in rtl8169_get_mac_version()
2092 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, in rtl8169_get_mac_version()
2093 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, in rtl8169_get_mac_version()
2096 { 0x000, 0x000, RTL_GIGA_MAC_NONE } in rtl8169_get_mac_version()
2147 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); in rtl8168_config_eee_mac()
2149 rtl_eri_set_bits(tp, 0x1b0, 0x0003); in rtl8168_config_eee_mac()
2154 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125a_config_eee_mac()
2155 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); in rtl8125a_config_eee_mac()
2160 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); in rtl8125_set_eee_txidle_timer()
2166 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125b_config_eee_mac()
2171 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); in rtl_rar_exgmac_set()
2172 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); in rtl_rar_exgmac_set()
2173 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); in rtl_rar_exgmac_set()
2174 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); in rtl_rar_exgmac_set()
2181 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); in rtl8168h_2_get_adc_bias_ioffset()
2182 data1 = r8168_mac_ocp_read(tp, 0xdd02); in rtl8168h_2_get_adc_bias_ioffset()
2183 data2 = r8168_mac_ocp_read(tp, 0xdd00); in rtl8168h_2_get_adc_bias_ioffset()
2185 ioffset = (data2 >> 1) & 0x7ff8; in rtl8168h_2_get_adc_bias_ioffset()
2186 ioffset |= data2 & 0x0007; in rtl8168h_2_get_adc_bias_ioffset()
2204 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); in rtl8169_init_phy()
2205 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); in rtl8169_init_phy()
2206 /* set undocumented MAC Reg C+CR Offset 0x82h */ in rtl8169_init_phy()
2207 RTL_W8(tp, 0x82, 0x01); in rtl8169_init_phy()
2212 tp->pci_dev->subsystem_device == 0xe000) in rtl8169_init_phy()
2213 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); in rtl8169_init_phy()
2251 return 0; in rtl_set_mac_address()
2268 rtl_ephy_write(tp, 0x19, 0xff64); in rtl_prepare_power_down()
2302 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; in rtl8169_init_ring_indexes()
2329 RTL_W8(tp, MaxTxPacketSize, 0x24); in r8168e_hw_jumbo_enable()
2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); in r8168e_hw_jumbo_enable()
2336 RTL_W8(tp, MaxTxPacketSize, 0x3f); in r8168e_hw_jumbo_disable()
2338 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); in r8168e_hw_jumbo_disable()
2343 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); in r8168b_1_hw_jumbo_enable()
2348 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); in r8168b_1_hw_jumbo_disable()
2465 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; in DECLARE_RTL_COND()
2530 val = 0x000fff00; in rtl8169_set_magic_reg()
2532 val = 0x00ffff00; in rtl8169_set_magic_reg()
2537 val |= 0xff; in rtl8169_set_magic_reg()
2539 RTL_W32(tp, 0x7c, val); in rtl8169_set_magic_reg()
2546 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; in rtl_set_rx_mode()
2561 mc_filter[1] = mc_filter[0] = 0; in rtl_set_rx_mode()
2568 tmp = mc_filter[0]; in rtl_set_rx_mode()
2569 mc_filter[0] = swab32(mc_filter[1]); in rtl_set_rx_mode()
2575 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
2605 RTL_R32(tp, CSIDR) : ~0; in rtl_csi_read()
2613 /* According to Realtek the value at config space address 0x070f in rtl_set_aspm_entry_latency()
2616 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) in rtl_set_aspm_entry_latency()
2617 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us in rtl_set_aspm_entry_latency()
2619 if (pdev->cfg_size > 0x070f && in rtl_set_aspm_entry_latency()
2620 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) in rtl_set_aspm_entry_latency()
2625 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; in rtl_set_aspm_entry_latency()
2626 rtl_csi_write(tp, 0x070c, csi | val << 24); in rtl_set_aspm_entry_latency()
2632 rtl_set_aspm_entry_latency(tp, 0x27); in rtl_set_def_aspm_entry_latency()
2646 while (len-- > 0) { in __rtl_ephy_init()
2685 rtl_eri_set_bits(tp, 0xd4, 0x1f00); in rtl_enable_exit_l1()
2688 rtl_eri_set_bits(tp, 0xd4, 0x0c00); in rtl_enable_exit_l1()
2691 rtl_eri_set_bits(tp, 0xd4, 0x1f80); in rtl_enable_exit_l1()
2694 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); in rtl_enable_exit_l1()
2721 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); in rtl_set_fifo_size()
2722 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); in rtl_set_fifo_size()
2729 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); in rtl8168g_set_pause_thresholds()
2730 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); in rtl8168g_set_pause_thresholds()
2750 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168cp_1()
2751 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168cp_1()
2752 { 0x03, 0, 0x0042 }, in rtl_hw_start_8168cp_1()
2753 { 0x06, 0x0080, 0x0000 }, in rtl_hw_start_8168cp_1()
2754 { 0x07, 0, 0x2000 } in rtl_hw_start_8168cp_1()
2778 RTL_W8(tp, DBG_REG, 0x20); in rtl_hw_start_8168cp_3()
2784 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168c_1()
2785 { 0x03, 0, 0x0002 }, in rtl_hw_start_8168c_1()
2786 { 0x06, 0x0080, 0x0000 } in rtl_hw_start_8168c_1()
2791 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); in rtl_hw_start_8168c_1()
2801 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168c_2()
2802 { 0x03, 0x0400, 0x0020 } in rtl_hw_start_8168c_2()
2829 { 0x0b, 0x0000, 0x0048 }, in rtl_hw_start_8168d_4()
2830 { 0x19, 0x0020, 0x0050 }, in rtl_hw_start_8168d_4()
2831 { 0x0c, 0x0100, 0x0020 }, in rtl_hw_start_8168d_4()
2832 { 0x10, 0x0004, 0x0000 }, in rtl_hw_start_8168d_4()
2845 { 0x00, 0x0200, 0x0100 }, in rtl_hw_start_8168e_1()
2846 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_1()
2847 { 0x06, 0x0002, 0x0001 }, in rtl_hw_start_8168e_1()
2848 { 0x06, 0x0000, 0x0030 }, in rtl_hw_start_8168e_1()
2849 { 0x07, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
2850 { 0x00, 0x0000, 0x0020 }, in rtl_hw_start_8168e_1()
2851 { 0x03, 0x5800, 0x2000 }, in rtl_hw_start_8168e_1()
2852 { 0x03, 0x0000, 0x0001 }, in rtl_hw_start_8168e_1()
2853 { 0x01, 0x0800, 0x1000 }, in rtl_hw_start_8168e_1()
2854 { 0x07, 0x0000, 0x4000 }, in rtl_hw_start_8168e_1()
2855 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
2856 { 0x19, 0xffff, 0xfe6c }, in rtl_hw_start_8168e_1()
2857 { 0x0a, 0x0000, 0x0040 } in rtl_hw_start_8168e_1()
2876 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168e_2()
2877 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168e_2()
2878 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_2()
2879 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168e_2()
2886 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168e_2()
2887 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168e_2()
2888 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168e_2()
2889 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); in rtl_hw_start_8168e_2()
2891 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168e_2()
2892 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168e_2()
2893 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); in rtl_hw_start_8168e_2()
2912 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168f()
2913 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168f()
2914 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168f()
2916 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168f()
2917 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); in rtl_hw_start_8168f()
2918 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168f()
2919 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); in rtl_hw_start_8168f()
2934 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8168f_1()
2935 { 0x08, 0x0001, 0x0002 }, in rtl_hw_start_8168f_1()
2936 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168f_1()
2937 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168f_1()
2938 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8168f_1()
2939 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168f_1()
2950 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8411()
2951 { 0x0f, 0xffff, 0x5200 }, in rtl_hw_start_8411()
2952 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8411()
2953 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8411()
2954 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8411()
2965 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168g()
2966 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168g()
2971 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); in rtl_hw_start_8168g()
2975 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
2976 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
2980 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168g()
2981 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168g()
2989 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_1()
2990 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_1()
2991 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8168g_1()
2992 { 0x19, 0x8000, 0x0000 } in rtl_hw_start_8168g_1()
3006 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_2()
3007 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_2()
3008 { 0x19, 0xffff, 0x7c00 }, in rtl_hw_start_8168g_2()
3009 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8168g_2()
3010 { 0x0d, 0xffff, 0x1666 }, in rtl_hw_start_8168g_2()
3011 { 0x00, 0xffff, 0x10a3 }, in rtl_hw_start_8168g_2()
3012 { 0x06, 0xffff, 0xf050 }, in rtl_hw_start_8168g_2()
3013 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8168g_2()
3014 { 0x1d, 0x4000, 0x0000 }, in rtl_hw_start_8168g_2()
3027 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8411_2()
3028 { 0x0c, 0x37d0, 0x0820 }, in rtl_hw_start_8411_2()
3029 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8411_2()
3030 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8411_2()
3031 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8411_2()
3032 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8411_2()
3033 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8411_2()
3034 { 0x06, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3035 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3036 { 0x1d, 0x0000, 0x4000 }, in rtl_hw_start_8411_2()
3048 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); in rtl_hw_start_8411_2()
3049 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); in rtl_hw_start_8411_2()
3050 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); in rtl_hw_start_8411_2()
3051 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); in rtl_hw_start_8411_2()
3052 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); in rtl_hw_start_8411_2()
3053 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); in rtl_hw_start_8411_2()
3054 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); in rtl_hw_start_8411_2()
3055 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); in rtl_hw_start_8411_2()
3057 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); in rtl_hw_start_8411_2()
3059 r8168_mac_ocp_write(tp, 0xF800, 0xE008); in rtl_hw_start_8411_2()
3060 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); in rtl_hw_start_8411_2()
3061 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); in rtl_hw_start_8411_2()
3062 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); in rtl_hw_start_8411_2()
3063 r8168_mac_ocp_write(tp, 0xF808, 0xE027); in rtl_hw_start_8411_2()
3064 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); in rtl_hw_start_8411_2()
3065 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); in rtl_hw_start_8411_2()
3066 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); in rtl_hw_start_8411_2()
3067 r8168_mac_ocp_write(tp, 0xF810, 0xC602); in rtl_hw_start_8411_2()
3068 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); in rtl_hw_start_8411_2()
3069 r8168_mac_ocp_write(tp, 0xF814, 0x0000); in rtl_hw_start_8411_2()
3070 r8168_mac_ocp_write(tp, 0xF816, 0xC502); in rtl_hw_start_8411_2()
3071 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); in rtl_hw_start_8411_2()
3072 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); in rtl_hw_start_8411_2()
3073 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); in rtl_hw_start_8411_2()
3074 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); in rtl_hw_start_8411_2()
3075 r8168_mac_ocp_write(tp, 0xF820, 0x080A); in rtl_hw_start_8411_2()
3076 r8168_mac_ocp_write(tp, 0xF822, 0x6420); in rtl_hw_start_8411_2()
3077 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); in rtl_hw_start_8411_2()
3078 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); in rtl_hw_start_8411_2()
3079 r8168_mac_ocp_write(tp, 0xF828, 0xC516); in rtl_hw_start_8411_2()
3080 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); in rtl_hw_start_8411_2()
3081 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); in rtl_hw_start_8411_2()
3082 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); in rtl_hw_start_8411_2()
3083 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); in rtl_hw_start_8411_2()
3084 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); in rtl_hw_start_8411_2()
3085 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); in rtl_hw_start_8411_2()
3086 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); in rtl_hw_start_8411_2()
3087 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); in rtl_hw_start_8411_2()
3088 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); in rtl_hw_start_8411_2()
3089 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); in rtl_hw_start_8411_2()
3090 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); in rtl_hw_start_8411_2()
3091 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); in rtl_hw_start_8411_2()
3092 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); in rtl_hw_start_8411_2()
3093 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); in rtl_hw_start_8411_2()
3094 r8168_mac_ocp_write(tp, 0xF846, 0xC404); in rtl_hw_start_8411_2()
3095 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); in rtl_hw_start_8411_2()
3096 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); in rtl_hw_start_8411_2()
3097 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); in rtl_hw_start_8411_2()
3098 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); in rtl_hw_start_8411_2()
3099 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); in rtl_hw_start_8411_2()
3100 r8168_mac_ocp_write(tp, 0xF852, 0xE434); in rtl_hw_start_8411_2()
3101 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); in rtl_hw_start_8411_2()
3102 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); in rtl_hw_start_8411_2()
3103 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); in rtl_hw_start_8411_2()
3104 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); in rtl_hw_start_8411_2()
3105 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); in rtl_hw_start_8411_2()
3106 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); in rtl_hw_start_8411_2()
3107 r8168_mac_ocp_write(tp, 0xF860, 0xF007); in rtl_hw_start_8411_2()
3108 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); in rtl_hw_start_8411_2()
3109 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); in rtl_hw_start_8411_2()
3110 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); in rtl_hw_start_8411_2()
3111 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); in rtl_hw_start_8411_2()
3112 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); in rtl_hw_start_8411_2()
3113 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); in rtl_hw_start_8411_2()
3114 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); in rtl_hw_start_8411_2()
3115 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); in rtl_hw_start_8411_2()
3116 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); in rtl_hw_start_8411_2()
3117 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); in rtl_hw_start_8411_2()
3118 r8168_mac_ocp_write(tp, 0xF876, 0xC516); in rtl_hw_start_8411_2()
3119 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); in rtl_hw_start_8411_2()
3120 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); in rtl_hw_start_8411_2()
3121 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); in rtl_hw_start_8411_2()
3122 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); in rtl_hw_start_8411_2()
3123 r8168_mac_ocp_write(tp, 0xF880, 0xC512); in rtl_hw_start_8411_2()
3124 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); in rtl_hw_start_8411_2()
3125 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); in rtl_hw_start_8411_2()
3126 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); in rtl_hw_start_8411_2()
3127 r8168_mac_ocp_write(tp, 0xF888, 0x483F); in rtl_hw_start_8411_2()
3128 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); in rtl_hw_start_8411_2()
3129 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); in rtl_hw_start_8411_2()
3130 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); in rtl_hw_start_8411_2()
3131 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); in rtl_hw_start_8411_2()
3132 r8168_mac_ocp_write(tp, 0xF892, 0xC505); in rtl_hw_start_8411_2()
3133 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); in rtl_hw_start_8411_2()
3134 r8168_mac_ocp_write(tp, 0xF896, 0xC502); in rtl_hw_start_8411_2()
3135 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); in rtl_hw_start_8411_2()
3136 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); in rtl_hw_start_8411_2()
3137 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); in rtl_hw_start_8411_2()
3138 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); in rtl_hw_start_8411_2()
3139 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); in rtl_hw_start_8411_2()
3140 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); in rtl_hw_start_8411_2()
3141 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); in rtl_hw_start_8411_2()
3142 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); in rtl_hw_start_8411_2()
3143 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); in rtl_hw_start_8411_2()
3144 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); in rtl_hw_start_8411_2()
3145 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); in rtl_hw_start_8411_2()
3146 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); in rtl_hw_start_8411_2()
3147 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); in rtl_hw_start_8411_2()
3148 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); in rtl_hw_start_8411_2()
3149 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); in rtl_hw_start_8411_2()
3150 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); in rtl_hw_start_8411_2()
3151 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); in rtl_hw_start_8411_2()
3152 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); in rtl_hw_start_8411_2()
3153 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); in rtl_hw_start_8411_2()
3154 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); in rtl_hw_start_8411_2()
3155 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); in rtl_hw_start_8411_2()
3156 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); in rtl_hw_start_8411_2()
3157 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); in rtl_hw_start_8411_2()
3158 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); in rtl_hw_start_8411_2()
3159 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); in rtl_hw_start_8411_2()
3160 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); in rtl_hw_start_8411_2()
3161 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); in rtl_hw_start_8411_2()
3162 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); in rtl_hw_start_8411_2()
3163 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); in rtl_hw_start_8411_2()
3164 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); in rtl_hw_start_8411_2()
3165 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); in rtl_hw_start_8411_2()
3166 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); in rtl_hw_start_8411_2()
3167 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); in rtl_hw_start_8411_2()
3168 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); in rtl_hw_start_8411_2()
3169 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); in rtl_hw_start_8411_2()
3171 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); in rtl_hw_start_8411_2()
3173 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); in rtl_hw_start_8411_2()
3174 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); in rtl_hw_start_8411_2()
3175 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); in rtl_hw_start_8411_2()
3176 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); in rtl_hw_start_8411_2()
3177 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); in rtl_hw_start_8411_2()
3178 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); in rtl_hw_start_8411_2()
3179 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); in rtl_hw_start_8411_2()
3187 { 0x1e, 0x0800, 0x0001 }, in rtl_hw_start_8168h_1()
3188 { 0x1d, 0x0000, 0x0800 }, in rtl_hw_start_8168h_1()
3189 { 0x05, 0xffff, 0x2089 }, in rtl_hw_start_8168h_1()
3190 { 0x06, 0xffff, 0x5881 }, in rtl_hw_start_8168h_1()
3191 { 0x04, 0xffff, 0x854a }, in rtl_hw_start_8168h_1()
3192 { 0x01, 0xffff, 0x068b } in rtl_hw_start_8168h_1()
3200 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168h_1()
3201 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168h_1()
3207 rtl_eri_set_bits(tp, 0xdc, 0x001c); in rtl_hw_start_8168h_1()
3209 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168h_1()
3213 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3214 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3223 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168h_1()
3227 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8168h_1()
3228 if (rg_saw_cnt > 0) { in rtl_hw_start_8168h_1()
3232 sw_cnt_1ms_ini &= 0x0fff; in rtl_hw_start_8168h_1()
3233 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8168h_1()
3236 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8168h_1()
3237 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); in rtl_hw_start_8168h_1()
3238 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); in rtl_hw_start_8168h_1()
3239 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8168h_1()
3241 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8168h_1()
3242 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8168h_1()
3243 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8168h_1()
3244 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8168h_1()
3253 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168ep()
3254 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8168ep()
3260 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168ep()
3264 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3265 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3269 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168ep()
3279 { 0x00, 0xffff, 0x10ab }, in rtl_hw_start_8168ep_1()
3280 { 0x06, 0xffff, 0xf030 }, in rtl_hw_start_8168ep_1()
3281 { 0x08, 0xffff, 0x2006 }, in rtl_hw_start_8168ep_1()
3282 { 0x0d, 0xffff, 0x1666 }, in rtl_hw_start_8168ep_1()
3283 { 0x0c, 0x3ff0, 0x0000 } in rtl_hw_start_8168ep_1()
3298 { 0x00, 0xffff, 0x10a3 }, in rtl_hw_start_8168ep_2()
3299 { 0x19, 0xffff, 0xfc00 }, in rtl_hw_start_8168ep_2()
3300 { 0x1e, 0xffff, 0x20ea } in rtl_hw_start_8168ep_2()
3318 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8168ep_3()
3319 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8168ep_3()
3320 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8168ep_3()
3321 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168ep_3()
3333 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); in rtl_hw_start_8168ep_3()
3334 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8168ep_3()
3335 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8168ep_3()
3343 { 0x19, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3344 { 0x59, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3354 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8117()
3355 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8117()
3361 rtl_eri_set_bits(tp, 0xd4, 0x0010); in rtl_hw_start_8117()
3363 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8117()
3367 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3368 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3377 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8117()
3381 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8117()
3382 if (rg_saw_cnt > 0) { in rtl_hw_start_8117()
3385 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; in rtl_hw_start_8117()
3386 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8117()
3389 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8117()
3390 r8168_mac_ocp_write(tp, 0xea80, 0x0003); in rtl_hw_start_8117()
3391 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); in rtl_hw_start_8117()
3392 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8117()
3394 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8117()
3395 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8117()
3396 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8117()
3397 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8117()
3408 { 0x01, 0, 0x6e65 }, in rtl_hw_start_8102e_1()
3409 { 0x02, 0, 0x091f }, in rtl_hw_start_8102e_1()
3410 { 0x03, 0, 0xc2f9 }, in rtl_hw_start_8102e_1()
3411 { 0x06, 0, 0xafb5 }, in rtl_hw_start_8102e_1()
3412 { 0x07, 0, 0x0e00 }, in rtl_hw_start_8102e_1()
3413 { 0x19, 0, 0xec80 }, in rtl_hw_start_8102e_1()
3414 { 0x01, 0, 0x2e65 }, in rtl_hw_start_8102e_1()
3415 { 0x01, 0, 0x6e65 } in rtl_hw_start_8102e_1()
3446 rtl_ephy_write(tp, 0x03, 0xc2f9); in rtl_hw_start_8102e_3()
3452 { 0x01, 0xffff, 0x6fe5 }, in rtl_hw_start_8401()
3453 { 0x03, 0xffff, 0x0599 }, in rtl_hw_start_8401()
3454 { 0x06, 0xffff, 0xaf25 }, in rtl_hw_start_8401()
3455 { 0x07, 0xffff, 0x8e68 }, in rtl_hw_start_8401()
3465 { 0x07, 0, 0x4000 }, in rtl_hw_start_8105e_1()
3466 { 0x19, 0, 0x0200 }, in rtl_hw_start_8105e_1()
3467 { 0x19, 0, 0x0020 }, in rtl_hw_start_8105e_1()
3468 { 0x1e, 0, 0x2000 }, in rtl_hw_start_8105e_1()
3469 { 0x03, 0, 0x0001 }, in rtl_hw_start_8105e_1()
3470 { 0x19, 0, 0x0100 }, in rtl_hw_start_8105e_1()
3471 { 0x19, 0, 0x0004 }, in rtl_hw_start_8105e_1()
3472 { 0x0a, 0, 0x0020 } in rtl_hw_start_8105e_1()
3476 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
3479 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
3492 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); in rtl_hw_start_8105e_2()
3498 { 0x19, 0xffff, 0xff64 }, in rtl_hw_start_8402()
3499 { 0x1e, 0, 0x4000 } in rtl_hw_start_8402()
3505 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
3511 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); in rtl_hw_start_8402()
3513 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3514 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3515 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); in rtl_hw_start_8402()
3518 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3528 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
3535 rtl_set_aspm_entry_latency(tp, 0x2f); in rtl_hw_start_8106()
3537 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3540 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3548 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); in DECLARE_RTL_COND()
3555 RTL_W16(tp, 0x382, 0x221b); in rtl_hw_start_8125_common()
3556 RTL_W8(tp, 0x4500, 0); in rtl_hw_start_8125_common()
3557 RTL_W16(tp, 0x4800, 0); in rtl_hw_start_8125_common()
3560 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); in rtl_hw_start_8125_common()
3562 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); in rtl_hw_start_8125_common()
3564 r8168_mac_ocp_write(tp, 0xc140, 0xffff); in rtl_hw_start_8125_common()
3565 r8168_mac_ocp_write(tp, 0xc142, 0xffff); in rtl_hw_start_8125_common()
3567 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); in rtl_hw_start_8125_common()
3568 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8125_common()
3569 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8125_common()
3572 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3575 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); in rtl_hw_start_8125_common()
3577 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); in rtl_hw_start_8125_common()
3580 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); in rtl_hw_start_8125_common()
3582 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); in rtl_hw_start_8125_common()
3584 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); in rtl_hw_start_8125_common()
3585 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); in rtl_hw_start_8125_common()
3586 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); in rtl_hw_start_8125_common()
3587 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); in rtl_hw_start_8125_common()
3588 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); in rtl_hw_start_8125_common()
3589 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); in rtl_hw_start_8125_common()
3590 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); in rtl_hw_start_8125_common()
3591 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); in rtl_hw_start_8125_common()
3592 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); in rtl_hw_start_8125_common()
3594 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3595 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); in rtl_hw_start_8125_common()
3597 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3598 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); in rtl_hw_start_8125_common()
3600 r8168_mac_ocp_write(tp, 0xe098, 0xc302); in rtl_hw_start_8125_common()
3616 { 0x01, 0xffff, 0xa812 }, in rtl_hw_start_8125a_1()
3617 { 0x09, 0xffff, 0x520c }, in rtl_hw_start_8125a_1()
3618 { 0x04, 0xffff, 0xd000 }, in rtl_hw_start_8125a_1()
3619 { 0x0d, 0xffff, 0xf702 }, in rtl_hw_start_8125a_1()
3620 { 0x0a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_1()
3621 { 0x06, 0xffff, 0x001e }, in rtl_hw_start_8125a_1()
3622 { 0x08, 0xffff, 0x3595 }, in rtl_hw_start_8125a_1()
3623 { 0x20, 0xffff, 0x9455 }, in rtl_hw_start_8125a_1()
3624 { 0x21, 0xffff, 0x99ff }, in rtl_hw_start_8125a_1()
3625 { 0x02, 0xffff, 0x6046 }, in rtl_hw_start_8125a_1()
3626 { 0x29, 0xffff, 0xfe00 }, in rtl_hw_start_8125a_1()
3627 { 0x23, 0xffff, 0xab62 }, in rtl_hw_start_8125a_1()
3629 { 0x41, 0xffff, 0xa80c }, in rtl_hw_start_8125a_1()
3630 { 0x49, 0xffff, 0x520c }, in rtl_hw_start_8125a_1()
3631 { 0x44, 0xffff, 0xd000 }, in rtl_hw_start_8125a_1()
3632 { 0x4d, 0xffff, 0xf702 }, in rtl_hw_start_8125a_1()
3633 { 0x4a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_1()
3634 { 0x46, 0xffff, 0x001e }, in rtl_hw_start_8125a_1()
3635 { 0x48, 0xffff, 0x3595 }, in rtl_hw_start_8125a_1()
3636 { 0x60, 0xffff, 0x9455 }, in rtl_hw_start_8125a_1()
3637 { 0x61, 0xffff, 0x99ff }, in rtl_hw_start_8125a_1()
3638 { 0x42, 0xffff, 0x6046 }, in rtl_hw_start_8125a_1()
3639 { 0x69, 0xffff, 0xfe00 }, in rtl_hw_start_8125a_1()
3640 { 0x63, 0xffff, 0xab62 }, in rtl_hw_start_8125a_1()
3656 { 0x04, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3657 { 0x0a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3658 { 0x23, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3659 { 0x20, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3660 { 0x21, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3661 { 0x29, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3663 { 0x44, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3664 { 0x4a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3665 { 0x63, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3666 { 0x60, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3667 { 0x61, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3668 { 0x69, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3684 { 0x0b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3685 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3686 { 0x4b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3687 { 0x5e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3688 { 0x22, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3689 { 0x62, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3764 for (i = 0xa00; i < 0xb00; i += 4) in rtl_hw_start_8125()
3765 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3780 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8168()
3798 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8169()
3849 return 0; in rtl8169_change_mtu()
3856 desc->opts2 = 0; in rtl8169_mark_to_asic()
3874 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); in rtl8169_alloc_rx_data()
3891 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { in rtl8169_rx_clear()
3897 tp->RxDescArray[i].addr = 0; in rtl8169_rx_clear()
3898 tp->RxDescArray[i].opts1 = 0; in rtl8169_rx_clear()
3906 for (i = 0; i < NUM_RX_DESC; i++) { in rtl8169_rx_fill()
3920 return 0; in rtl8169_rx_fill()
3927 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); in rtl8169_init_ring()
3928 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); in rtl8169_init_ring()
3940 memset(desc, 0, sizeof(*desc)); in rtl8169_unmap_tx_skb()
3941 memset(tx_skb, 0, sizeof(*tx_skb)); in rtl8169_unmap_tx_skb()
3949 for (i = 0; i < n; i++) { in rtl8169_tx_clear_range()
4019 for (i = 0; i < NUM_RX_DESC; i++) in rtl_reset_work()
4053 opts1 = opts[0] | len; in rtl8169_tx_map()
4062 return 0; in rtl8169_tx_map()
4071 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { in rtl8169_xmit_frags()
4082 return 0; in rtl8169_xmit_frags()
4113 unsigned int padto = 0, len = skb->len; in rtl8125_quirk_udp_padto()
4163 opts[0] |= TD_LSO; in rtl8169_tso_csum_v1()
4164 opts[0] |= mss << TD0_MSS_SHIFT; in rtl8169_tso_csum_v1()
4169 opts[0] |= TD0_IP_CS | TD0_TCP_CS; in rtl8169_tso_csum_v1()
4171 opts[0] |= TD0_IP_CS | TD0_UDP_CS; in rtl8169_tso_csum_v1()
4186 opts[0] |= TD1_GTSENV4; in rtl8169_tso_csum_v2()
4188 if (skb_cow_head(skb, 0)) in rtl8169_tso_csum_v2()
4192 opts[0] |= TD1_GTSENV6; in rtl8169_tso_csum_v2()
4197 opts[0] |= transport_offset << GTTCPHO_SHIFT; in rtl8169_tso_csum_v2()
4260 RTL_W16(tp, TxPoll_8125, BIT(0)); in rtl8169_doorbell()
4282 opts[0] = 0; in rtl8169_start_xmit()
4430 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", in rtl8169_pcierr_interrupt()
4439 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; in rtl_tx()
4510 for (count = 0; count < budget; count++, tp->cur_rx++) { in rtl_rx()
4544 pkt_size = status & GENMASK(13, 0); in rtl_rx()
4596 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) in rtl8169_interrupt()
4692 return 0; in r8169_phy_connect()
4738 free_irq(pci_irq_vector(pdev, 0), tp); in rtl8169_close()
4751 return 0; in rtl8169_close()
4759 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); in rtl8169_netpoll()
4787 if (retval < 0) in rtl_open()
4793 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, in rtl_open()
4795 if (retval < 0) in rtl_open()
4811 free_irq(pci_irq_vector(pdev, 0), tp); in rtl_open()
4883 return 0; in rtl8169_runtime_resume()
4896 return 0; in rtl8169_suspend()
4919 return 0; in rtl8169_runtime_suspend()
4927 return 0; in rtl8169_runtime_suspend()
5064 value = rtl_eri_read(tp, 0xe0); in rtl_read_mac_address()
5066 value = rtl_eri_read(tp, 0xe4); in rtl_read_mac_address()
5087 if (phyaddr > 0) in r8169_mdio_read_reg()
5098 if (phyaddr > 0) in r8169_mdio_write_reg()
5103 return 0; in r8169_mdio_write_reg()
5119 new_bus->irq[0] = PHY_MAC_INTERRUPT; in r8169_mdio_register()
5130 tp->phydev = mdiobus_get_phy(new_bus, 0); in r8169_mdio_register()
5137 …dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be… in r8169_mdio_register()
5149 return 0; in r8169_mdio_register()
5160 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8168g()
5163 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); in rtl_hw_init_8168g()
5175 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8125()
5178 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); in rtl_hw_init_8125()
5179 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); in rtl_hw_init_8125()
5180 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); in rtl_hw_init_8125()
5205 return 0; in rtl_jumbo_max()
5240 rc = 0; in rtl_get_ether_clk()
5296 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; in rtl_init_one()
5318 if (rc < 0) { in rtl_init_one()
5323 if (pcim_set_mwi(pdev) < 0) in rtl_init_one()
5328 if (region < 0) { in rtl_init_one()
5340 if (rc < 0) { in rtl_init_one()
5347 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; in rtl_init_one()
5375 if (rc < 0) { in rtl_init_one()
5455 pci_irq_vector(pdev, 0)); in rtl_init_one()
5470 return 0; in rtl_init_one()