60 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\  argument
61 	FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
62 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\  argument
63 	FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
66 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
67 	FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
68 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
69 	FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
75 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\  argument
76 	FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
77 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\  argument
78 	FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)
90 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\  argument
91 	FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
92 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\  argument
93 	FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)
105 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\  argument
106 	FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
107 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\  argument
108 	FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)
114 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\  argument
115 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
116 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\  argument
117 	FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
120 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\  argument
121 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
122 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\  argument
123 	FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
126 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\  argument
127 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
128 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\  argument
129 	FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
135 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\  argument
136 	FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x)
137 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\  argument
138 	FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x)
144 #define ANA_AC_STAT_RESET_RESET_SET(x)\  argument
145 	FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
146 #define ANA_AC_STAT_RESET_RESET_GET(x)\  argument
147 	FIELD_GET(ANA_AC_STAT_RESET_RESET, x)
153 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\  argument
154 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
155 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\  argument
156 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
159 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\  argument
160 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
161 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\  argument
162 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
165 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\  argument
166 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
167 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\  argument
168 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
177 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
178 	FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
179 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
180 	FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
186 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\  argument
187 	FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
188 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\  argument
189 	FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
195 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
196 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
197 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
198 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
201 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
202 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
203 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
204 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
207 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
208 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
209 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
210 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
213 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
214 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
215 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
216 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
222 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
223 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
224 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
225 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
228 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
229 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
230 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
231 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
234 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
235 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
236 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
237 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
240 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
241 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
242 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
243 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
249 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\  argument
250 	FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
251 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\  argument
252 	FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
255 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\  argument
256 	FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
257 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\  argument
258 	FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
261 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\  argument
262 	FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
263 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\  argument
264 	FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
270 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\  argument
271 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
272 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\  argument
273 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
276 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\  argument
277 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
278 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\  argument
279 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
282 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\  argument
283 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
284 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\  argument
285 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
288 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\  argument
289 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
290 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\  argument
291 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
294 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\  argument
295 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
296 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\  argument
297 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
300 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\  argument
301 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
302 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\  argument
303 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
306 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\  argument
307 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
308 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\  argument
309 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
312 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\  argument
313 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
314 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\  argument
315 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
318 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\  argument
319 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
320 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\  argument
321 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
324 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\  argument
325 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
326 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\  argument
327 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
330 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\  argument
331 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
332 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\  argument
333 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
339 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\  argument
340 	FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
341 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\  argument
342 	FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
345 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\  argument
346 	FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
347 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\  argument
348 	FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
354 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\  argument
355 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
356 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\  argument
357 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
360 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\  argument
361 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
362 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\  argument
363 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
366 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\  argument
367 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
368 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\  argument
369 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
372 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\  argument
373 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
374 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\  argument
375 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
378 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\  argument
379 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
380 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\  argument
381 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
384 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\  argument
385 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
386 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\  argument
387 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
390 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\  argument
391 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
392 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\  argument
393 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
396 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\  argument
397 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
398 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\  argument
399 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
402 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\  argument
403 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
404 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\  argument
405 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)
408 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\  argument
409 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
410 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\  argument
411 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)
414 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\  argument
415 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
416 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\  argument
417 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
423 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\  argument
424 	FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
425 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\  argument
426 	FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
435 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
436 	FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x)
437 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
438 	FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x)
450 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\  argument
451 	FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
452 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\  argument
453 	FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
459 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\  argument
460 	FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x)
461 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\  argument
462 	FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x)
468 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\  argument
469 	FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
470 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\  argument
471 	FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
477 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\  argument
478 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
479 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\  argument
480 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
483 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\  argument
484 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
485 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\  argument
486 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
489 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\  argument
490 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
491 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\  argument
492 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
495 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\  argument
496 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
497 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\  argument
498 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
501 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\  argument
502 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
503 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\  argument
504 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
507 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\  argument
508 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
509 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\  argument
510 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
513 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\  argument
514 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
515 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\  argument
516 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
519 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\  argument
520 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
521 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\  argument
522 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
525 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\  argument
526 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
527 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\  argument
528 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
540 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\  argument
541 	FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
542 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\  argument
543 	FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
816 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
817 	FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
818 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
819 	FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
825 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
826 	FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
827 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
828 	FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
834 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
835 	FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
836 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
837 	FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
843 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
844 	FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
845 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
846 	FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
852 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
853 	FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
854 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
855 	FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
861 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
862 	FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
863 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
864 	FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
870 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
871 	FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
872 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
873 	FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
879 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
880 	FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
881 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
882 	FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
891 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\  argument
892 	FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
893 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\  argument
894 	FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
900 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\  argument
901 	FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x)
902 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\  argument
903 	FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x)
906 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\  argument
907 	FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
908 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\  argument
909 	FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
912 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\  argument
913 	FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
914 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\  argument
915 	FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
918 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\  argument
919 	FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
920 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\  argument
921 	FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
924 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\  argument
925 	FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
926 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\  argument
927 	FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
930 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\  argument
931 	FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x)
932 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\  argument
933 	FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x)
936 #define ASM_PORT_CFG_PAD_ENA_SET(x)\  argument
937 	FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
938 #define ASM_PORT_CFG_PAD_ENA_GET(x)\  argument
939 	FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
942 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\  argument
943 	FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
944 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\  argument
945 	FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
948 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\  argument
949 	FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
950 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\  argument
951 	FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
954 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\  argument
955 	FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
956 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\  argument
957 	FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
960 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\  argument
961 	FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x)
962 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\  argument
963 	FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x)
969 #define ASM_RAM_INIT_RAM_INIT_SET(x)\  argument
970 	FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x)
971 #define ASM_RAM_INIT_RAM_INIT_GET(x)\  argument
972 	FIELD_GET(ASM_RAM_INIT_RAM_INIT, x)
975 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
976 	FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x)
977 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
978 	FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x)
984 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\  argument
985 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
986 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\  argument
987 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
990 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\  argument
991 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
992 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\  argument
993 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
996 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\  argument
997 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
998 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\  argument
999 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
1002 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\  argument
1003 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
1004 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\  argument
1005 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
1008 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\  argument
1009 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
1010 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\  argument
1011 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
1014 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\  argument
1015 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
1016 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\  argument
1017 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
1023 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\  argument
1024 	FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
1025 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\  argument
1026 	FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
1029 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\  argument
1030 	FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
1031 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\  argument
1032 	FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
1035 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\  argument
1036 	FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
1037 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\  argument
1038 	FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
1041 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\  argument
1042 	FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
1043 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\  argument
1044 	FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
1047 #define CPU_PROC_CTRL_VINITHI_SET(x)\  argument
1048 	FIELD_PREP(CPU_PROC_CTRL_VINITHI, x)
1049 #define CPU_PROC_CTRL_VINITHI_GET(x)\  argument
1050 	FIELD_GET(CPU_PROC_CTRL_VINITHI, x)
1053 #define CPU_PROC_CTRL_CFGTE_SET(x)\  argument
1054 	FIELD_PREP(CPU_PROC_CTRL_CFGTE, x)
1055 #define CPU_PROC_CTRL_CFGTE_GET(x)\  argument
1056 	FIELD_GET(CPU_PROC_CTRL_CFGTE, x)
1059 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\  argument
1060 	FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x)
1061 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\  argument
1062 	FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x)
1065 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\  argument
1066 	FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
1067 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\  argument
1068 	FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
1071 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\  argument
1072 	FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
1073 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\  argument
1074 	FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
1077 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\  argument
1078 	FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x)
1079 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\  argument
1080 	FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x)
1083 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\  argument
1084 	FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x)
1085 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\  argument
1086 	FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x)
1089 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\  argument
1090 	FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
1091 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\  argument
1092 	FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
1095 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\  argument
1096 	FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x)
1097 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\  argument
1098 	FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
1104 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1105 	FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x)
1106 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1107 	FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x)
1110 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1111 	FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x)
1112 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1113 	FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x)
1119 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
1120 	FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1121 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
1122 	FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1125 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1126 	FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
1127 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1128 	FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
1134 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\  argument
1135 	FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
1136 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\  argument
1137 	FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
1143 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
1144 	FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
1145 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
1146 	FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
1149 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\  argument
1150 	FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
1151 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\  argument
1152 	FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
1158 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
1159 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1160 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
1161 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1164 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
1165 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1166 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
1167 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1170 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
1171 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1172 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
1173 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1176 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
1177 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1178 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
1179 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1182 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
1183 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1184 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
1185 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1188 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
1189 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1190 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
1191 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1194 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
1195 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1196 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
1197 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1203 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\  argument
1204 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
1205 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\  argument
1206 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
1209 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\  argument
1210 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
1211 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\  argument
1212 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
1215 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\  argument
1216 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
1217 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\  argument
1218 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
1221 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\  argument
1222 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
1223 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\  argument
1224 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
1227 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\  argument
1228 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
1229 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\  argument
1230 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
1236 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
1237 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1238 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
1239 	FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1242 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1243 	FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1244 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1245 	FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1248 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
1249 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1250 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
1251 	FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1254 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
1255 	FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1256 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
1257 	FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1260 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1261 	FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
1262 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1263 	FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
1266 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1267 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
1268 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1269 	FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
1272 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1273 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
1274 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1275 	FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
1278 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1279 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
1280 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1281 	FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
1284 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1285 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
1286 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1287 	FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
1293 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
1294 	FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
1295 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
1296 	FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
1302 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1303 	FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x)
1304 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1305 	FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x)
1308 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1309 	FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x)
1310 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1311 	FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x)
1317 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
1318 	FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1319 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
1320 	FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1323 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1324 	FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
1325 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1326 	FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
1332 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
1333 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1334 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
1335 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1338 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
1339 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1340 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
1341 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1344 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
1345 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1346 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
1347 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1350 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
1351 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1352 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
1353 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1356 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
1357 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1358 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
1359 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1362 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
1363 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1364 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
1365 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1368 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
1369 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1370 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
1371 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1377 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
1378 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1379 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
1380 	FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1383 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1384 	FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1385 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1386 	FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1389 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
1390 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1391 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
1392 	FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1395 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
1396 	FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1397 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
1398 	FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1401 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1402 	FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
1403 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1404 	FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
1407 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1408 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
1409 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1410 	FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
1413 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1414 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
1415 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1416 	FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
1419 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1420 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
1421 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1422 	FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
1425 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1426 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
1427 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1428 	FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
1434 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
1435 	FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
1436 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
1437 	FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
1443 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\  argument
1444 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
1445 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\  argument
1446 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
1449 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\  argument
1450 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x)
1451 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\  argument
1452 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x)
1455 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\  argument
1456 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
1457 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\  argument
1458 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
1464 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1465 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1466 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1467 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1470 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1471 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
1472 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1473 	FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
1476 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\  argument
1477 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
1478 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\  argument
1479 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
1482 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\  argument
1483 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
1484 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\  argument
1485 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
1488 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1489 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
1490 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1491 	FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
1494 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1495 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
1496 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1497 	FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
1500 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1501 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
1502 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1503 	FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
1506 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1507 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
1508 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1509 	FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
1515 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1516 	FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
1517 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1518 	FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
1521 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1522 	FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
1523 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1524 	FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
1530 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\  argument
1531 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
1532 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\  argument
1533 	FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
1536 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\  argument
1537 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
1538 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\  argument
1539 	FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
1542 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\  argument
1543 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
1544 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\  argument
1545 	FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
1551 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1552 	FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
1553 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1554 	FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
1560 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
1561 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
1562 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
1563 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
1566 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\  argument
1567 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
1568 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\  argument
1569 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
1572 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\  argument
1573 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
1574 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\  argument
1575 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
1578 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\  argument
1579 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
1580 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\  argument
1581 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
1587 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\  argument
1588 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
1589 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\  argument
1590 	FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
1593 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\  argument
1594 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
1595 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\  argument
1596 	FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
1602 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\  argument
1603 	FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
1604 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\  argument
1605 	FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
1611 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\  argument
1612 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
1613 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\  argument
1614 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
1617 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\  argument
1618 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
1619 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\  argument
1620 	FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
1623 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\  argument
1624 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
1625 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\  argument
1626 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
1629 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\  argument
1630 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
1631 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\  argument
1632 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
1638 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\  argument
1639 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
1640 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\  argument
1641 	FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
1644 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\  argument
1645 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x)
1646 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\  argument
1647 	FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x)
1650 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\  argument
1651 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
1652 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\  argument
1653 	FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
1656 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\  argument
1657 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
1658 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\  argument
1659 	FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
1662 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\  argument
1663 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
1664 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\  argument
1665 	FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
1671 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\  argument
1672 	FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
1673 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\  argument
1674 	FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
1677 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
1678 	FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
1679 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
1680 	FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
1683 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\  argument
1684 	FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
1685 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\  argument
1686 	FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
1692 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
1693 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
1694 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
1695 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
1698 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\  argument
1699 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
1700 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\  argument
1701 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
1704 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\  argument
1705 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
1706 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\  argument
1707 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
1713 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\  argument
1714 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
1715 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\  argument
1716 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
1719 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\  argument
1720 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
1721 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\  argument
1722 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
1725 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\  argument
1726 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
1727 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\  argument
1728 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
1734 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\  argument
1735 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
1736 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\  argument
1737 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
1740 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\  argument
1741 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
1742 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\  argument
1743 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
1746 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\  argument
1747 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
1748 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\  argument
1749 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
1752 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\  argument
1753 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
1754 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\  argument
1755 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
1761 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\  argument
1762 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
1763 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\  argument
1764 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
1767 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\  argument
1768 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
1769 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\  argument
1770 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
1773 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\  argument
1774 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
1775 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\  argument
1776 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
1782 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\  argument
1783 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
1784 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\  argument
1785 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
1788 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\  argument
1789 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
1790 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\  argument
1791 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
1794 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\  argument
1795 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
1796 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\  argument
1797 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
1800 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\  argument
1801 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
1802 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\  argument
1803 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
1809 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\  argument
1810 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
1811 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\  argument
1812 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
1815 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\  argument
1816 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
1817 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\  argument
1818 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
1821 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\  argument
1822 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
1823 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\  argument
1824 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
1827 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\  argument
1828 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
1829 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\  argument
1830 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
1836 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\  argument
1837 	FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
1838 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\  argument
1839 	FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
1842 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\  argument
1843 	FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
1844 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\  argument
1845 	FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
1851 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\  argument
1852 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
1853 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\  argument
1854 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
1857 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\  argument
1858 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x)
1859 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\  argument
1860 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x)
1863 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\  argument
1864 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
1865 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\  argument
1866 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
1869 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\  argument
1870 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
1871 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\  argument
1872 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
1875 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\  argument
1876 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
1877 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\  argument
1878 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
1881 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\  argument
1882 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
1883 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\  argument
1884 	FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
1887 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\  argument
1888 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
1889 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\  argument
1890 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
1893 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\  argument
1894 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
1895 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\  argument
1896 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
1899 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\  argument
1900 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
1901 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\  argument
1902 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
1905 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
1906 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
1907 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
1908 	FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
1911 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\  argument
1912 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
1913 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\  argument
1914 	FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
1917 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\  argument
1918 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
1919 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\  argument
1920 	FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
1923 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\  argument
1924 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
1925 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\  argument
1926 	FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
1932 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\  argument
1933 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
1934 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\  argument
1935 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
1938 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\  argument
1939 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
1940 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\  argument
1941 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
1944 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\  argument
1945 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
1946 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\  argument
1947 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
1950 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\  argument
1951 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
1952 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\  argument
1953 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
1956 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\  argument
1957 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
1958 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\  argument
1959 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
1962 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\  argument
1963 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
1964 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\  argument
1965 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
1968 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\  argument
1969 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
1970 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\  argument
1971 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
1974 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\  argument
1975 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
1976 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\  argument
1977 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
1983 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1984 	FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x)
1985 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1986 	FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x)
1989 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1990 	FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x)
1991 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1992 	FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x)
1998 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
1999 	FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2000 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
2001 	FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2004 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
2005 	FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
2006 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
2007 	FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
2013 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
2014 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2015 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
2016 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2019 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
2020 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2021 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
2022 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2025 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
2026 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2027 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
2028 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2031 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
2032 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2033 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
2034 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2037 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
2038 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2039 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
2040 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2043 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
2044 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2045 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
2046 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2049 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
2050 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2051 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
2052 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2297 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
2298 	FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2299 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
2300 	FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2309 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2310 	FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2311 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2312 	FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2321 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2322 	FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2323 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2324 	FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2333 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
2334 	FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2335 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
2336 	FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2345 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2346 	FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2347 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2348 	FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2357 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2358 	FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2359 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2360 	FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2369 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2370 	FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2371 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2372 	FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2381 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2382 	FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2383 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2384 	FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2390 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
2391 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2392 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
2393 	FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2396 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
2397 	FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2398 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
2399 	FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2402 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
2403 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2404 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
2405 	FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2408 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
2409 	FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2410 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
2411 	FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2414 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
2415 	FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
2416 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
2417 	FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
2420 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
2421 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
2422 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
2423 	FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
2426 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
2427 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
2428 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
2429 	FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
2432 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
2433 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
2434 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
2435 	FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
2438 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
2439 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
2440 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
2441 	FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
2447 #define DSM_RAM_INIT_RAM_INIT_SET(x)\  argument
2448 	FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x)
2449 #define DSM_RAM_INIT_RAM_INIT_GET(x)\  argument
2450 	FIELD_GET(DSM_RAM_INIT_RAM_INIT, x)
2453 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
2454 	FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x)
2455 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
2456 	FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x)
2462 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\  argument
2463 	FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x)
2464 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\  argument
2465 	FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x)
2468 #define DSM_BUF_CFG_AGING_ENA_SET(x)\  argument
2469 	FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x)
2470 #define DSM_BUF_CFG_AGING_ENA_GET(x)\  argument
2471 	FIELD_GET(DSM_BUF_CFG_AGING_ENA, x)
2474 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\  argument
2475 	FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
2476 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\  argument
2477 	FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
2480 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\  argument
2481 	FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
2482 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\  argument
2483 	FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
2489 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\  argument
2490 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
2491 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\  argument
2492 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
2495 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\  argument
2496 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
2497 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\  argument
2498 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
2501 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\  argument
2502 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
2503 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\  argument
2504 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
2507 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\  argument
2508 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
2509 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\  argument
2510 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
2516 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\  argument
2517 	FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
2518 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\  argument
2519 	FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
2522 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\  argument
2523 	FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
2524 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\  argument
2525 	FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
2531 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\  argument
2532 	FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x)
2533 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\  argument
2534 	FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x)
2537 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\  argument
2538 	FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
2539 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\  argument
2540 	FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
2543 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\  argument
2544 	FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
2545 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\  argument
2546 	FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
2549 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\  argument
2550 	FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
2551 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\  argument
2552 	FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
2558 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\  argument
2559 	FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
2560 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\  argument
2561 	FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
2567 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\  argument
2568 	FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
2569 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\  argument
2570 	FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
2576 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\  argument
2577 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
2578 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\  argument
2579 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
2582 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\  argument
2583 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
2584 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\  argument
2585 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
2588 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\  argument
2589 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
2590 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\  argument
2591 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
2594 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\  argument
2595 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
2596 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\  argument
2597 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
2600 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\  argument
2601 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
2602 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\  argument
2603 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
2609 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\  argument
2610 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
2611 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\  argument
2612 	FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
2615 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\  argument
2616 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
2617 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\  argument
2618 	FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
2621 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\  argument
2622 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
2623 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\  argument
2624 	FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
2627 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\  argument
2628 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
2629 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\  argument
2630 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
2633 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\  argument
2634 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
2635 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\  argument
2636 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
2639 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\  argument
2640 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
2641 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\  argument
2642 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
2648 #define EACL_RAM_INIT_RAM_INIT_SET(x)\  argument
2649 	FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x)
2650 #define EACL_RAM_INIT_RAM_INIT_GET(x)\  argument
2651 	FIELD_GET(EACL_RAM_INIT_RAM_INIT, x)
2654 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
2655 	FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x)
2656 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
2657 	FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x)
2663 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\  argument
2664 	FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
2665 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\  argument
2666 	FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
2672 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\  argument
2673 	FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
2674 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\  argument
2675 	FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
2681 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\  argument
2682 	FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
2683 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\  argument
2684 	FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
2702 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\  argument
2703 	FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
2704 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\  argument
2705 	FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
2708 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\  argument
2709 	FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
2710 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\  argument
2711 	FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
2714 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\  argument
2715 	FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
2716 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\  argument
2717 	FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
2720 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\  argument
2721 	FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
2722 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\  argument
2723 	FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
2726 #define FDMA_CH_CFG_CH_MEM_SET(x)\  argument
2727 	FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
2728 #define FDMA_CH_CFG_CH_MEM_GET(x)\  argument
2729 	FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
2735 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\  argument
2736 	FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x)
2737 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\  argument
2738 	FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x)
2744 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\  argument
2745 	FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x)
2746 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\  argument
2747 	FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x)
2750 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\  argument
2751 	FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x)
2752 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\  argument
2753 	FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x)
2759 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\  argument
2760 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
2761 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\  argument
2762 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
2765 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\  argument
2766 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
2767 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\  argument
2768 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
2771 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\  argument
2772 	FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
2773 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\  argument
2774 	FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
2777 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\  argument
2778 	FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
2779 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\  argument
2780 	FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
2783 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\  argument
2784 	FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x)
2785 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\  argument
2786 	FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x)
2792 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\  argument
2793 	FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x)
2794 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\  argument
2795 	FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x)
2801 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\  argument
2802 	FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
2803 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\  argument
2804 	FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
2810 #define FDMA_INTR_DB_INTR_DB_SET(x)\  argument
2811 	FIELD_PREP(FDMA_INTR_DB_INTR_DB, x)
2812 #define FDMA_INTR_DB_INTR_DB_GET(x)\  argument
2813 	FIELD_GET(FDMA_INTR_DB_INTR_DB, x)
2819 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\  argument
2820 	FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
2821 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\  argument
2822 	FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
2828 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\  argument
2829 	FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x)
2830 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\  argument
2831 	FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x)
2834 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\  argument
2835 	FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x)
2836 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\  argument
2837 	FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x)
2843 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\  argument
2844 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x)
2845 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\  argument
2846 	FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x)
2849 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\  argument
2850 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x)
2851 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\  argument
2852 	FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x)
2855 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\  argument
2856 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
2857 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\  argument
2858 	FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
2861 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\  argument
2862 	FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
2863 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\  argument
2864 	FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
2867 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\  argument
2868 	FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x)
2869 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\  argument
2870 	FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x)
2873 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\  argument
2874 	FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x)
2875 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\  argument
2876 	FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x)
2879 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\  argument
2880 	FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
2881 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\  argument
2882 	FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
2885 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\  argument
2886 	FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x)
2887 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\  argument
2888 	FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x)
2894 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\  argument
2895 	FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
2896 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\  argument
2897 	FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
2903 #define FDMA_CTRL_NRESET_SET(x)\  argument
2904 	FIELD_PREP(FDMA_CTRL_NRESET, x)
2905 #define FDMA_CTRL_NRESET_GET(x)\  argument
2906 	FIELD_GET(FDMA_CTRL_NRESET, x)
2912 #define GCB_CHIP_ID_REV_ID_SET(x)\  argument
2913 	FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
2914 #define GCB_CHIP_ID_REV_ID_GET(x)\  argument
2915 	FIELD_GET(GCB_CHIP_ID_REV_ID, x)
2918 #define GCB_CHIP_ID_PART_ID_SET(x)\  argument
2919 	FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
2920 #define GCB_CHIP_ID_PART_ID_GET(x)\  argument
2921 	FIELD_GET(GCB_CHIP_ID_PART_ID, x)
2924 #define GCB_CHIP_ID_MFG_ID_SET(x)\  argument
2925 	FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
2926 #define GCB_CHIP_ID_MFG_ID_GET(x)\  argument
2927 	FIELD_GET(GCB_CHIP_ID_MFG_ID, x)
2930 #define GCB_CHIP_ID_ONE_SET(x)\  argument
2931 	FIELD_PREP(GCB_CHIP_ID_ONE, x)
2932 #define GCB_CHIP_ID_ONE_GET(x)\  argument
2933 	FIELD_GET(GCB_CHIP_ID_ONE, x)
2939 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\  argument
2940 	FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
2941 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\  argument
2942 	FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
2945 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\  argument
2946 	FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x)
2947 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\  argument
2948 	FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x)
2951 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\  argument
2952 	FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
2953 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\  argument
2954 	FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
2960 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\  argument
2961 	FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
2962 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\  argument
2963 	FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
2966 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\  argument
2967 	FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
2968 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\  argument
2969 	FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
2975 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\  argument
2976 	FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
2977 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\  argument
2978 	FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
2984 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\  argument
2985 	FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
2986 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\  argument
2987 	FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
2990 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\  argument
2991 	FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
2992 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\  argument
2993 	FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
2999 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(x)\  argument
3000 	FIELD_PREP(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x)
3001 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_GET(x)\  argument
3002 	FIELD_GET(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x)
3008 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\  argument
3009 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
3010 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\  argument
3011 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
3014 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\  argument
3015 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
3016 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\  argument
3017 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
3020 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\  argument
3021 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x)
3022 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\  argument
3023 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x)
3026 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\  argument
3027 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
3028 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\  argument
3029 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
3032 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\  argument
3033 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
3034 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\  argument
3035 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
3038 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\  argument
3039 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x)
3040 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\  argument
3041 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x)
3044 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\  argument
3045 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
3046 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\  argument
3047 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
3053 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\  argument
3054 	FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x)
3055 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\  argument
3056 	FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x)
3059 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\  argument
3060 	FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x)
3061 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\  argument
3062 	FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x)
3065 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\  argument
3066 	FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x)
3067 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\  argument
3068 	FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x)
3071 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\  argument
3072 	FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
3073 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\  argument
3074 	FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
3077 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\  argument
3078 	FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
3079 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\  argument
3080 	FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
3086 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\  argument
3087 	FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
3088 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\  argument
3089 	FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
3095 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\  argument
3096 	FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
3097 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\  argument
3098 	FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
3104 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\  argument
3105 	FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
3106 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\  argument
3107 	FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
3113 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\  argument
3114 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
3115 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\  argument
3116 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
3119 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\  argument
3120 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
3121 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\  argument
3122 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
3125 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\  argument
3126 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
3127 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\  argument
3128 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
3131 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\  argument
3132 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
3133 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\  argument
3134 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
3137 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\  argument
3138 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
3139 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\  argument
3140 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
3146 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\  argument
3147 	FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
3148 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\  argument
3149 	FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
3152 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\  argument
3153 	FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
3154 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\  argument
3155 	FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
3164 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\  argument
3165 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
3166 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\  argument
3167 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
3170 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\  argument
3171 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
3172 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\  argument
3173 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
3176 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\  argument
3177 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
3178 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\  argument
3179 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
3182 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\  argument
3183 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
3184 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\  argument
3185 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
3188 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\  argument
3189 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
3190 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\  argument
3191 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
3194 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\  argument
3195 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
3196 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\  argument
3197 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
3200 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\  argument
3201 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
3202 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\  argument
3203 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
3206 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\  argument
3207 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
3208 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\  argument
3209 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
3212 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\  argument
3213 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
3214 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\  argument
3215 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
3218 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\  argument
3219 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
3220 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\  argument
3221 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
3224 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\  argument
3225 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
3226 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\  argument
3227 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
3230 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\  argument
3231 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
3232 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\  argument
3233 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
3239 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\  argument
3240 	FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
3241 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\  argument
3242 	FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
3248 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\  argument
3249 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
3250 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\  argument
3251 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
3254 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\  argument
3255 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
3256 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\  argument
3257 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
3260 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\  argument
3261 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
3262 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\  argument
3263 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
3266 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\  argument
3267 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
3268 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\  argument
3269 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
3272 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\  argument
3273 	FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
3274 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\  argument
3275 	FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
3278 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\  argument
3279 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
3280 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\  argument
3281 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
3284 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\  argument
3285 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
3286 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\  argument
3287 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
3290 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\  argument
3291 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
3292 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\  argument
3293 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
3296 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\  argument
3297 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
3298 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\  argument
3299 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
3302 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\  argument
3303 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
3304 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\  argument
3305 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
3308 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\  argument
3309 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
3310 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\  argument
3311 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
3314 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\  argument
3315 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
3316 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\  argument
3317 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
3320 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\  argument
3321 	FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
3322 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\  argument
3323 	FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
3326 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\  argument
3327 	FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
3328 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\  argument
3329 	FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
3332 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\  argument
3333 	FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
3334 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\  argument
3335 	FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
3341 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\  argument
3342 	FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
3343 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\  argument
3344 	FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
3347 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\  argument
3348 	FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
3349 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\  argument
3350 	FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
3356 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\  argument
3357 	FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
3358 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\  argument
3359 	FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
3362 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\  argument
3363 	FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
3364 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\  argument
3365 	FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
3371 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\  argument
3372 	FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
3373 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\  argument
3374 	FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
3377 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\  argument
3378 	FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
3379 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\  argument
3380 	FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
3383 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\  argument
3384 	FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
3385 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\  argument
3386 	FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
3389 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\  argument
3390 	FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
3391 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\  argument
3392 	FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
3395 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\  argument
3396 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
3397 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\  argument
3398 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
3401 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\  argument
3402 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
3403 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\  argument
3404 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
3407 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\  argument
3408 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
3409 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\  argument
3410 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
3416 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\  argument
3417 	FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
3418 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\  argument
3419 	FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
3422 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\  argument
3423 	FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
3424 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\  argument
3425 	FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
3431 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\  argument
3432 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
3433 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\  argument
3434 	FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
3437 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\  argument
3438 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x)
3439 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\  argument
3440 	FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x)
3443 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\  argument
3444 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
3445 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\  argument
3446 	FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
3449 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\  argument
3450 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
3451 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\  argument
3452 	FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
3455 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\  argument
3456 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x)
3457 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\  argument
3458 	FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x)
3461 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\  argument
3462 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
3463 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\  argument
3464 	FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
3467 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\  argument
3468 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
3469 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\  argument
3470 	FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
3473 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\  argument
3474 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
3475 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\  argument
3476 	FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
3479 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\  argument
3480 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
3481 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\  argument
3482 	FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
3485 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\  argument
3486 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
3487 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\  argument
3488 	FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
3494 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\  argument
3495 	FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
3496 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\  argument
3497 	FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
3500 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\  argument
3501 	FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
3502 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\  argument
3503 	FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
3512 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\  argument
3513 	FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
3514 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\  argument
3515 	FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
3518 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\  argument
3519 	FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
3520 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\  argument
3521 	FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
3533 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\  argument
3534 	FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
3535 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\  argument
3536 	FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
3539 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\  argument
3540 	FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
3541 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\  argument
3542 	FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
3548 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3549 	FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x)
3550 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3551 	FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x)
3554 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3555 	FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3556 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3557 	FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3560 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3561 	FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
3562 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3563 	FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
3566 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3567 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
3568 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3569 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
3572 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3573 	FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
3574 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3575 	FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
3578 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3579 	FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
3580 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3581 	FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
3584 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3585 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
3586 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3587 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
3590 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3591 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3592 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3593 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3596 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3597 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
3598 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3599 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
3602 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3603 	FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3604 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3605 	FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3608 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3609 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
3610 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3611 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
3614 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3615 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3616 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3617 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3623 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3624 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
3625 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3626 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
3629 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3630 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
3631 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3632 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
3635 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3636 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
3637 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
3638 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
3644 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3645 	FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x)
3646 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3647 	FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x)
3650 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3651 	FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3652 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3653 	FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3656 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3657 	FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
3658 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3659 	FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
3662 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3663 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
3664 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3665 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
3668 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3669 	FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
3670 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3671 	FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
3674 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3675 	FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
3676 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3677 	FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
3680 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3681 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
3682 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3683 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
3686 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3687 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3688 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3689 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3692 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3693 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
3694 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3695 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
3698 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3699 	FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3700 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3701 	FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3704 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3705 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
3706 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3707 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
3710 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3711 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3712 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3713 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3719 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3720 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
3721 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3722 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
3725 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3726 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
3727 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3728 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
3731 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3732 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
3733 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
3734 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
3740 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3741 	FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x)
3742 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3743 	FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x)
3746 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3747 	FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3748 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3749 	FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3752 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3753 	FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
3754 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3755 	FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
3758 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3759 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
3760 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3761 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
3764 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3765 	FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
3766 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3767 	FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
3770 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3771 	FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
3772 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3773 	FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
3776 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3777 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
3778 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3779 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
3782 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3783 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3784 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3785 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3788 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3789 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
3790 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3791 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
3794 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3795 	FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3796 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3797 	FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3800 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3801 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
3802 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3803 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
3806 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3807 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3808 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3809 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3815 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3816 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
3817 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3818 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
3821 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3822 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
3823 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3824 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
3827 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3828 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
3829 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
3830 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
3836 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\  argument
3837 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
3838 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\  argument
3839 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
3842 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\  argument
3843 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
3844 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\  argument
3845 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
3848 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\  argument
3849 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
3850 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\  argument
3851 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
3854 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\  argument
3855 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
3856 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\  argument
3857 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
3860 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\  argument
3861 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
3862 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\  argument
3863 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
3866 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\  argument
3867 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
3868 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\  argument
3869 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
3872 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\  argument
3873 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
3874 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\  argument
3875 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
3878 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\  argument
3879 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
3880 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\  argument
3881 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
3884 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\  argument
3885 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
3886 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\  argument
3887 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
3890 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\  argument
3891 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
3892 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\  argument
3893 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
3896 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\  argument
3897 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
3898 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\  argument
3899 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
3902 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\  argument
3903 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
3904 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\  argument
3905 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
3908 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\  argument
3909 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
3910 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\  argument
3911 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
3917 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\  argument
3918 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
3919 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\  argument
3920 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
3923 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\  argument
3924 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
3925 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\  argument
3926 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
3929 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\  argument
3930 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
3931 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\  argument
3932 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
3935 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\  argument
3936 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
3937 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\  argument
3938 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
3941 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\  argument
3942 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
3943 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\  argument
3944 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
3947 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\  argument
3948 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
3949 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\  argument
3950 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
3953 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\  argument
3954 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
3955 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\  argument
3956 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
3959 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\  argument
3960 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
3961 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\  argument
3962 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
3965 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\  argument
3966 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
3967 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\  argument
3968 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
3971 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\  argument
3972 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
3973 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\  argument
3974 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
3977 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\  argument
3978 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
3979 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\  argument
3980 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
3983 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\  argument
3984 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
3985 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\  argument
3986 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
3992 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\  argument
3993 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
3994 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\  argument
3995 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
3998 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\  argument
3999 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
4000 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\  argument
4001 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
4004 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\  argument
4005 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
4006 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\  argument
4007 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
4010 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\  argument
4011 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
4012 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\  argument
4013 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
4016 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\  argument
4017 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
4018 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\  argument
4019 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
4022 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\  argument
4023 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
4024 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\  argument
4025 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
4028 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\  argument
4029 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
4030 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\  argument
4031 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
4034 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\  argument
4035 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
4036 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\  argument
4037 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
4043 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\  argument
4044 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
4045 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\  argument
4046 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
4049 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\  argument
4050 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
4051 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\  argument
4052 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
4055 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\  argument
4056 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
4057 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\  argument
4058 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
4061 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\  argument
4062 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
4063 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\  argument
4064 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
4067 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\  argument
4068 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
4069 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\  argument
4070 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
4073 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\  argument
4074 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
4075 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\  argument
4076 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
4079 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\  argument
4080 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
4081 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\  argument
4082 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
4085 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\  argument
4086 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
4087 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\  argument
4088 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
4091 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\  argument
4092 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
4093 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\  argument
4094 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
4097 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\  argument
4098 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
4099 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\  argument
4100 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
4103 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\  argument
4104 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
4105 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\  argument
4106 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
4109 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\  argument
4110 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
4111 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\  argument
4112 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
4118 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\  argument
4119 	FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
4120 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\  argument
4121 	FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
4124 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\  argument
4125 	FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
4126 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\  argument
4127 	FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
4130 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\  argument
4131 	FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
4132 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\  argument
4133 	FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
4136 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\  argument
4137 	FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
4138 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\  argument
4139 	FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
4142 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\  argument
4143 	FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
4144 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\  argument
4145 	FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
4148 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\  argument
4149 	FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
4150 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\  argument
4151 	FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
4154 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\  argument
4155 	FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
4156 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\  argument
4157 	FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
4163 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\  argument
4164 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
4165 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\  argument
4166 	FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
4169 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\  argument
4170 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
4171 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\  argument
4172 	FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
4175 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\  argument
4176 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
4177 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\  argument
4178 	FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
4181 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\  argument
4182 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
4183 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\  argument
4184 	FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
4187 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\  argument
4188 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
4189 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\  argument
4190 	FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
4193 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\  argument
4194 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
4195 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\  argument
4196 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
4199 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\  argument
4200 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
4201 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\  argument
4202 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
4205 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\  argument
4206 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
4207 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\  argument
4208 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
4211 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\  argument
4212 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
4213 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\  argument
4214 	FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
4220 #define QRES_RES_CFG_WM_HIGH_SET(x)\  argument
4221 	FIELD_PREP(QRES_RES_CFG_WM_HIGH, x)
4222 #define QRES_RES_CFG_WM_HIGH_GET(x)\  argument
4223 	FIELD_GET(QRES_RES_CFG_WM_HIGH, x)
4229 #define QRES_RES_STAT_MAXUSE_SET(x)\  argument
4230 	FIELD_PREP(QRES_RES_STAT_MAXUSE, x)
4231 #define QRES_RES_STAT_MAXUSE_GET(x)\  argument
4232 	FIELD_GET(QRES_RES_STAT_MAXUSE, x)
4238 #define QRES_RES_STAT_CUR_INUSE_SET(x)\  argument
4239 	FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x)
4240 #define QRES_RES_STAT_CUR_INUSE_GET(x)\  argument
4241 	FIELD_GET(QRES_RES_STAT_CUR_INUSE, x)
4247 #define QS_XTR_GRP_CFG_MODE_SET(x)\  argument
4248 	FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
4249 #define QS_XTR_GRP_CFG_MODE_GET(x)\  argument
4250 	FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
4253 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\  argument
4254 	FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
4255 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\  argument
4256 	FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
4259 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\  argument
4260 	FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
4261 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\  argument
4262 	FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
4271 #define QS_XTR_FLUSH_FLUSH_SET(x)\  argument
4272 	FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
4273 #define QS_XTR_FLUSH_FLUSH_GET(x)\  argument
4274 	FIELD_GET(QS_XTR_FLUSH_FLUSH, x)
4280 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\  argument
4281 	FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
4282 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\  argument
4283 	FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
4289 #define QS_INJ_GRP_CFG_MODE_SET(x)\  argument
4290 	FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
4291 #define QS_INJ_GRP_CFG_MODE_GET(x)\  argument
4292 	FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
4295 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\  argument
4296 	FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
4297 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\  argument
4298 	FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
4307 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\  argument
4308 	FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
4309 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\  argument
4310 	FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
4313 #define QS_INJ_CTRL_ABORT_SET(x)\  argument
4314 	FIELD_PREP(QS_INJ_CTRL_ABORT, x)
4315 #define QS_INJ_CTRL_ABORT_GET(x)\  argument
4316 	FIELD_GET(QS_INJ_CTRL_ABORT, x)
4319 #define QS_INJ_CTRL_EOF_SET(x)\  argument
4320 	FIELD_PREP(QS_INJ_CTRL_EOF, x)
4321 #define QS_INJ_CTRL_EOF_GET(x)\  argument
4322 	FIELD_GET(QS_INJ_CTRL_EOF, x)
4325 #define QS_INJ_CTRL_SOF_SET(x)\  argument
4326 	FIELD_PREP(QS_INJ_CTRL_SOF, x)
4327 #define QS_INJ_CTRL_SOF_GET(x)\  argument
4328 	FIELD_GET(QS_INJ_CTRL_SOF, x)
4331 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\  argument
4332 	FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
4333 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\  argument
4334 	FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
4340 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\  argument
4341 	FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
4342 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\  argument
4343 	FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
4346 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\  argument
4347 	FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
4348 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\  argument
4349 	FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
4352 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\  argument
4353 	FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
4354 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\  argument
4355 	FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
4361 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\  argument
4362 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x)
4363 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\  argument
4364 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x)
4367 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\  argument
4368 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x)
4369 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\  argument
4370 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x)
4373 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\  argument
4374 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x)
4375 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\  argument
4376 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x)
4379 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\  argument
4380 	FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
4381 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\  argument
4382 	FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
4388 #define QSYS_ATOP_ATOP_SET(x)\  argument
4389 	FIELD_PREP(QSYS_ATOP_ATOP, x)
4390 #define QSYS_ATOP_ATOP_GET(x)\  argument
4391 	FIELD_GET(QSYS_ATOP_ATOP, x)
4397 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\  argument
4398 	FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
4399 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\  argument
4400 	FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
4403 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\  argument
4404 	FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
4405 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\  argument
4406 	FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
4412 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\  argument
4413 	FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
4414 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\  argument
4415 	FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
4421 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\  argument
4422 	FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x)
4423 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\  argument
4424 	FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x)
4430 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\  argument
4431 	FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
4432 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\  argument
4433 	FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
4436 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\  argument
4437 	FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
4438 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\  argument
4439 	FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
4442 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\  argument
4443 	FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
4444 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\  argument
4445 	FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
4451 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\  argument
4452 	FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x)
4453 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\  argument
4454 	FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x)
4457 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4458 	FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
4459 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4460 	FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
4466 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\  argument
4467 	FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x)
4468 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\  argument
4469 	FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x)
4475 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\  argument
4476 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x)
4477 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\  argument
4478 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x)
4481 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\  argument
4482 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x)
4483 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\  argument
4484 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x)
4487 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\  argument
4488 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
4489 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\  argument
4490 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
4496 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\  argument
4497 	FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
4498 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\  argument
4499 	FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
4502 #define REW_TAG_CTRL_TAG_CFG_SET(x)\  argument
4503 	FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x)
4504 #define REW_TAG_CTRL_TAG_CFG_GET(x)\  argument
4505 	FIELD_GET(REW_TAG_CTRL_TAG_CFG, x)
4508 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\  argument
4509 	FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x)
4510 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\  argument
4511 	FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x)
4514 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\  argument
4515 	FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x)
4516 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\  argument
4517 	FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x)
4520 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\  argument
4521 	FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x)
4522 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\  argument
4523 	FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x)
4526 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\  argument
4527 	FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x)
4528 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\  argument
4529 	FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
4535 #define REW_RAM_INIT_RAM_INIT_SET(x)\  argument
4536 	FIELD_PREP(REW_RAM_INIT_RAM_INIT, x)
4537 #define REW_RAM_INIT_RAM_INIT_GET(x)\  argument
4538 	FIELD_GET(REW_RAM_INIT_RAM_INIT, x)
4541 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4542 	FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x)
4543 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4544 	FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x)
4550 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\  argument
4551 	FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
4552 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\  argument
4553 	FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
4556 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4557 	FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
4558 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4559 	FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
4565 #define VOP_RAM_INIT_RAM_INIT_SET(x)\  argument
4566 	FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x)
4567 #define VOP_RAM_INIT_RAM_INIT_GET(x)\  argument
4568 	FIELD_GET(VOP_RAM_INIT_RAM_INIT, x)
4571 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4572 	FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x)
4573 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4574 	FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x)
4580 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\  argument
4581 	FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
4582 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\  argument
4583 	FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
4586 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\  argument
4587 	FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x)
4588 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\  argument
4589 	FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x)
4592 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\  argument
4593 	FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
4594 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\  argument
4595 	FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
4598 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\  argument
4599 	FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x)
4600 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\  argument
4601 	FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x)
4607 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\  argument
4608 	FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
4609 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\  argument
4610 	FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
4616 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\  argument
4617 	FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
4618 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\  argument
4619 	FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
4625 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\  argument
4626 	FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
4627 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\  argument
4628 	FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
4634 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\  argument
4635 	FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
4636 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\  argument
4637 	FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)