Lines Matching +full:0 +full:xfffe
14 #define MLXSW_PCI_CIR_BASE 0x71000
16 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
17 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
18 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
19 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
20 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
21 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
30 #define MLXSW_PCI_FW_READY 0xA1844
31 #define MLXSW_PCI_FW_READY_MASK 0xFFFF
32 #define MLXSW_PCI_FW_READY_MAGIC 0x5E
34 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
35 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
36 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
37 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
38 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
39 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
49 #define MLXSW_PCI_EQ_ASYNC_NUM 0
53 #define MLXSW_PCI_SDQ_EMAD_INDEX 0
54 #define MLXSW_PCI_SDQ_EMAD_TC 0
68 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
71 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
77 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
89 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
94 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
97 * Size of i-th scatter/gather entry, 0 if entry is unused.
99 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
105 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
146 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
147 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
148 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
151 * When lag=0: System port on which the packet was received
154 * bits [3:0] sub_port on which the packet was received
156 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
157 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
158 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
159 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
160 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
161 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
162 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
167 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
174 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
176 #define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID 0xFFFF
180 * packet that does mirroring to the CPU. Value of 0xFFFF means that the
183 MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
188 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
194 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
195 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
196 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
201 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
202 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
203 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
207 * 0 - Receive Queue
209 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
210 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
211 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
216 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
217 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
218 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
220 #define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID 0x1F
224 * CPU. Value of 0x1F means that the traffic class is invalid.
226 MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
231 MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
235 * CPU. Reserved when tx_lag is 0.
237 MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
239 #define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT 0xFFFE
240 #define MLXSW_PCI_CQE2_TX_PORT_INVALID 0xFFFF
244 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID
245 * is invalid. Reserved when tx_lag is 0.
247 MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
251 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is
254 MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
258 * packet that does mirroring to the CPU. Value of 0xFFFF means that the
261 MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
276 MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
281 MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
283 #define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID 0xFFFFFF
287 * Value of 0xFFFFFF means that the latency is invalid. Units are according to
290 MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
295 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
296 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
302 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
303 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
304 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
309 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
314 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
319 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
324 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
329 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
334 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
339 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);