Lines Matching +full:0 +full:x10100
25 #define MTK_TX_DMA_BUF_LEN 0x3fff
31 #define MTK_DMA_DUMMY_DESC 0xffffffff
66 #define MTK_RST_GL 0x04
67 #define RST_GL_PSE BIT(0)
70 #define MTK_INT_STATUS2 0x08
75 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
78 #define MTK_FE_INT_GRP 0x20
81 #define MTK_CDMQ_IG_CTRL 0x1400
82 #define MTK_CDMQ_STAG_EN BIT(0)
85 #define MTK_CDMP_EG_CTRL 0x404
88 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
93 #define MTK_GDMA_TO_PDMA 0x0
94 #define MTK_GDMA_TO_PPE 0x4444
95 #define MTK_GDMA_DROP_ALL 0x7777
98 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
101 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
104 #define MTK_PRX_BASE_PTR0 0x900
105 #define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
108 #define MTK_PRX_MAX_CNT0 0x904
109 #define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
112 #define MTK_PRX_CRX_IDX0 0x908
113 #define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
116 #define MTK_PDMA_LRO_CTRL_DW0 0x980
117 #define MTK_LRO_EN BIT(0)
120 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
121 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
123 #define MTK_PDMA_LRO_CTRL_DW1 0x984
124 #define MTK_PDMA_LRO_CTRL_DW2 0x988
125 #define MTK_PDMA_LRO_CTRL_DW3 0x98c
130 #define MTK_PDMA_GLO_CFG 0xa04
135 #define MTK_PDMA_RST_IDX 0xa08
140 #define MTK_PDMA_DELAY_INT 0xa0c
141 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
144 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0
151 #define MTK_PDMA_DELAY_PINT_MASK 0x7f
152 #define MTK_PDMA_DELAY_PTIME_MASK 0xff
155 #define MTK_PDMA_INT_STATUS 0xa20
158 #define MTK_PDMA_INT_MASK 0xa28
161 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
164 #define MTK_PDMA_INT_GRP1 0xa50
165 #define MTK_PDMA_INT_GRP2 0xa54
168 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04
169 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
173 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
174 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
175 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
176 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
177 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
178 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
179 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
180 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
183 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
184 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
185 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
188 #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
192 #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
195 #define MTK_QRX_BASE_PTR0 0x1900
198 #define MTK_QRX_MAX_CNT0 0x1904
201 #define MTK_QRX_CRX_IDX0 0x1908
204 #define MTK_QRX_DRX_IDX0 0x190C
207 #define MTK_QDMA_GLO_CFG 0x1A04
216 #define MTK_TX_DMA_EN BIT(0)
220 #define MTK_QDMA_RST_IDX 0x1A08
223 #define MTK_QDMA_DELAY_INT 0x1A0C
226 #define MTK_QDMA_FC_THRES 0x1A10
229 #define FC_THRES_MIN 0x4444
232 #define MTK_QDMA_INT_STATUS 0x1A18
242 #define MTK_TX_DONE_INT0 BIT(0)
247 #define MTK_QDMA_INT_GRP1 0x1a20
248 #define MTK_QDMA_INT_GRP2 0x1a24
249 #define MTK_RLS_DONE_INT BIT(0)
252 #define MTK_QDMA_INT_MASK 0x1A1C
255 #define MTK_QDMA_HRED2 0x1A44
258 #define MTK_QTX_CTX_PTR 0x1B00
261 #define MTK_QTX_DTX_PTR 0x1B04
264 #define MTK_QTX_CRX_PTR 0x1B10
267 #define MTK_QTX_DRX_PTR 0x1B14
270 #define MTK_QDMA_FQ_HEAD 0x1B20
273 #define MTK_QDMA_FQ_TAIL 0x1B24
276 #define MTK_QDMA_FQ_CNT 0x1B28
279 #define MTK_QDMA_FQ_BLEN 0x1B2C
282 #define MTK_GDM1_RX_GBCNT_L 0x2400
283 #define MTK_GDM1_RX_GBCNT_H 0x2404
284 #define MTK_GDM1_RX_GPCNT 0x2408
285 #define MTK_GDM1_RX_OERCNT 0x2410
286 #define MTK_GDM1_RX_FERCNT 0x2414
287 #define MTK_GDM1_RX_SERCNT 0x2418
288 #define MTK_GDM1_RX_LENCNT 0x241c
289 #define MTK_GDM1_RX_CERCNT 0x2420
290 #define MTK_GDM1_RX_FCCNT 0x2424
291 #define MTK_GDM1_TX_SKIPCNT 0x2428
292 #define MTK_GDM1_TX_COLCNT 0x242c
293 #define MTK_GDM1_TX_GBCNT_L 0x2430
294 #define MTK_GDM1_TX_GBCNT_H 0x2434
295 #define MTK_GDM1_TX_GPCNT 0x2438
296 #define MTK_STAT_OFFSET 0x40
299 #define TX_DMA_CHKSUM (0x7 << 29)
302 #define TX_DMA_FPORT_MASK 0x7
311 #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
321 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
322 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
326 #define RX_DMA_VID(_x) ((_x) & 0xfff)
329 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
338 #define RX_DMA_FPORT_MASK 0x7
342 #define MTK_PHY_IAC 0x10004
351 #define MTK_MAC_MISC 0x1000c
352 #define MTK_MUX_TO_ESW BIT(0)
355 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
358 #define MAC_MCR_MAX_RX_1518 0x0
359 #define MAC_MCR_MAX_RX_1536 0x1
360 #define MAC_MCR_MAX_RX_1552 0x2
361 #define MAC_MCR_MAX_RX_2048 0x3
373 #define MAC_MCR_FORCE_LINK BIT(0)
377 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
386 #define MAC_MSR_LINK BIT(0)
389 #define TRGMII_RCK_CTRL 0x10300
390 #define DQSI0(x) ((x << 0) & GENMASK(6, 0))
401 #define TRGMII_TCK_CTRL 0x10340
408 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
409 #define TD_DM_DRVP(x) ((x) & 0xf)
410 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
413 #define INTF_MODE 0x10390
414 #define TRGMII_INTF_DIS BIT(0)
418 #define INTF_MODE_RGMII_10_100 0
421 #define GPIO_OD33_CTRL8 0x4c0
422 #define GPIO_BIAS_CTRL 0xed0
423 #define GPIO_DRV_SEL10 0xf00
426 #define ETHSYS_CHIPID0_3 0x0
427 #define ETHSYS_CHIPID4_7 0x4
433 #define ETHSYS_SYSCFG 0x10
437 #define ETHSYS_SYSCFG0 0x14
438 #define SYSCFG0_GE_MASK 0x3
448 #define ETHSYS_CLKCFG0 0x2c
455 #define ETHSYS_RSTCTRL 0x34
461 #define SGMSYS_PCS_CONTROL_1 0x0
472 #define SGMSYS_PCS_LINK_TIMER 0x18
473 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
476 #define SGMSYS_SGMII_MODE 0x20
477 #define SGMII_IF_MODE_BIT0 BIT(0)
479 #define SGMII_SPEED_10 0x0
491 #define SGMSYS_ANA_RG_CS3 0x2028
493 #define RG_PHY_SPEED_1_25G 0x0
497 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
501 #define INFRA_MISC2 0x70c
502 #define CO_QPHY_SEL BIT(0)
506 #define MT7628_PDMA_OFFSET 0x0800
507 #define MT7628_SDM_OFFSET 0x0c00
509 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
510 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
511 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
512 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
513 #define MT7628_PST_DTX_IDX0 BIT(0)
515 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
516 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
519 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100)
520 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104)
521 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108)
522 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
523 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
574 MTK_TX_FLAGS_SINGLE0 = 0x01,
575 MTK_TX_FLAGS_PAGE0 = 0x02,
580 MTK_TX_FLAGS_FPORT0 = 0x04,
581 MTK_TX_FLAGS_FPORT1 = 0x08,
621 #define MT7621_CLKS_BITMAP (0)
622 #define MT7628_CLKS_BITMAP (0)
687 MTK_RX_FLAGS_NORMAL = 0,
713 MTK_RGMII_BIT = 0,
788 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
791 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
795 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
804 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
854 #define MTK_SGMII_PHYSPEED_MASK GENMASK(2, 0)
855 #define MTK_SGMII_PHYSPEED_1000 BIT(0)