74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)  in mvpp2_write()  function
420 	mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),  in mvpp2_bm_pool_create()
422 	mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);  in mvpp2_bm_pool_create()
439 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);  in mvpp2_bm_pool_create()
458 	mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);  in mvpp2_bm_pool_bufsize_set()
567 	mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);  in mvpp2_bm_pool_destroy()
614 	mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);  in mvpp23_bm_set_8pool_mode()
659 		mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);  in mvpp2_bm_init()
661 		mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);  in mvpp2_bm_init()
712 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);  in mvpp2_rxq_long_pool_set()
733 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);  in mvpp2_rxq_short_pool_set()
1367 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),  in mvpp2_interrupts_enable()
1378 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),  in mvpp2_interrupts_disable()
1386 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),  in mvpp2_qvec_interrupt_enable()
1394 	mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),  in mvpp2_qvec_interrupt_disable()
1862 	mvpp2_write(priv, MVPP2_CTRS_IDX, index);  in mvpp2_read_index()
2245 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,  in mvpp2_defaults_set()
2247 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);  in mvpp2_defaults_set()
2250 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);  in mvpp2_defaults_set()
2254 		mvpp2_write(port->priv,  in mvpp2_defaults_set()
2260 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,  in mvpp2_defaults_set()
2266 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);  in mvpp2_defaults_set()
2268 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);  in mvpp2_defaults_set()
2271 	mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),  in mvpp2_defaults_set()
2281 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_defaults_set()
2298 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_ingress_enable()
2311 		mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);  in mvpp2_ingress_disable()
2333 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);  in mvpp2_egress_enable()
2334 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);  in mvpp2_egress_enable()
2347 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);  in mvpp2_egress_disable()
2351 		mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,  in mvpp2_egress_disable()
2396 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);  in mvpp2_rxq_status_update()
2426 	mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);  in mvpp2_rxq_offset_set()
2644 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);  in mvpp2_txp_max_tx_size_set()
2650 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);  in mvpp2_txp_max_tx_size_set()
2659 		mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);  in mvpp2_txp_max_tx_size_set()
2671 			mvpp2_write(port->priv,  in mvpp2_txp_max_tx_size_set()
2684 	mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);  in mvpp2_set_rxq_free_tresh()
2689 	mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);  in mvpp2_set_rxq_free_tresh()
2761 	mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);  in mvpp2_rx_time_coal_set()
2777 	mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);  in mvpp2_tx_time_coal_set()
2906 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);  in mvpp2_aggr_txq_init()
2907 	mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),  in mvpp2_aggr_txq_init()
2934 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);  in mvpp2_rxq_init()
3053 	mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);  in mvpp2_rxq_deinit()
3111 	mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);  in mvpp2_txq_init()
3117 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);  in mvpp2_txq_init()
3120 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),  in mvpp2_txq_init()
3184 	mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);  in mvpp2_txq_deinit()
3254 	mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);  in mvpp2_cleanup_txqs()
3265 	mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);  in mvpp2_cleanup_txqs()
4483 		mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);  in mvpp2_poll()
5861 		mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),  in mvpp2_rx_irqs_setup()
5875 		mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);  in mvpp2_rx_irqs_setup()
5879 		mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);  in mvpp2_rx_irqs_setup()
7025 		mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);  in mvpp2_conf_mbus_windows()
7026 		mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);  in mvpp2_conf_mbus_windows()
7029 			mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);  in mvpp2_conf_mbus_windows()
7037 		mvpp2_write(priv, MVPP2_WIN_BASE(i),  in mvpp2_conf_mbus_windows()
7041 		mvpp2_write(priv, MVPP2_WIN_SIZE(i),  in mvpp2_conf_mbus_windows()
7047 	mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);  in mvpp2_conf_mbus_windows()
7056 		mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),  in mvpp2_rx_fifo_init()
7058 		mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),  in mvpp2_rx_fifo_init()
7062 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,  in mvpp2_rx_fifo_init()
7064 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);  in mvpp2_rx_fifo_init()
7071 	mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size);  in mvpp22_rx_fifo_set_hw()
7072 	mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);  in mvpp22_rx_fifo_set_hw()
7119 	mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,  in mvpp22_rx_fifo_init()
7121 	mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);  in mvpp22_rx_fifo_init()
7143 			mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);  in mvpp23_rx_fifo_fc_set_tresh()
7148 			mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);  in mvpp23_rx_fifo_fc_set_tresh()
7153 			mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);  in mvpp23_rx_fifo_fc_set_tresh()
7170 	mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);  in mvpp23_rx_fifo_fc_en()
7177 	mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);  in mvpp22_tx_fifo_set_hw()
7178 	mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);  in mvpp22_tx_fifo_set_hw()
7227 	mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);  in mvpp2_axi_init()
7242 	mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);  in mvpp2_axi_init()
7243 	mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);  in mvpp2_axi_init()
7246 	mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);  in mvpp2_axi_init()
7247 	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);  in mvpp2_axi_init()
7248 	mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);  in mvpp2_axi_init()
7249 	mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);  in mvpp2_axi_init()
7252 	mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);  in mvpp2_axi_init()
7253 	mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);  in mvpp2_axi_init()
7259 	mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);  in mvpp2_axi_init()
7260 	mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);  in mvpp2_axi_init()
7267 	mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);  in mvpp2_axi_init()
7274 	mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);  in mvpp2_axi_init()
7333 	mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);  in mvpp2_init()