Lines Matching +full:tcs +full:- +full:wait
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
12 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
20 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_dcb_sriov()
22 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_dcb_sriov()
25 u8 tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb_sriov() local
28 if (tcs <= 1) in ixgbe_cache_ring_dcb_sriov()
32 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_cache_ring_dcb_sriov()
35 /* start at VMDq register offset for SR-IOV enabled setups */ in ixgbe_cache_ring_dcb_sriov()
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
43 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
44 adapter->rx_ring[i]->netdev = pool ? NULL : adapter->netdev; in ixgbe_cache_ring_dcb_sriov()
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
51 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
52 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
57 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) in ixgbe_cache_ring_dcb_sriov()
61 if (fcoe->offset < tcs) in ixgbe_cache_ring_dcb_sriov()
65 if (fcoe->indices) { in ixgbe_cache_ring_dcb_sriov()
66 u16 queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
69 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; in ixgbe_cache_ring_dcb_sriov()
70 for (i = fcoe->offset; i < adapter->num_rx_queues; i++) { in ixgbe_cache_ring_dcb_sriov()
71 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; in ixgbe_cache_ring_dcb_sriov()
72 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
73 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_dcb_sriov()
77 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; in ixgbe_cache_ring_dcb_sriov()
78 for (i = fcoe->offset; i < adapter->num_tx_queues; i++) { in ixgbe_cache_ring_dcb_sriov()
79 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; in ixgbe_cache_ring_dcb_sriov()
80 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
89 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
93 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_get_first_reg_idx()
94 u8 num_tcs = adapter->hw_tcs; in ixgbe_get_first_reg_idx()
99 switch (hw->mac.type) { in ixgbe_get_first_reg_idx()
112 * TCs : TC0/1 TC2/3 TC4-7 in ixgbe_get_first_reg_idx()
125 * TCs : TC0 TC1 TC2/3 in ixgbe_get_first_reg_idx()
142 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
150 u8 num_tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb()
158 rss_i = adapter->ring_feature[RING_F_RSS].indices; in ixgbe_cache_ring_dcb()
163 adapter->tx_ring[offset + i]->reg_idx = tx_idx; in ixgbe_cache_ring_dcb()
164 adapter->rx_ring[offset + i]->reg_idx = rx_idx; in ixgbe_cache_ring_dcb()
165 adapter->rx_ring[offset + i]->netdev = adapter->netdev; in ixgbe_cache_ring_dcb()
166 adapter->tx_ring[offset + i]->dcb_tc = tc; in ixgbe_cache_ring_dcb()
167 adapter->rx_ring[offset + i]->dcb_tc = tc; in ixgbe_cache_ring_dcb()
176 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
179 * SR-IOV doesn't use any descriptor rings but changes the default if
186 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_sriov()
188 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_sriov()
189 struct ixgbe_ring_feature *rss = &adapter->ring_feature[RING_F_RSS]; in ixgbe_cache_ring_sriov()
194 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)) in ixgbe_cache_ring_sriov()
197 /* start at VMDq register offset for SR-IOV enabled setups */ in ixgbe_cache_ring_sriov()
199 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_sriov()
200 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
203 if (fcoe->offset && (i > fcoe->offset)) in ixgbe_cache_ring_sriov()
207 if ((reg_idx & ~vmdq->mask) >= rss->indices) { in ixgbe_cache_ring_sriov()
209 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_sriov()
211 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
212 adapter->rx_ring[i]->netdev = pool ? NULL : adapter->netdev; in ixgbe_cache_ring_sriov()
217 for (; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
218 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
219 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_sriov()
223 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_sriov()
224 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
227 if (fcoe->offset && (i > fcoe->offset)) in ixgbe_cache_ring_sriov()
231 if ((reg_idx & rss->mask) >= rss->indices) in ixgbe_cache_ring_sriov()
232 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_sriov()
233 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
238 for (; i < adapter->num_tx_queues; i++, reg_idx++) in ixgbe_cache_ring_sriov()
239 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
247 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
257 for (i = 0; i < adapter->num_rx_queues; i++) { in ixgbe_cache_ring_rss()
258 adapter->rx_ring[i]->reg_idx = i; in ixgbe_cache_ring_rss()
259 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_rss()
261 for (i = 0, reg_idx = 0; i < adapter->num_tx_queues; i++, reg_idx++) in ixgbe_cache_ring_rss()
262 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_rss()
263 for (i = 0; i < adapter->num_xdp_queues; i++, reg_idx++) in ixgbe_cache_ring_rss()
264 adapter->xdp_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_rss()
270 * ixgbe_cache_ring_register - Descriptor ring to register mapping
273 * Once we know the feature-set enabled for the device, we'll cache
283 adapter->rx_ring[0]->reg_idx = 0; in ixgbe_cache_ring_register()
284 adapter->tx_ring[0]->reg_idx = 0; in ixgbe_cache_ring_register()
302 return adapter->xdp_prog ? nr_cpu_ids : 0; in ixgbe_xdp_queues()
314 * ixgbe_set_dcb_sriov_queues: Allocate queues for SR-IOV devices w/ DCB
317 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
325 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; in ixgbe_set_dcb_sriov_queues()
330 u8 tcs = adapter->hw_tcs; in ixgbe_set_dcb_sriov_queues() local
333 if (tcs <= 1) in ixgbe_set_dcb_sriov_queues()
337 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_set_dcb_sriov_queues()
341 vmdq_i = min_t(u16, vmdq_i, MAX_TX_QUEUES / tcs); in ixgbe_set_dcb_sriov_queues()
344 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_dcb_sriov_queues()
347 if (tcs > 4) { in ixgbe_set_dcb_sriov_queues()
358 fcoe_i = (128 / __ALIGN_MASK(1, ~vmdq_m)) - vmdq_i; in ixgbe_set_dcb_sriov_queues()
362 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_dcb_sriov_queues()
365 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; in ixgbe_set_dcb_sriov_queues()
366 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; in ixgbe_set_dcb_sriov_queues()
372 adapter->ring_feature[RING_F_RSS].indices = 1; in ixgbe_set_dcb_sriov_queues()
373 adapter->ring_feature[RING_F_RSS].mask = IXGBE_RSS_DISABLED_MASK; in ixgbe_set_dcb_sriov_queues()
376 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_dcb_sriov_queues()
378 adapter->num_rx_pools = vmdq_i; in ixgbe_set_dcb_sriov_queues()
379 adapter->num_rx_queues_per_pool = tcs; in ixgbe_set_dcb_sriov_queues()
381 adapter->num_tx_queues = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
382 adapter->num_xdp_queues = 0; in ixgbe_set_dcb_sriov_queues()
383 adapter->num_rx_queues = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
386 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_dcb_sriov_queues()
389 fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_dcb_sriov_queues()
392 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_dcb_sriov_queues()
396 fcoe->indices = fcoe_i; in ixgbe_set_dcb_sriov_queues()
397 fcoe->offset = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
400 adapter->num_tx_queues += fcoe_i; in ixgbe_set_dcb_sriov_queues()
401 adapter->num_rx_queues += fcoe_i; in ixgbe_set_dcb_sriov_queues()
402 } else if (tcs > 1) { in ixgbe_set_dcb_sriov_queues()
404 fcoe->indices = 1; in ixgbe_set_dcb_sriov_queues()
405 fcoe->offset = ixgbe_fcoe_get_tc(adapter); in ixgbe_set_dcb_sriov_queues()
407 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; in ixgbe_set_dcb_sriov_queues()
409 fcoe->indices = 0; in ixgbe_set_dcb_sriov_queues()
410 fcoe->offset = 0; in ixgbe_set_dcb_sriov_queues()
416 for (i = 0; i < tcs; i++) in ixgbe_set_dcb_sriov_queues()
417 netdev_set_tc_queue(adapter->netdev, i, 1, i); in ixgbe_set_dcb_sriov_queues()
424 struct net_device *dev = adapter->netdev; in ixgbe_set_dcb_queues()
427 int tcs; in ixgbe_set_dcb_queues() local
430 tcs = adapter->hw_tcs; in ixgbe_set_dcb_queues()
433 if (tcs <= 1) in ixgbe_set_dcb_queues()
437 rss_i = dev->num_tx_queues / tcs; in ixgbe_set_dcb_queues()
438 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { in ixgbe_set_dcb_queues()
442 } else if (tcs > 4) { in ixgbe_set_dcb_queues()
453 f = &adapter->ring_feature[RING_F_RSS]; in ixgbe_set_dcb_queues()
454 rss_i = min_t(int, rss_i, f->limit); in ixgbe_set_dcb_queues()
455 f->indices = rss_i; in ixgbe_set_dcb_queues()
456 f->mask = rss_m; in ixgbe_set_dcb_queues()
458 /* disable ATR as it is not supported when multiple TCs are enabled */ in ixgbe_set_dcb_queues()
459 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_dcb_queues()
467 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_dcb_queues()
470 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_dcb_queues()
471 f->indices = min_t(u16, rss_i, f->limit); in ixgbe_set_dcb_queues()
472 f->offset = rss_i * tc; in ixgbe_set_dcb_queues()
476 for (i = 0; i < tcs; i++) in ixgbe_set_dcb_queues()
479 adapter->num_tx_queues = rss_i * tcs; in ixgbe_set_dcb_queues()
480 adapter->num_xdp_queues = 0; in ixgbe_set_dcb_queues()
481 adapter->num_rx_queues = rss_i * tcs; in ixgbe_set_dcb_queues()
488 * ixgbe_set_sriov_queues - Allocate queues for SR-IOV devices
491 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
498 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; in ixgbe_set_sriov_queues()
500 u16 rss_i = adapter->ring_feature[RING_F_RSS].limit; in ixgbe_set_sriov_queues()
506 /* only proceed if SR-IOV is enabled */ in ixgbe_set_sriov_queues()
507 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_set_sriov_queues()
514 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_sriov_queues()
534 fcoe_i = 128 - (vmdq_i * __ALIGN_MASK(1, ~vmdq_m)); in ixgbe_set_sriov_queues()
538 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_sriov_queues()
541 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; in ixgbe_set_sriov_queues()
542 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; in ixgbe_set_sriov_queues()
545 adapter->ring_feature[RING_F_RSS].indices = rss_i; in ixgbe_set_sriov_queues()
546 adapter->ring_feature[RING_F_RSS].mask = rss_m; in ixgbe_set_sriov_queues()
548 adapter->num_rx_pools = vmdq_i; in ixgbe_set_sriov_queues()
549 adapter->num_rx_queues_per_pool = rss_i; in ixgbe_set_sriov_queues()
551 adapter->num_rx_queues = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
552 adapter->num_tx_queues = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
553 adapter->num_xdp_queues = 0; in ixgbe_set_sriov_queues()
556 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_sriov_queues()
564 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_sriov_queues()
567 fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_sriov_queues()
570 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_sriov_queues()
574 fcoe->indices = fcoe_i; in ixgbe_set_sriov_queues()
575 fcoe->offset = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
580 /* limit indices to rss_i if MSI-X is disabled */ in ixgbe_set_sriov_queues()
581 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_set_sriov_queues()
585 fcoe->indices = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_sriov_queues()
586 fcoe->offset = fcoe_i - fcoe->indices; in ixgbe_set_sriov_queues()
588 fcoe_i -= rss_i; in ixgbe_set_sriov_queues()
592 adapter->num_tx_queues += fcoe_i; in ixgbe_set_sriov_queues()
593 adapter->num_rx_queues += fcoe_i; in ixgbe_set_sriov_queues()
603 netdev_set_num_tc(adapter->netdev, 1); in ixgbe_set_sriov_queues()
606 netdev_set_tc_queue(adapter->netdev, 0, in ixgbe_set_sriov_queues()
607 adapter->num_rx_queues_per_pool, 0); in ixgbe_set_sriov_queues()
613 * ixgbe_set_rss_queues - Allocate queues for RSS
622 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_set_rss_queues()
627 f = &adapter->ring_feature[RING_F_RSS]; in ixgbe_set_rss_queues()
628 rss_i = f->limit; in ixgbe_set_rss_queues()
630 f->indices = rss_i; in ixgbe_set_rss_queues()
632 if (hw->mac.type < ixgbe_mac_X550) in ixgbe_set_rss_queues()
633 f->mask = IXGBE_RSS_16Q_MASK; in ixgbe_set_rss_queues()
635 f->mask = IXGBE_RSS_64Q_MASK; in ixgbe_set_rss_queues()
638 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_rss_queues()
645 if (rss_i > 1 && adapter->atr_sample_rate) { in ixgbe_set_rss_queues()
646 f = &adapter->ring_feature[RING_F_FDIR]; in ixgbe_set_rss_queues()
648 rss_i = f->indices = f->limit; in ixgbe_set_rss_queues()
650 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) in ixgbe_set_rss_queues()
651 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_rss_queues()
663 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_rss_queues()
664 struct net_device *dev = adapter->netdev; in ixgbe_set_rss_queues()
667 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_rss_queues()
670 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus()); in ixgbe_set_rss_queues()
671 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues); in ixgbe_set_rss_queues()
673 /* limit indices to rss_i if MSI-X is disabled */ in ixgbe_set_rss_queues()
674 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_set_rss_queues()
678 f->indices = min_t(u16, fcoe_i, f->limit); in ixgbe_set_rss_queues()
679 f->offset = fcoe_i - f->indices; in ixgbe_set_rss_queues()
684 adapter->num_rx_queues = rss_i; in ixgbe_set_rss_queues()
685 adapter->num_tx_queues = rss_i; in ixgbe_set_rss_queues()
686 adapter->num_xdp_queues = ixgbe_xdp_queues(adapter); in ixgbe_set_rss_queues()
692 * ixgbe_set_num_queues - Allocate queues for device, feature dependent
705 adapter->num_rx_queues = 1; in ixgbe_set_num_queues()
706 adapter->num_tx_queues = 1; in ixgbe_set_num_queues()
707 adapter->num_xdp_queues = 0; in ixgbe_set_num_queues()
708 adapter->num_rx_pools = 1; in ixgbe_set_num_queues()
709 adapter->num_rx_queues_per_pool = 1; in ixgbe_set_num_queues()
726 * ixgbe_acquire_msix_vectors - acquire MSI-X vectors
729 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
730 * return a negative error code if unable to acquire MSI-X vectors for any
735 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_acquire_msix_vectors()
741 vectors = max(adapter->num_rx_queues, adapter->num_tx_queues); in ixgbe_acquire_msix_vectors()
742 vectors = max(vectors, adapter->num_xdp_queues); in ixgbe_acquire_msix_vectors()
744 /* It is easy to be greedy for MSI-X vectors. However, it really in ixgbe_acquire_msix_vectors()
751 /* Some vectors are necessary for non-queue interrupts */ in ixgbe_acquire_msix_vectors()
754 /* Hardware can only support a maximum of hw.mac->max_msix_vectors. in ixgbe_acquire_msix_vectors()
760 vectors = min_t(int, vectors, hw->mac.max_msix_vectors); in ixgbe_acquire_msix_vectors()
762 /* We want a minimum of two MSI-X vectors for (1) a TxQ[0] + RxQ[0] in ixgbe_acquire_msix_vectors()
767 adapter->msix_entries = kcalloc(vectors, in ixgbe_acquire_msix_vectors()
770 if (!adapter->msix_entries) in ixgbe_acquire_msix_vectors()
771 return -ENOMEM; in ixgbe_acquire_msix_vectors()
774 adapter->msix_entries[i].entry = i; in ixgbe_acquire_msix_vectors()
776 vectors = pci_enable_msix_range(adapter->pdev, adapter->msix_entries, in ixgbe_acquire_msix_vectors()
781 * acquiring within the specified range of MSI-X vectors in ixgbe_acquire_msix_vectors()
783 e_dev_warn("Failed to allocate MSI-X interrupts. Err: %d\n", in ixgbe_acquire_msix_vectors()
786 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; in ixgbe_acquire_msix_vectors()
787 kfree(adapter->msix_entries); in ixgbe_acquire_msix_vectors()
788 adapter->msix_entries = NULL; in ixgbe_acquire_msix_vectors()
796 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; in ixgbe_acquire_msix_vectors()
801 vectors -= NON_Q_VECTORS; in ixgbe_acquire_msix_vectors()
802 adapter->num_q_vectors = min_t(int, vectors, adapter->max_q_vectors); in ixgbe_acquire_msix_vectors()
810 ring->next = head->ring; in ixgbe_add_ring()
811 head->ring = ring; in ixgbe_add_ring()
812 head->count++; in ixgbe_add_ring()
813 head->next_update = jiffies + 1; in ixgbe_add_ring()
817 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
828 * We allocate one q_vector. If allocation fails we return -ENOMEM.
836 int node = dev_to_node(&adapter->pdev->dev); in ixgbe_alloc_q_vector()
839 int cpu = -1; in ixgbe_alloc_q_vector()
841 u8 tcs = adapter->hw_tcs; in ixgbe_alloc_q_vector() local
846 if ((tcs <= 1) && !(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { in ixgbe_alloc_q_vector()
847 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; in ixgbe_alloc_q_vector()
848 if (rss_i > 1 && adapter->atr_sample_rate) { in ixgbe_alloc_q_vector()
861 return -ENOMEM; in ixgbe_alloc_q_vector()
864 if (cpu != -1) in ixgbe_alloc_q_vector()
865 cpumask_set_cpu(cpu, &q_vector->affinity_mask); in ixgbe_alloc_q_vector()
866 q_vector->numa_node = node; in ixgbe_alloc_q_vector()
870 q_vector->cpu = -1; in ixgbe_alloc_q_vector()
874 netif_napi_add(adapter->netdev, &q_vector->napi, in ixgbe_alloc_q_vector()
878 adapter->q_vector[v_idx] = q_vector; in ixgbe_alloc_q_vector()
879 q_vector->adapter = adapter; in ixgbe_alloc_q_vector()
880 q_vector->v_idx = v_idx; in ixgbe_alloc_q_vector()
883 q_vector->tx.work_limit = adapter->tx_work_limit; in ixgbe_alloc_q_vector()
886 q_vector->tx.itr = IXGBE_ITR_ADAPTIVE_MAX_USECS | in ixgbe_alloc_q_vector()
888 q_vector->rx.itr = IXGBE_ITR_ADAPTIVE_MAX_USECS | in ixgbe_alloc_q_vector()
894 if (adapter->tx_itr_setting == 1) in ixgbe_alloc_q_vector()
895 q_vector->itr = IXGBE_12K_ITR; in ixgbe_alloc_q_vector()
897 q_vector->itr = adapter->tx_itr_setting; in ixgbe_alloc_q_vector()
900 if (adapter->rx_itr_setting == 1) in ixgbe_alloc_q_vector()
901 q_vector->itr = IXGBE_20K_ITR; in ixgbe_alloc_q_vector()
903 q_vector->itr = adapter->rx_itr_setting; in ixgbe_alloc_q_vector()
907 ring = q_vector->ring; in ixgbe_alloc_q_vector()
911 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
912 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
915 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
918 ixgbe_add_ring(ring, &q_vector->tx); in ixgbe_alloc_q_vector()
921 ring->count = adapter->tx_ring_count; in ixgbe_alloc_q_vector()
922 ring->queue_index = txr_idx; in ixgbe_alloc_q_vector()
925 WRITE_ONCE(adapter->tx_ring[txr_idx], ring); in ixgbe_alloc_q_vector()
928 txr_count--; in ixgbe_alloc_q_vector()
937 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
938 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
941 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
944 ixgbe_add_ring(ring, &q_vector->tx); in ixgbe_alloc_q_vector()
947 ring->count = adapter->tx_ring_count; in ixgbe_alloc_q_vector()
948 ring->queue_index = xdp_idx; in ixgbe_alloc_q_vector()
952 WRITE_ONCE(adapter->xdp_ring[xdp_idx], ring); in ixgbe_alloc_q_vector()
955 xdp_count--; in ixgbe_alloc_q_vector()
964 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
965 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
968 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
971 ixgbe_add_ring(ring, &q_vector->rx); in ixgbe_alloc_q_vector()
977 if (adapter->hw.mac.type == ixgbe_mac_82599EB) in ixgbe_alloc_q_vector()
978 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); in ixgbe_alloc_q_vector()
981 if (adapter->netdev->features & NETIF_F_FCOE_MTU) { in ixgbe_alloc_q_vector()
983 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_alloc_q_vector()
984 if ((rxr_idx >= f->offset) && in ixgbe_alloc_q_vector()
985 (rxr_idx < f->offset + f->indices)) in ixgbe_alloc_q_vector()
986 set_bit(__IXGBE_RX_FCOE, &ring->state); in ixgbe_alloc_q_vector()
991 ring->count = adapter->rx_ring_count; in ixgbe_alloc_q_vector()
992 ring->queue_index = rxr_idx; in ixgbe_alloc_q_vector()
995 WRITE_ONCE(adapter->rx_ring[rxr_idx], ring); in ixgbe_alloc_q_vector()
998 rxr_count--; in ixgbe_alloc_q_vector()
1009 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
1019 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; in ixgbe_free_q_vector()
1022 ixgbe_for_each_ring(ring, q_vector->tx) { in ixgbe_free_q_vector()
1024 WRITE_ONCE(adapter->xdp_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1026 WRITE_ONCE(adapter->tx_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1029 ixgbe_for_each_ring(ring, q_vector->rx) in ixgbe_free_q_vector()
1030 WRITE_ONCE(adapter->rx_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1032 adapter->q_vector[v_idx] = NULL; in ixgbe_free_q_vector()
1033 __netif_napi_del(&q_vector->napi); in ixgbe_free_q_vector()
1038 * we must wait a grace period before freeing it. in ixgbe_free_q_vector()
1044 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
1048 * return -ENOMEM.
1052 int q_vectors = adapter->num_q_vectors; in ixgbe_alloc_q_vectors()
1053 int rxr_remaining = adapter->num_rx_queues; in ixgbe_alloc_q_vectors()
1054 int txr_remaining = adapter->num_tx_queues; in ixgbe_alloc_q_vectors()
1055 int xdp_remaining = adapter->num_xdp_queues; in ixgbe_alloc_q_vectors()
1059 /* only one q_vector if MSI-X is disabled. */ in ixgbe_alloc_q_vectors()
1060 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_alloc_q_vectors()
1072 rxr_remaining--; in ixgbe_alloc_q_vectors()
1078 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1079 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1080 int xqpv = DIV_ROUND_UP(xdp_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1091 rxr_remaining -= rqpv; in ixgbe_alloc_q_vectors()
1092 txr_remaining -= tqpv; in ixgbe_alloc_q_vectors()
1093 xdp_remaining -= xqpv; in ixgbe_alloc_q_vectors()
1099 for (i = 0; i < adapter->num_rx_queues; i++) { in ixgbe_alloc_q_vectors()
1100 if (adapter->rx_ring[i]) in ixgbe_alloc_q_vectors()
1101 adapter->rx_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1104 for (i = 0; i < adapter->num_tx_queues; i++) { in ixgbe_alloc_q_vectors()
1105 if (adapter->tx_ring[i]) in ixgbe_alloc_q_vectors()
1106 adapter->tx_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1109 for (i = 0; i < adapter->num_xdp_queues; i++) { in ixgbe_alloc_q_vectors()
1110 if (adapter->xdp_ring[i]) in ixgbe_alloc_q_vectors()
1111 adapter->xdp_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1117 adapter->num_tx_queues = 0; in ixgbe_alloc_q_vectors()
1118 adapter->num_xdp_queues = 0; in ixgbe_alloc_q_vectors()
1119 adapter->num_rx_queues = 0; in ixgbe_alloc_q_vectors()
1120 adapter->num_q_vectors = 0; in ixgbe_alloc_q_vectors()
1122 while (v_idx--) in ixgbe_alloc_q_vectors()
1125 return -ENOMEM; in ixgbe_alloc_q_vectors()
1129 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
1138 int v_idx = adapter->num_q_vectors; in ixgbe_free_q_vectors()
1140 adapter->num_tx_queues = 0; in ixgbe_free_q_vectors()
1141 adapter->num_xdp_queues = 0; in ixgbe_free_q_vectors()
1142 adapter->num_rx_queues = 0; in ixgbe_free_q_vectors()
1143 adapter->num_q_vectors = 0; in ixgbe_free_q_vectors()
1145 while (v_idx--) in ixgbe_free_q_vectors()
1151 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { in ixgbe_reset_interrupt_capability()
1152 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; in ixgbe_reset_interrupt_capability()
1153 pci_disable_msix(adapter->pdev); in ixgbe_reset_interrupt_capability()
1154 kfree(adapter->msix_entries); in ixgbe_reset_interrupt_capability()
1155 adapter->msix_entries = NULL; in ixgbe_reset_interrupt_capability()
1156 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { in ixgbe_reset_interrupt_capability()
1157 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; in ixgbe_reset_interrupt_capability()
1158 pci_disable_msi(adapter->pdev); in ixgbe_reset_interrupt_capability()
1163 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
1173 /* We will try to get MSI-X interrupts first */ in ixgbe_set_interrupt_capability()
1177 /* At this point, we do not have MSI-X capabilities. We need to in ixgbe_set_interrupt_capability()
1178 * reconfigure or disable various features which require MSI-X in ixgbe_set_interrupt_capability()
1183 if (adapter->hw_tcs > 1) { in ixgbe_set_interrupt_capability()
1184 e_dev_warn("Number of DCB TCs exceeds number of available queues. Disabling DCB support.\n"); in ixgbe_set_interrupt_capability()
1185 netdev_reset_tc(adapter->netdev); in ixgbe_set_interrupt_capability()
1187 if (adapter->hw.mac.type == ixgbe_mac_82598EB) in ixgbe_set_interrupt_capability()
1188 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; in ixgbe_set_interrupt_capability()
1190 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; in ixgbe_set_interrupt_capability()
1191 adapter->temp_dcb_cfg.pfc_mode_enable = false; in ixgbe_set_interrupt_capability()
1192 adapter->dcb_cfg.pfc_mode_enable = false; in ixgbe_set_interrupt_capability()
1195 adapter->hw_tcs = 0; in ixgbe_set_interrupt_capability()
1196 adapter->dcb_cfg.num_tcs.pg_tcs = 1; in ixgbe_set_interrupt_capability()
1197 adapter->dcb_cfg.num_tcs.pfc_tcs = 1; in ixgbe_set_interrupt_capability()
1199 /* Disable SR-IOV support */ in ixgbe_set_interrupt_capability()
1200 e_dev_warn("Disabling SR-IOV support\n"); in ixgbe_set_interrupt_capability()
1205 adapter->ring_feature[RING_F_RSS].limit = 1; in ixgbe_set_interrupt_capability()
1211 adapter->num_q_vectors = 1; in ixgbe_set_interrupt_capability()
1213 err = pci_enable_msi(adapter->pdev); in ixgbe_set_interrupt_capability()
1218 adapter->flags |= IXGBE_FLAG_MSI_ENABLED; in ixgbe_set_interrupt_capability()
1222 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
1226 * - Kernel support (MSI, MSI-X)
1227 * - which can be user-defined (via MODULE_PARAM)
1228 * - Hardware queue count (num_*_queues)
1229 * - defined by miscellaneous hardware support/features (RSS, etc.)
1250 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", in ixgbe_init_interrupt_scheme()
1251 adapter->num_rx_queues, adapter->num_tx_queues, in ixgbe_init_interrupt_scheme()
1252 adapter->num_xdp_queues); in ixgbe_init_interrupt_scheme()
1254 set_bit(__IXGBE_DOWN, &adapter->state); in ixgbe_init_interrupt_scheme()
1264 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
1268 * to pre-load conditions
1272 adapter->num_tx_queues = 0; in ixgbe_clear_interrupt_scheme()
1273 adapter->num_xdp_queues = 0; in ixgbe_clear_interrupt_scheme()
1274 adapter->num_rx_queues = 0; in ixgbe_clear_interrupt_scheme()
1284 u16 i = tx_ring->next_to_use; in ixgbe_tx_ctxtdesc()
1289 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; in ixgbe_tx_ctxtdesc()
1294 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); in ixgbe_tx_ctxtdesc()
1295 context_desc->fceof_saidx = cpu_to_le32(fceof_saidx); in ixgbe_tx_ctxtdesc()
1296 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); in ixgbe_tx_ctxtdesc()
1297 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); in ixgbe_tx_ctxtdesc()