Lines Matching +full:10 +full:gbase +full:- +full:kr
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
65 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599()
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
72 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
74 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
78 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
79 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
83 if (hw->phy.multispeed_fiber) { in ixgbe_init_mac_link_ops_82599()
85 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
86 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; in ixgbe_init_mac_link_ops_82599()
87 mac->ops.set_rate_select_speed = in ixgbe_init_mac_link_ops_82599()
90 if ((mac->ops.get_media_type(hw) == in ixgbe_init_mac_link_ops_82599()
92 (hw->phy.smart_speed == ixgbe_smart_speed_auto || in ixgbe_init_mac_link_ops_82599()
93 hw->phy.smart_speed == ixgbe_smart_speed_on) && in ixgbe_init_mac_link_ops_82599()
95 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; in ixgbe_init_mac_link_ops_82599()
97 mac->ops.setup_link = &ixgbe_setup_mac_link_82599; in ixgbe_init_mac_link_ops_82599()
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { in ixgbe_setup_sfp_modules_82599()
109 hw->phy.ops.reset = NULL; in ixgbe_setup_sfp_modules_82599()
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in ixgbe_setup_sfp_modules_82599()
122 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) in ixgbe_setup_sfp_modules_82599()
127 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) in ixgbe_setup_sfp_modules_82599()
132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_setup_sfp_modules_82599()
137 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_setup_sfp_modules_82599()
138 hw->eeprom.semaphore_delay * 2000); in ixgbe_setup_sfp_modules_82599()
141 ret_val = hw->mac.ops.prot_autoc_write(hw, in ixgbe_setup_sfp_modules_82599()
142 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, in ixgbe_setup_sfp_modules_82599()
155 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_setup_sfp_modules_82599()
159 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_setup_sfp_modules_82599()
160 hw->eeprom.semaphore_delay * 2000); in ixgbe_setup_sfp_modules_82599()
166 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
171 * For this part (82599) we need to wrap read-modify-writes with a possible
184 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in prot_autoc_read_82599()
197 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
215 * - We didn't do it already (in the read part of a read-modify-write) in prot_autoc_write_82599()
216 * - LESM is enabled. in prot_autoc_write_82599()
219 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in prot_autoc_write_82599()
235 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in prot_autoc_write_82599()
242 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_82599()
246 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; in ixgbe_get_invariants_82599()
247 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; in ixgbe_get_invariants_82599()
248 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; in ixgbe_get_invariants_82599()
249 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; in ixgbe_get_invariants_82599()
250 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; in ixgbe_get_invariants_82599()
251 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; in ixgbe_get_invariants_82599()
252 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); in ixgbe_get_invariants_82599()
258 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
268 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_phy_ops_82599()
269 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82599()
273 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { in ixgbe_init_phy_ops_82599()
275 hw->phy.qsfp_shared_i2c_bus = true; in ixgbe_init_phy_ops_82599()
287 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
288 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
292 ret_val = phy->ops.identify(hw); in ixgbe_init_phy_ops_82599()
298 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { in ixgbe_init_phy_ops_82599()
299 mac->ops.setup_link = &ixgbe_setup_copper_link_82599; in ixgbe_init_phy_ops_82599()
300 mac->ops.get_link_capabilities = in ixgbe_init_phy_ops_82599()
305 switch (hw->phy.type) { in ixgbe_init_phy_ops_82599()
307 phy->ops.check_link = &ixgbe_check_phy_link_tnx; in ixgbe_init_phy_ops_82599()
308 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; in ixgbe_init_phy_ops_82599()
318 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
332 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || in ixgbe_get_link_capabilities_82599()
333 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || in ixgbe_get_link_capabilities_82599()
334 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || in ixgbe_get_link_capabilities_82599()
335 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || in ixgbe_get_link_capabilities_82599()
336 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || in ixgbe_get_link_capabilities_82599()
337 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { in ixgbe_get_link_capabilities_82599()
348 if (hw->mac.orig_link_settings_stored) in ixgbe_get_link_capabilities_82599()
349 autoc = hw->mac.orig_autoc; in ixgbe_get_link_capabilities_82599()
406 if (hw->phy.multispeed_fiber) { in ixgbe_get_link_capabilities_82599()
410 /* QSFP must not enable auto-negotiation */ in ixgbe_get_link_capabilities_82599()
411 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) in ixgbe_get_link_capabilities_82599()
421 * ixgbe_get_media_type_82599 - Get media type
429 switch (hw->phy.type) { in ixgbe_get_media_type_82599()
438 switch (hw->device_id) { in ixgbe_get_media_type_82599()
474 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
485 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); in ixgbe_stop_mac_link_on_d3_82599()
487 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && in ixgbe_stop_mac_link_on_d3_82599()
496 * ixgbe_start_mac_link_82599 - Setup MAC link settings
513 status = hw->mac.ops.acquire_swfw_sync(hw, in ixgbe_start_mac_link_82599()
525 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_start_mac_link_82599()
557 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
580 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
599 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
605 * so, we set the speed then disable and re-enable the tx laser, to
616 if (hw->mac.autotry_restart) { in ixgbe_flap_tx_laser_multispeed_fiber()
619 hw->mac.autotry_restart = false; in ixgbe_flap_tx_laser_multispeed_fiber()
624 * ixgbe_set_hard_rate_select_speed - Set module link speed
653 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
671 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_smartspeed()
674 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_smartspeed()
677 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_smartspeed()
680 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; in ixgbe_setup_mac_link_smartspeed()
690 hw->phy.smart_speed_active = false; in ixgbe_setup_mac_link_smartspeed()
699 * Section 73.10.2, we may have to wait up to 500ms if KR is in ixgbe_setup_mac_link_smartspeed()
707 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_smartspeed()
718 * We didn't get link. If we advertised KR plus one of KX4/KX in ixgbe_setup_mac_link_smartspeed()
719 * (or BX4/BX), then disable KR and try again. in ixgbe_setup_mac_link_smartspeed()
725 /* Turn SmartSpeed on to disable KR support */ in ixgbe_setup_mac_link_smartspeed()
726 hw->phy.smart_speed_active = true; in ixgbe_setup_mac_link_smartspeed()
735 * parallel detect, both 10g and 1g. This allows for the maximum in ixgbe_setup_mac_link_smartspeed()
736 * connect attempts as defined in the AN MAS table 73-7. in ixgbe_setup_mac_link_smartspeed()
742 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_smartspeed()
752 hw->phy.smart_speed_active = false; in ixgbe_setup_mac_link_smartspeed()
763 * ixgbe_setup_mac_link_82599 - Set MAC link speed
789 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, in ixgbe_setup_mac_link_82599()
799 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ in ixgbe_setup_mac_link_82599()
800 if (hw->mac.orig_link_settings_stored) in ixgbe_setup_mac_link_82599()
801 orig_autoc = hw->mac.orig_autoc; in ixgbe_setup_mac_link_82599()
811 /* Set KX4/KX/KR support according to speed requested */ in ixgbe_setup_mac_link_82599()
817 (hw->phy.smart_speed_active == false)) in ixgbe_setup_mac_link_82599()
825 /* Switch from 1G SFI to 10G SFI if requested */ in ixgbe_setup_mac_link_82599()
833 /* Switch from 10G SFI to 1G SFI if requested */ in ixgbe_setup_mac_link_82599()
846 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); in ixgbe_setup_mac_link_82599()
879 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
893 status = hw->phy.ops.setup_link_speed(hw, speed, in ixgbe_setup_copper_link_82599()
902 * ixgbe_reset_hw_82599 - Perform hardware reset
918 status = hw->mac.ops.stop_adapter(hw); in ixgbe_reset_hw_82599()
928 status = hw->phy.ops.init(hw); in ixgbe_reset_hw_82599()
934 if (hw->phy.sfp_setup_needed) { in ixgbe_reset_hw_82599()
935 status = hw->mac.ops.setup_sfp(hw); in ixgbe_reset_hw_82599()
936 hw->phy.sfp_setup_needed = false; in ixgbe_reset_hw_82599()
943 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) in ixgbe_reset_hw_82599()
944 hw->phy.ops.reset(hw); in ixgbe_reset_hw_82599()
957 if (!hw->force_full_reset) { in ixgbe_reset_hw_82599()
958 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); in ixgbe_reset_hw_82599()
968 /* Poll for reset bit to self-clear indicating reset is complete */ in ixgbe_reset_hw_82599()
969 for (i = 0; i < 10; i++) { in ixgbe_reset_hw_82599()
988 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { in ixgbe_reset_hw_82599()
989 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_reset_hw_82599()
1008 if (hw->mac.orig_link_settings_stored == false) { in ixgbe_reset_hw_82599()
1009 hw->mac.orig_autoc = autoc; in ixgbe_reset_hw_82599()
1010 hw->mac.orig_autoc2 = autoc2; in ixgbe_reset_hw_82599()
1011 hw->mac.orig_link_settings_stored = true; in ixgbe_reset_hw_82599()
1014 /* If MNG FW is running on a multi-speed device that in ixgbe_reset_hw_82599()
1020 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || in ixgbe_reset_hw_82599()
1021 hw->wol_enabled) in ixgbe_reset_hw_82599()
1022 hw->mac.orig_autoc = in ixgbe_reset_hw_82599()
1023 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | in ixgbe_reset_hw_82599()
1026 if (autoc != hw->mac.orig_autoc) { in ixgbe_reset_hw_82599()
1027 status = hw->mac.ops.prot_autoc_write(hw, in ixgbe_reset_hw_82599()
1028 hw->mac.orig_autoc, in ixgbe_reset_hw_82599()
1035 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { in ixgbe_reset_hw_82599()
1037 autoc2 |= (hw->mac.orig_autoc2 & in ixgbe_reset_hw_82599()
1044 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_82599()
1051 hw->mac.num_rar_entries = IXGBE_82599_RAR_ENTRIES; in ixgbe_reset_hw_82599()
1052 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_82599()
1055 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); in ixgbe_reset_hw_82599()
1058 if (is_valid_ether_addr(hw->mac.san_addr)) { in ixgbe_reset_hw_82599()
1060 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; in ixgbe_reset_hw_82599()
1062 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_82599()
1063 hw->mac.san_addr, 0, IXGBE_RAH_AV); in ixgbe_reset_hw_82599()
1066 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_82599()
1070 hw->mac.num_rar_entries--; in ixgbe_reset_hw_82599()
1074 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, in ixgbe_reset_hw_82599()
1075 &hw->mac.wwpn_prefix); in ixgbe_reset_hw_82599()
1081 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1093 udelay(10); in ixgbe_fdir_check_cmd_complete()
1100 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1118 …hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n"); in ixgbe_reinit_fdir_tables_82599()
1127 * before re-writing the FDIRCTRL control register with the same value. in ixgbe_reinit_fdir_tables_82599()
1128 * - write 1 to bit 8 of FDIRCMD register & in ixgbe_reinit_fdir_tables_82599()
1129 * - write 0 to bit 8 of FDIRCMD register in ixgbe_reinit_fdir_tables_82599()
1149 /* Poll init-done after we write FDIRCTRL register */ in ixgbe_reinit_fdir_tables_82599()
1172 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1185 * Poll init-done after we write the register. Estimated times: in ixgbe_fdir_enable_82599()
1186 * 10G: PBALLOC = 11b, timing is 60us in ixgbe_fdir_enable_82599()
1211 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1220 * Move the flexible bytes to use the ethertype - shift 6 words in ixgbe_init_fdir_signature_82599()
1235 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1246 * Move the flexible bytes to use the ethertype - shift 6 words in ixgbe_init_fdir_perfect_82599()
1277 sig_hash ^= lo_hash_dword << (16 - n); \
1283 sig_hash ^= hi_hash_dword << (16 - n); \
1287 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1335 IXGBE_COMPUTE_SIG_HASH_ITERATION(10); in ixgbe_atr_compute_sig_hash_82599()
1354 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter
1379 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); in ixgbe_fdir_add_signature_filter_82599()
1402 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits in ixgbe_fdir_add_signature_filter_82599()
1403 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. in ixgbe_fdir_add_signature_filter_82599()
1424 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1444 for (i = 0; i <= 10; i++) in ixgbe_atr_compute_perfect_hash_82599()
1445 input->dword_stream[i] &= input_mask->dword_stream[i]; in ixgbe_atr_compute_perfect_hash_82599()
1448 flow_vm_vlan = ntohl(input->dword_stream[0]); in ixgbe_atr_compute_perfect_hash_82599()
1451 for (i = 1; i <= 10; i++) in ixgbe_atr_compute_perfect_hash_82599()
1452 hi_dword ^= input->dword_stream[i]; in ixgbe_atr_compute_perfect_hash_82599()
1479 input->formatted.bkt_hash = (__force __be16)(bucket_hash & 0x1FFF); in ixgbe_atr_compute_perfect_hash_82599()
1483 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1493 u32 mask = ntohs(input_mask->formatted.dst_port); in ixgbe_get_fdirtcpm_82599()
1496 mask |= ntohs(input_mask->formatted.src_port); in ixgbe_get_fdirtcpm_82599()
1505 * that are either all or in part big-endian. As a result on big-endian
1506 * systems we will end up byte swapping the value to little-endian before
1508 * big-endian format.
1537 if (input_mask->formatted.bkt_hash) in ixgbe_fdir_set_input_mask_82599()
1541 switch (input_mask->formatted.vm_pool & 0x7F) { in ixgbe_fdir_set_input_mask_82599()
1552 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { in ixgbe_fdir_set_input_mask_82599()
1555 if (input_mask->formatted.dst_port || in ixgbe_fdir_set_input_mask_82599()
1556 input_mask->formatted.src_port) { in ixgbe_fdir_set_input_mask_82599()
1568 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) { in ixgbe_fdir_set_input_mask_82599()
1589 switch ((__force u16)input_mask->formatted.flex_bytes & 0xFFFF) { in ixgbe_fdir_set_input_mask_82599()
1601 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ in ixgbe_fdir_set_input_mask_82599()
1612 switch (hw->mac.type) { in ixgbe_fdir_set_input_mask_82599()
1622 /* store source and destination IP masks (big-enian) */ in ixgbe_fdir_set_input_mask_82599()
1624 ~input_mask->formatted.src_ip[0]); in ixgbe_fdir_set_input_mask_82599()
1626 ~input_mask->formatted.dst_ip[0]); in ixgbe_fdir_set_input_mask_82599()
1640 input->formatted.src_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1642 input->formatted.src_ip[1]); in ixgbe_fdir_write_perfect_filter_82599()
1644 input->formatted.src_ip[2]); in ixgbe_fdir_write_perfect_filter_82599()
1646 /* record the source address (big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1647 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1649 /* record the first 32 bits of the destination address (big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1652 /* record source and destination port (little-endian)*/ in ixgbe_fdir_write_perfect_filter_82599()
1653 fdirport = be16_to_cpu(input->formatted.dst_port); in ixgbe_fdir_write_perfect_filter_82599()
1655 fdirport |= be16_to_cpu(input->formatted.src_port); in ixgbe_fdir_write_perfect_filter_82599()
1658 /* record vlan (little-endian) and flex_bytes(big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1659 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); in ixgbe_fdir_write_perfect_filter_82599()
1661 fdirvlan |= ntohs(input->formatted.vlan_id); in ixgbe_fdir_write_perfect_filter_82599()
1665 fdirhash = (__force u32)input->formatted.bkt_hash; in ixgbe_fdir_write_perfect_filter_82599()
1680 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; in ixgbe_fdir_write_perfect_filter_82599()
1682 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; in ixgbe_fdir_write_perfect_filter_82599()
1703 fdirhash = (__force u32)input->formatted.bkt_hash; in ixgbe_fdir_erase_perfect_filter_82599()
1731 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1745 udelay(10); in ixgbe_read_analog_reg8_82599()
1753 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1767 udelay(10); in ixgbe_write_analog_reg8_82599()
1773 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1778 * Then performs revision-specific operations, if any.
1793 hw->mac.autotry_restart = true; in ixgbe_start_hw_82599()
1799 * ixgbe_identify_phy_82599 - Get physical layer module
1810 /* Detect PHY if not unknown - returns success if already detected. */ in ixgbe_identify_phy_82599()
1813 /* 82599 10GBASE-T requires an external PHY */ in ixgbe_identify_phy_82599()
1814 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) in ixgbe_identify_phy_82599()
1820 if (hw->phy.type == ixgbe_phy_unknown) { in ixgbe_identify_phy_82599()
1821 hw->phy.type = ixgbe_phy_none; in ixgbe_identify_phy_82599()
1826 if (hw->phy.type == ixgbe_phy_sfp_unsupported) in ixgbe_identify_phy_82599()
1833 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1847 hw->mac.ops.disable_rx_buff(hw); in ixgbe_enable_rx_dma_82599()
1850 hw->mac.ops.enable_rx(hw); in ixgbe_enable_rx_dma_82599()
1852 hw->mac.ops.disable_rx(hw); in ixgbe_enable_rx_dma_82599()
1854 hw->mac.ops.enable_rx_buff(hw); in ixgbe_enable_rx_dma_82599()
1860 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1877 if (hw->phy.media_type != ixgbe_media_type_fiber) in ixgbe_verify_fw_version_82599()
1882 if (hw->eeprom.ops.read(hw, offset, &fw_offset)) in ixgbe_verify_fw_version_82599()
1890 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset)) in ixgbe_verify_fw_version_82599()
1898 if (hw->eeprom.ops.read(hw, offset, &fw_version)) in ixgbe_verify_fw_version_82599()
1912 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1924 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); in ixgbe_verify_lesm_fw_enabled_82599()
1930 status = hw->eeprom.ops.read(hw, (fw_offset + in ixgbe_verify_lesm_fw_enabled_82599()
1939 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + in ixgbe_verify_lesm_fw_enabled_82599()
1950 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
1963 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_read_eeprom_buffer_82599()
1968 if (eeprom->type == ixgbe_eeprom_spi && in ixgbe_read_eeprom_buffer_82599()
1969 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR) in ixgbe_read_eeprom_buffer_82599()
1977 * ixgbe_read_eeprom_82599 - Read EEPROM word using
1989 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_read_eeprom_82599()
1995 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR) in ixgbe_read_eeprom_82599()
2002 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2007 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2032 for (i = 0; i < 10; i++) { in ixgbe_reset_pipeline_82599()
2056 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2072 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_read_i2c_byte_82599()
2085 timeout--; in ixgbe_read_i2c_byte_82599()
2098 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_read_i2c_byte_82599()
2110 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2126 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_write_i2c_byte_82599()
2139 timeout--; in ixgbe_write_i2c_byte_82599()
2152 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_write_i2c_byte_82599()