Lines Matching +full:0 +full:xffffff7f
36 module_param(debug, int, 0);
37 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 {E1000_RDLEN(0), "RDLEN"},
74 {E1000_RDH(0), "RDH"},
75 {E1000_RDT(0), "RDT"},
77 {E1000_RXDCTL(0), "RXDCTL"},
79 {E1000_RDBAL(0), "RDBAL"},
80 {E1000_RDBAH(0), "RDBAH"},
89 {E1000_TDBAL(0), "TDBAL"},
90 {E1000_TDBAH(0), "TDBAH"},
91 {E1000_TDLEN(0), "TDLEN"},
92 {E1000_TDH(0), "TDH"},
93 {E1000_TDT(0), "TDT"},
95 {E1000_TXDCTL(0), "TXDCTL"},
97 {E1000_TARC(0), "TARC"},
105 {0, NULL}
143 int n = 0; in e1000_regdump()
148 case E1000_RXDCTL(0): in e1000_regdump()
149 for (n = 0; n < 2; n++) in e1000_regdump()
152 case E1000_TXDCTL(0): in e1000_regdump()
153 for (n = 0; n < 2; n++) in e1000_regdump()
156 case E1000_TARC(0): in e1000_regdump()
157 for (n = 0; n < 2; n++) in e1000_regdump()
166 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); in e1000_regdump()
167 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); in e1000_regdump()
176 for (i = 0; i < adapter->rx_ps_pages; i++) { in e1000e_dump_ps_pages()
214 int i = 0; in e1000e_dump()
243 0, tx_ring->next_to_use, tx_ring->next_to_clean, in e1000e_dump()
255 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) in e1000e_dump()
259 * 0 | Buffer Address [63:0] (Reserved on Write Back) | in e1000e_dump()
263 * 63 48 47 36 35 32 31 24 23 16 15 0 in e1000e_dump()
265 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload in e1000e_dump()
266 * 63 48 47 40 39 32 31 16 15 8 7 0 in e1000e_dump()
268 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | in e1000e_dump()
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 in e1000e_dump()
274 * Extended Data Descriptor (DTYP=0x1) in e1000e_dump()
276 * 0 | Buffer Address [63:0] | in e1000e_dump()
280 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 in e1000e_dump()
282 …pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp … in e1000e_dump()
284 …pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp … in e1000e_dump()
285 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { in e1000e_dump()
298 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", in e1000e_dump()
320 0, rx_ring->next_to_use, rx_ring->next_to_clean); in e1000e_dump()
334 * 0 | Buffer Address 0 [63:0] | in e1000e_dump()
336 * 8 | Buffer Address 1 [63:0] | in e1000e_dump()
338 * 16 | Buffer Address 2 [63:0] | in e1000e_dump()
340 * 24 | Buffer Address 3 [63:0] | in e1000e_dump()
343 …pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->d… in e1000e_dump()
346 * 63 48 47 32 31 13 12 8 7 4 3 0 in e1000e_dump()
348 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | in e1000e_dump()
353 * 63 48 47 32 31 20 19 0 in e1000e_dump()
356 for (i = 0; i < rx_ring->count; i++) { in e1000e_dump()
373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", in e1000e_dump()
381 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", in e1000e_dump()
397 case 0: in e1000e_dump()
401 * 0 | Buffer Address [63:0] | in e1000e_dump()
406 …pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read… in e1000e_dump()
409 * 63 48 47 32 31 24 23 4 3 0 in e1000e_dump()
412 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | in e1000e_dump()
418 * 63 48 47 32 31 20 19 0 in e1000e_dump()
422 for (i = 0; i < rx_ring->count; i++) { in e1000e_dump()
439 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", in e1000e_dump()
445 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", in e1000e_dump()
502 memset(hwtstamps, 0, sizeof(*hwtstamps)); in e1000e_systim_to_hwtstamp()
661 skb_trim(skb, 0); in e1000_alloc_rx_buffers()
700 i = 0; in e1000_alloc_rx_buffers()
731 for (j = 0; j < PS_PAGE_BUFFERS; j++) { in e1000_alloc_rx_buffers_ps()
736 ~cpu_to_le64(0); in e1000_alloc_rx_buffers_ps()
747 0, PAGE_SIZE, in e1000_alloc_rx_buffers_ps()
786 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); in e1000_alloc_rx_buffers_ps()
803 i = 0; in e1000_alloc_rx_buffers_ps()
836 skb_trim(skb, 0); in e1000_alloc_jumbo_rx_buffers()
860 buffer_info->page, 0, in e1000_alloc_jumbo_rx_buffers()
873 i = 0; in e1000_alloc_jumbo_rx_buffers()
879 if (unlikely(i-- == 0)) in e1000_alloc_jumbo_rx_buffers()
922 int cleaned_count = 0; in e1000_clean_rx_irq()
924 unsigned int total_rx_bytes = 0, total_rx_packets = 0; in e1000_clean_rx_irq()
946 i = 0; in e1000_clean_rx_irq()
956 buffer_info->dma = 0; in e1000_clean_rx_irq()
1033 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); in e1000_clean_rx_irq()
1039 cleaned_count = 0; in e1000_clean_rx_irq()
1072 buffer_info->dma = 0; in e1000_put_txbuf()
1081 buffer_info->time_stamp = 0; in e1000_put_txbuf()
1119 if (er32(TDH(0)) == er32(TDT(0))) { in e1000_print_hw_hang()
1220 unsigned int count = 0; in e1000_clean_tx_irq()
1221 unsigned int total_tx_bytes = 0, total_tx_packets = 0; in e1000_clean_tx_irq()
1222 unsigned int bytes_compl = 0, pkts_compl = 0; in e1000_clean_tx_irq()
1248 tx_desc->upper.data = 0; in e1000_clean_tx_irq()
1252 i = 0; in e1000_clean_tx_irq()
1320 int cleaned_count = 0; in e1000_clean_rx_irq_ps()
1322 unsigned int total_rx_bytes = 0, total_rx_packets = 0; in e1000_clean_rx_irq_ps()
1341 i = 0; in e1000_clean_rx_irq_ps()
1351 buffer_info->dma = 0; in e1000_clean_rx_irq_ps()
1386 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); in e1000_clean_rx_irq_ps()
1397 ps_page = &buffer_info->ps_pages[0]; in e1000_clean_rx_irq_ps()
1426 for (j = 0; j < PS_PAGE_BUFFERS; j++) { in e1000_clean_rx_irq_ps()
1434 ps_page->dma = 0; in e1000_clean_rx_irq_ps()
1435 skb_fill_page_desc(skb, j, ps_page->page, 0, length); in e1000_clean_rx_irq_ps()
1466 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); in e1000_clean_rx_irq_ps()
1473 cleaned_count = 0; in e1000_clean_rx_irq_ps()
1521 int cleaned_count = 0; in e1000_clean_jumbo_rx_irq()
1523 unsigned int total_rx_bytes = 0, total_rx_packets = 0; in e1000_clean_jumbo_rx_irq()
1544 i = 0; in e1000_clean_jumbo_rx_irq()
1554 buffer_info->dma = 0; in e1000_clean_jumbo_rx_irq()
1576 skb_fill_page_desc(rxtop, 0, buffer_info->page, in e1000_clean_jumbo_rx_irq()
1577 0, length); in e1000_clean_jumbo_rx_irq()
1582 buffer_info->page, 0, in e1000_clean_jumbo_rx_irq()
1594 buffer_info->page, 0, in e1000_clean_jumbo_rx_irq()
1619 skb_fill_page_desc(skb, 0, in e1000_clean_jumbo_rx_irq()
1620 buffer_info->page, 0, in e1000_clean_jumbo_rx_irq()
1648 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); in e1000_clean_jumbo_rx_irq()
1654 cleaned_count = 0; in e1000_clean_jumbo_rx_irq()
1687 for (i = 0; i < rx_ring->count; i++) { in e1000_clean_rx_ring()
1701 buffer_info->dma = 0; in e1000_clean_rx_ring()
1714 for (j = 0; j < PS_PAGE_BUFFERS; j++) { in e1000_clean_rx_ring()
1720 ps_page->dma = 0; in e1000_clean_rx_ring()
1733 memset(rx_ring->desc, 0, rx_ring->size); in e1000_clean_rx_ring()
1735 rx_ring->next_to_clean = 0; in e1000_clean_rx_ring()
1736 rx_ring->next_to_use = 0; in e1000_clean_rx_ring()
1809 adapter->total_tx_bytes = 0; in e1000_intr_msi()
1810 adapter->total_tx_packets = 0; in e1000_intr_msi()
1811 adapter->total_rx_bytes = 0; in e1000_intr_msi()
1812 adapter->total_rx_packets = 0; in e1000_intr_msi()
1889 adapter->total_tx_bytes = 0; in e1000_intr()
1890 adapter->total_tx_packets = 0; in e1000_intr()
1891 adapter->total_rx_bytes = 0; in e1000_intr()
1892 adapter->total_rx_packets = 0; in e1000_intr()
1929 adapter->total_tx_bytes = 0; in e1000_intr_msix_tx()
1930 adapter->total_tx_packets = 0; in e1000_intr_msix_tx()
1953 1000000000 / (rx_ring->itr_val * 256) : 0; in e1000_intr_msix_rx()
1956 rx_ring->set_itr = 0; in e1000_intr_msix_rx()
1960 adapter->total_rx_bytes = 0; in e1000_intr_msix_rx()
1961 adapter->total_rx_packets = 0; in e1000_intr_msix_rx()
1979 int vector = 0; in e1000_configure_msix()
1980 u32 ctrl_ext, ivar = 0; in e1000_configure_msix()
1982 adapter->eiac_mask = 0; in e1000_configure_msix()
2069 for (i = 0; i < adapter->num_vectors; i++) in e1000e_set_interrupt_capability()
2076 if (err > 0) in e1000e_set_interrupt_capability()
2112 int err = 0, vector = 0; in e1000_request_msix()
2117 "%.14s-rx-0", netdev->name); in e1000_request_msix()
2121 e1000_intr_msix_rx, 0, adapter->rx_ring->name, in e1000_request_msix()
2133 "%.14s-tx-0", netdev->name); in e1000_request_msix()
2137 e1000_intr_msix_tx, 0, adapter->tx_ring->name, in e1000_request_msix()
2147 e1000_msix_other, 0, netdev->name, netdev); in e1000_request_msix()
2153 return 0; in e1000_request_msix()
2178 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, in e1000_request_irq()
2201 int vector = 0; in e1000_free_irq()
2225 ew32(IMC, ~0); in e1000_irq_disable()
2227 ew32(EIAC_82574, 0); in e1000_irq_disable()
2233 for (i = 0; i < adapter->num_vectors; i++) in e1000_irq_disable()
2326 return 0; in e1000_alloc_ring_dma()
2333 * Return 0 on success, negative on failure
2353 tx_ring->next_to_use = 0; in e1000e_setup_tx_resources()
2354 tx_ring->next_to_clean = 0; in e1000e_setup_tx_resources()
2356 return 0; in e1000e_setup_tx_resources()
2367 * Returns 0 on success, negative on failure
2380 for (i = 0; i < rx_ring->count; i++) { in e1000e_setup_rx_resources()
2399 rx_ring->next_to_clean = 0; in e1000e_setup_rx_resources()
2400 rx_ring->next_to_use = 0; in e1000e_setup_rx_resources()
2403 return 0; in e1000e_setup_rx_resources()
2406 for (i = 0; i < rx_ring->count; i++) { in e1000e_setup_rx_resources()
2427 for (i = 0; i < tx_ring->count; i++) { in e1000_clean_tx_ring()
2434 memset(tx_ring->buffer_info, 0, size); in e1000_clean_tx_ring()
2436 memset(tx_ring->desc, 0, tx_ring->size); in e1000_clean_tx_ring()
2438 tx_ring->next_to_use = 0; in e1000_clean_tx_ring()
2439 tx_ring->next_to_clean = 0; in e1000_clean_tx_ring()
2477 for (i = 0; i < rx_ring->count; i++) in e1000e_free_rx_resources()
2507 if (packets == 0) in e1000_update_itr()
2553 current_itr = 0; in e1000_set_itr()
2559 new_itr = 0; in e1000_set_itr()
2623 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; in e1000e_write_itr()
2628 for (vector = 0; vector < adapter->num_vectors; vector++) in e1000e_write_itr()
2655 return 0; in e1000_alloc_queues()
2674 int tx_cleaned = 1, work_done = 0; in e1000e_poll()
2715 return 0; in e1000_vlan_rx_add_vid()
2719 index = (vid >> 5) & 0x7F; in e1000_vlan_rx_add_vid()
2721 vfta |= BIT((vid & 0x1F)); in e1000_vlan_rx_add_vid()
2727 return 0; in e1000_vlan_rx_add_vid()
2742 return 0; in e1000_vlan_rx_kill_vid()
2747 index = (vid >> 5) & 0x7F; in e1000_vlan_rx_kill_vid()
2749 vfta &= ~BIT((vid & 0x1F)); in e1000_vlan_rx_kill_vid()
2755 return 0; in e1000_vlan_rx_kill_vid()
2849 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); in e1000_restore_vlan()
2881 for (i = 0, j = 0; i < 8; i++) { in e1000_init_manageability_pt()
2899 for (i = 0, j = 0; i < 8; i++) in e1000_init_manageability_pt()
2900 if (er32(MDEF(i)) == 0) { in e1000_init_manageability_pt()
2933 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); in e1000_configure_tx()
2934 ew32(TDBAH(0), (tdba >> 32)); in e1000_configure_tx()
2935 ew32(TDLEN(0), tdlen); in e1000_configure_tx()
2936 ew32(TDH(0), 0); in e1000_configure_tx()
2937 ew32(TDT(0), 0); in e1000_configure_tx()
2938 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); in e1000_configure_tx()
2939 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); in e1000_configure_tx()
2941 writel(0, tx_ring->head); in e1000_configure_tx()
2943 e1000e_update_tdt_wa(tx_ring, 0); in e1000_configure_tx()
2945 writel(0, tx_ring->tail); in e1000_configure_tx()
2953 u32 txdctl = er32(TXDCTL(0)); in e1000_configure_tx()
2962 * pthresh = 0x1f ==> prefetch if internal cache 31 or less in e1000_configure_tx()
2967 ew32(TXDCTL(0), txdctl); in e1000_configure_tx()
2970 ew32(TXDCTL(1), er32(TXDCTL(0))); in e1000_configure_tx()
2979 tarc = er32(TARC(0)); in e1000_configure_tx()
2985 ew32(TARC(0), tarc); in e1000_configure_tx()
2990 tarc = er32(TARC(0)); in e1000_configure_tx()
2992 ew32(TARC(0), tarc); in e1000_configure_tx()
3020 reg_val = er32(TARC(0)); in e1000_configure_tx()
3027 ew32(TARC(0), reg_val); in e1000_configure_tx()
3032 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3042 u32 pages = 0; in e1000_setup_rctl()
3088 phy_data &= 0xfff8; in e1000_setup_rctl()
3093 phy_data &= 0x0fff; in e1000_setup_rctl()
3095 e1e_wphy(hw, 0x10, 0x2823); in e1000_setup_rctl()
3096 e1e_wphy(hw, 0x11, 0x0003); in e1000_setup_rctl()
3143 adapter->rx_ps_pages = 0; in e1000_setup_rctl()
3146 u32 psrctl = 0; in e1000_setup_rctl()
3228 * is set). set GRAN=1 and write back up to 0x4 worth, and in e1000_configure_rx()
3229 * enable prefetching of 0x20 Rx descriptors in e1000_configure_rx()
3233 * pthresh = 0x20 in e1000_configure_rx()
3235 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); in e1000_configure_rx()
3244 if ((adapter->itr_setting != 0) && (adapter->itr != 0)) in e1000_configure_rx()
3250 ew32(IAM, 0xffffffff); in e1000_configure_rx()
3258 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); in e1000_configure_rx()
3259 ew32(RDBAH(0), (rdba >> 32)); in e1000_configure_rx()
3260 ew32(RDLEN(0), rdlen); in e1000_configure_rx()
3261 ew32(RDH(0), 0); in e1000_configure_rx()
3262 ew32(RDT(0), 0); in e1000_configure_rx()
3263 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); in e1000_configure_rx()
3264 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); in e1000_configure_rx()
3266 writel(0, rx_ring->head); in e1000_configure_rx()
3268 e1000e_update_rdt_wa(rx_ring, 0); in e1000_configure_rx()
3270 writel(0, rx_ring->tail); in e1000_configure_rx()
3289 u32 rxdctl = er32(RXDCTL(0)); in e1000_configure_rx()
3291 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); in e1000_configure_rx()
3312 * 0 on no addresses written
3325 hw->mac.ops.update_mc_addr_list(hw, NULL, 0); in e1000e_write_mc_addr_list()
3326 return 0; in e1000e_write_mc_addr_list()
3334 i = 0; in e1000e_write_mc_addr_list()
3350 * 0 on no addresses written
3358 int count = 0; in e1000e_write_uc_addr_list()
3385 if (ret_val < 0) in e1000e_write_uc_addr_list()
3392 for (; rar_entries > 0; rar_entries--) { in e1000e_write_uc_addr_list()
3393 ew32(RAH(rar_entries), 0); in e1000e_write_uc_addr_list()
3394 ew32(RAL(rar_entries), 0); in e1000e_write_uc_addr_list()
3440 if (count < 0) in e1000e_set_rx_mode()
3449 if (count < 0) in e1000e_set_rx_mode()
3469 for (i = 0; i < 10; i++) in e1000e_setup_rss_hash()
3472 /* Direct all traffic to queue 0 */ in e1000e_setup_rss_hash()
3473 for (i = 0; i < 32; i++) in e1000e_setup_rss_hash()
3474 ew32(RETA(i), 0); in e1000e_setup_rss_hash()
3514 if (!(fextnvm7 & BIT(0))) { in e1000e_get_base_timinca()
3515 ew32(FEXTNVM7, fextnvm7 | BIT(0)); in e1000e_get_base_timinca()
3584 return 0; in e1000e_get_base_timinca()
3609 u32 rxmtrl = 0; in e1000e_config_hwtstamp()
3610 u16 rxudp = 0; in e1000e_config_hwtstamp()
3624 tsync_tx_ctl = 0; in e1000e_config_hwtstamp()
3634 tsync_rx_ctl = 0; in e1000e_config_hwtstamp()
3751 return 0; in e1000e_config_hwtstamp()
3824 tdt = er32(TDT(0)); in e1000_flush_tx_ring()
3830 tx_desc->upper.data = 0; in e1000_flush_tx_ring()
3835 tx_ring->next_to_use = 0; in e1000_flush_tx_ring()
3836 ew32(TDT(0), tx_ring->next_to_use); in e1000_flush_tx_ring()
3856 rxdctl = er32(RXDCTL(0)); in e1000_flush_rx_ring()
3858 rxdctl &= 0xffffc000; in e1000_flush_rx_ring()
3863 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); in e1000_flush_rx_ring()
3865 ew32(RXDCTL(0), rxdctl); in e1000_flush_rx_ring()
3896 tdlen = er32(TDLEN(0)); in e1000_flush_desc_rings()
3989 pba &= 0xffff; in e1000e_reset()
4029 fc->pause_time = 0xFFFF; in e1000e_reset()
4041 fc->high_water = 0x2800; in e1000e_reset()
4058 fc->high_water = 0x3500; in e1000e_reset()
4059 fc->low_water = 0x1500; in e1000e_reset()
4061 fc->high_water = 0x5000; in e1000e_reset()
4062 fc->low_water = 0x3000; in e1000e_reset()
4064 fc->refresh_time = 0x1000; in e1000e_reset()
4074 fc->refresh_time = 0xFFFF; in e1000e_reset()
4075 fc->pause_time = 0xFFFF; in e1000e_reset()
4078 fc->high_water = 0x05C20; in e1000e_reset()
4079 fc->low_water = 0x05048; in e1000e_reset()
4101 if (adapter->itr_setting & 0x3) { in e1000e_reset()
4107 e1000e_write_itr(adapter, 0); in e1000e_reset()
4129 ew32(WUC, 0); in e1000e_reset()
4171 0 : adapter->eee_advert); in e1000e_reset()
4184 u16 phy_data = 0; in e1000e_reset()
4193 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { in e1000e_reset()
4196 /* Fextnvm7 @ 0xe4[2] = 1 */ in e1000e_reset()
4200 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ in e1000e_reset()
4315 adapter->link_speed = 0; in e1000e_down()
4316 adapter->link_duplex = 0; in e1000e_down()
4364 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { in e1000e_sanitize_systim()
4373 /* VMWare users have seen incvalue of zero, don't div / 0 */ in e1000e_sanitize_systim()
4374 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); in e1000e_sanitize_systim()
4378 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) in e1000e_sanitize_systim()
4408 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { in e1000e_read_systim()
4482 return 0; in e1000_sw_init()
4510 * e1000_test_msi_interrupt - Returns 0 for successful test
4538 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, in e1000_test_msi_interrupt()
4577 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4588 return 0; in e1000_test_msi()
4612 * Returns 0 on success, negative value on failure
4700 return 0; in e1000e_open()
4720 * Returns 0, this is not allowed to fail
4771 return 0; in e1000e_close()
4779 * Returns 0 on success, negative on failure
4793 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); in e1000_set_mac()
4800 * between the time RAR[0] gets clobbered and the time it in e1000_set_mac()
4803 * are dropped. Eventually the LAA will be in RAR[0] and in e1000_set_mac()
4810 return 0; in e1000_set_mac()
4945 if (adapter->link_speed == 0) in e1000e_update_stats()
5081 phy->lpa = 0; in e1000_phy_read_status()
5084 phy->stat1000 = 0; in e1000_phy_read_status()
5108 s32 ret_val = 0; in e1000e_has_link()
5169 adapter->phy_hang_count = 0; in e1000e_check_82574_phy_workaround()
5172 adapter->phy_hang_count = 0; in e1000e_check_82574_phy_workaround()
5201 u32 dmoff_exit_timeout = 100, tries = 0; in e1000_watchdog_task()
5295 tarc0 = er32(TARC(0)); in e1000_watchdog_task()
5297 ew32(TARC(0), tarc0); in e1000_watchdog_task()
5326 * after setting TARC(0) in e1000_watchdog_task()
5347 adapter->link_speed = 0; in e1000_watchdog_task()
5348 adapter->link_duplex = 0; in e1000_watchdog_task()
5411 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; in e1000_watchdog_task()
5429 * reset from the other port. Set the appropriate LAA in RAR[0] in e1000_watchdog_task()
5432 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); in e1000_watchdog_task()
5454 #define E1000_TX_FLAGS_CSUM 0x00000001
5455 #define E1000_TX_FLAGS_VLAN 0x00000002
5456 #define E1000_TX_FLAGS_TSO 0x00000004
5457 #define E1000_TX_FLAGS_IPV4 0x00000008
5458 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5459 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5460 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5469 u32 cmd_length = 0; in e1000_tso()
5470 u16 ipcse = 0, mss; in e1000_tso()
5475 return 0; in e1000_tso()
5477 err = skb_cow_head(skb, 0); in e1000_tso()
5478 if (err < 0) in e1000_tso()
5485 iph->tot_len = 0; in e1000_tso()
5486 iph->check = 0; in e1000_tso()
5488 0, IPPROTO_TCP, 0); in e1000_tso()
5493 ipcse = 0; in e1000_tso()
5512 context_desc->upper_setup.tcp_fields.tucse = 0; in e1000_tso()
5522 i = 0; in e1000_tso()
5564 context_desc->lower_setup.ip_config = 0; in e1000_tx_csum()
5567 context_desc->upper_setup.tcp_fields.tucse = 0; in e1000_tx_csum()
5568 context_desc->tcp_seg_setup.data = 0; in e1000_tx_csum()
5576 i = 0; in e1000_tx_csum()
5590 unsigned int offset = 0, size, count = 0, i; in e1000_tx_map()
5616 i = 0; in e1000_tx_map()
5620 for (f = 0; f < nr_frags; f++) { in e1000_tx_map()
5624 offset = 0; in e1000_tx_map()
5629 i = 0; in e1000_tx_map()
5663 buffer_info->dma = 0; in e1000_tx_map()
5668 if (i == 0) in e1000_tx_map()
5675 return 0; in e1000_tx_map()
5683 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; in e1000_tx_queue()
5725 i = 0; in e1000_tx_queue()
5726 } while (--count > 0); in e1000_tx_queue()
5755 return 0; in e1000_transfer_dhcp_info()
5758 return 0; in e1000_transfer_dhcp_info()
5761 return 0; in e1000_transfer_dhcp_info()
5768 return 0; in e1000_transfer_dhcp_info()
5772 return 0; in e1000_transfer_dhcp_info()
5779 return 0; in e1000_transfer_dhcp_info()
5802 return 0; in __e1000_maybe_stop_tx()
5810 return 0; in e1000_maybe_stop_tx()
5820 unsigned int tx_flags = 0; in e1000_xmit_frame()
5824 int count = 0; in e1000_xmit_frame()
5834 if (skb->len <= 0) { in e1000_xmit_frame()
5878 for (f = 0; f < nr_frags; f++) in e1000_xmit_frame()
5900 if (tso < 0) { in e1000_xmit_frame()
5920 /* if count is 0 then mapping error has occurred */ in e1000_xmit_frame()
5948 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { in e1000_xmit_frame()
5957 tx_ring->buffer_info[first].time_stamp = 0; in e1000_xmit_frame()
6049 * Returns 0 on success, negative on failure
6110 return 0; in e1000_change_mtu()
6129 switch (data->reg_num & 0x1F) { in e1000_mii_ioctl()
6140 data->val_out = (adapter->hw.phy.id & 0xFFFF); in e1000_mii_ioctl()
6168 return 0; in e1000_mii_ioctl()
6219 sizeof(config)) ? -EFAULT : 0; in e1000e_hwtstamp_set()
6227 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; in e1000e_hwtstamp_get()
6268 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { in e1000_init_phy_wakeup()
6271 (u16)(mac_reg & 0xFFFF)); in e1000_init_phy_wakeup()
6273 (u16)((mac_reg >> 16) & 0xFFFF)); in e1000_init_phy_wakeup()
6373 * Force the SMBus in PHY page769_23[0] = 1 in e1000e_s0ix_entry_flow()
6383 /* DFT control: PHY bit: page769_20[0] = 1 in e1000e_s0ix_entry_flow()
6387 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1 in e1000e_s0ix_entry_flow()
6390 phy_data |= BIT(0); in e1000e_s0ix_entry_flow()
6446 mac_data &= ~BIT(0); in e1000e_s0ix_entry_flow()
6460 ew32(TDFH, 0); in e1000e_s0ix_entry_flow()
6463 ew32(TDFT, 0); in e1000e_s0ix_entry_flow()
6466 ew32(TDFHS, 0); in e1000e_s0ix_entry_flow()
6469 ew32(TDFTS, 0); in e1000e_s0ix_entry_flow()
6472 ew32(TDFPC, 0); in e1000e_s0ix_entry_flow()
6475 ew32(RDFH, 0); in e1000e_s0ix_entry_flow()
6478 ew32(RDFT, 0); in e1000e_s0ix_entry_flow()
6481 ew32(RDFHS, 0); in e1000e_s0ix_entry_flow()
6484 ew32(RDFTS, 0); in e1000e_s0ix_entry_flow()
6487 ew32(RDFPC, 0); in e1000e_s0ix_entry_flow()
6496 u32 i = 0; in e1000e_s0ix_exit_flow()
6531 mac_data &= 0xFFBFFFFF; in e1000e_s0ix_exit_flow()
6565 mac_data &= 0xFFF7FFFF; in e1000e_s0ix_exit_flow()
6572 mac_data &= 0xFFFFFF7F; in e1000e_s0ix_exit_flow()
6579 phy_data &= 0xFBFF; in e1000e_s0ix_exit_flow()
6584 * 772_29[5] = 0 CS_Mode_Stay_In_K1 in e1000e_s0ix_exit_flow()
6587 phy_data &= 0xFFDF; in e1000e_s0ix_exit_flow()
6591 * Unforce the SMBus in PHY page769_23[0] = 0 in e1000e_s0ix_exit_flow()
6592 * Unforce the SMBus in MAC CTRL_EXT[11] = 0 in e1000e_s0ix_exit_flow()
6604 mac_data &= 0xFFFFFFF7; in e1000e_s0ix_exit_flow()
6610 mac_data |= BIT(0); in e1000e_s0ix_exit_flow()
6644 return 0; in e1000e_pm_freeze()
6653 int retval = 0; in __e1000_shutdown()
6661 wufc = 0; in __e1000_shutdown()
6710 ew32(WUC, 0); in __e1000_shutdown()
6711 ew32(WUFC, 0); in __e1000_shutdown()
6734 u16 lpi_ctrl = 0; in __e1000_shutdown()
6778 return 0; in __e1000_shutdown()
6790 return 0; in __e1000_shutdown()
6804 u16 aspm_dis_mask = 0; in __e1000e_disable_aspm()
6876 __e1000e_disable_aspm(pdev, state, 0); in e1000e_disable_aspm()
6896 int rc = 0; in e1000e_pm_thaw()
6921 u16 aspm_disable_flag = 0; in __e1000_resume()
6951 e1e_wphy(&adapter->hw, BM_WUS, ~0); in __e1000_resume()
6964 ew32(WUS, ~0); in __e1000_resume()
6978 return 0; in __e1000_resume()
7084 return 0; in e1000e_pm_runtime_suspend()
7106 vector = 0; in e1000_intr_msix()
7192 u16 aspm_disable_flag = 0; in e1000_io_slot_reset()
7213 pci_enable_wake(pdev, PCI_D3hot, 0); in e1000_io_slot_reset()
7214 pci_enable_wake(pdev, PCI_D3cold, 0); in e1000_io_slot_reset()
7217 ew32(WUS, ~0); in e1000_io_slot_reset()
7277 u16 buf = 0; in e1000_eeprom_checks()
7284 if (!ret_val && (!(buf & BIT(0)))) { in e1000_eeprom_checks()
7324 return 0; in e1000_set_features()
7377 * Returns 0 on success, negative on failure
7392 u16 aspm_disable_flag = 0; in e1000_probe()
7394 u16 eeprom_data = 0; in e1000_probe()
7396 s32 ret_val = 0; in e1000_probe()
7409 pci_using_dac = 0; in e1000_probe()
7460 mmio_start = pci_resource_start(pdev, 0); in e1000_probe()
7461 mmio_len = pci_resource_len(pdev, 0); in e1000_probe()
7516 adapter->hw.phy.autoneg_wait_to_complete = 0; in e1000_probe()
7521 adapter->hw.phy.disable_polarity_correction = 0; in e1000_probe()
7576 for (i = 0;; i++) { in e1000_probe()
7577 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) in e1000_probe()
7602 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); in e1000_probe()
7603 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); in e1000_probe()
7616 adapter->hw.phy.autoneg_advertised = 0x2f; in e1000_probe()
7651 adapter->eeprom_wol = 0; in e1000_probe()
7666 adapter->eeprom_vers = 0; in e1000_probe()
7700 return 0; in e1000_probe()
7923 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */