21 #define HINIC_CSR_DMA_ATTR_ADDR(idx)                    \  argument
22 	(HINIC_DMA_ATTR_BASE + (idx) * HINIC_DMA_ATTR_STRIDE)
27 #define HINIC_CSR_PPF_ELECTION_ADDR(idx)                \  argument
28 	(HINIC_ELECTION_BASE +  (idx) * HINIC_PPF_ELECTION_STRIDE)
35 #define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)       \  argument
36 	(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
38 #define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)       \  argument
39 	(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
41 #define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx)           \  argument
42 	(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
44 #define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx)           \  argument
45 	(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
47 #define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)     \  argument
48 	(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
50 #define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)          \  argument
51 	(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
53 #define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx)            \  argument
54 	(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
56 #define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx)           \  argument
57 	(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
59 #define HINIC_CSR_API_CMD_STATUS_ADDR(idx)              \  argument
60 	(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
68 #define HINIC_CSR_MSIX_CTRL_ADDR(idx)                   \  argument
69 	(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
71 #define HINIC_CSR_MSIX_CNT_ADDR(idx)                    \  argument
72 	(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
116 #define HINIC_CSR_AEQ_CTRL_0_ADDR(idx)                  \  argument
117 	(HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
119 #define HINIC_CSR_AEQ_CTRL_1_ADDR(idx)                  \  argument
120 	(HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
122 #define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx)                \  argument
123 	(HINIC_AEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
125 #define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx)                \  argument
126 	(HINIC_AEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
128 #define HINIC_CSR_CEQ_CTRL_0_ADDR(idx)                  \  argument
129 	(HINIC_CEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
131 #define HINIC_CSR_CEQ_CTRL_1_ADDR(idx)                  \  argument
132 	(HINIC_CEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
134 #define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx)                \  argument
135 	(HINIC_CEQ_CONS_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
137 #define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx)                \  argument
138 	(HINIC_CEQ_PROD_IDX_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)