Lines Matching defs:gfar
698 struct gfar { struct
699 u32 tsec_id; /* 0x.000 - Controller ID register */
700 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
701 u8 res1[8];
702 u32 ievent; /* 0x.010 - Interrupt Event Register */
703 u32 imask; /* 0x.014 - Interrupt Mask Register */
704 u32 edis; /* 0x.018 - Error Disabled Register */
705 u32 emapg; /* 0x.01c - Group Error mapping register */
706 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
707 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
708 u32 ptv; /* 0x.028 - Pause Time Value Register */
709 u32 dmactrl; /* 0x.02c - DMA Control Register */
710 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
711 u8 res2[28];
712 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
714 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
716 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
718 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
720 u8 res3[44];
721 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
722 u8 res4[8];
723 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
724 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
725 u8 res5[96];
726 u32 tctrl; /* 0x.100 - Transmit Control Register */
727 u32 tstat; /* 0x.104 - Transmit Status Register */
728 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
729 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
730 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
731 u32 tqueue; /* 0x.114 - Transmit queue control register */
732 u8 res7[40];
733 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
734 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
735 u8 res8[52];
736 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
737 u8 res9a[4];
738 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
739 u8 res9b[4];
740 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
741 u8 res9c[4];
742 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
743 u8 res9d[4];
744 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
745 u8 res9e[4];
746 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
747 u8 res9f[4];
748 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
749 u8 res9g[4];
750 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
751 u8 res9h[4];
752 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
753 u8 res9[64];
754 u32 tbaseh; /* 0x.200 - TxBD base address high */
755 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
756 u8 res10a[4];
757 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
758 u8 res10b[4];
759 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
760 u8 res10c[4];
761 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
762 u8 res10d[4];
763 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
764 u8 res10e[4];
765 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
766 u8 res10f[4];
767 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
768 u8 res10g[4];
769 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
770 u8 res10[192];
771 u32 rctrl; /* 0x.300 - Receive Control Register */
772 u32 rstat; /* 0x.304 - Receive Status Register */
773 u8 res12[8];
774 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
775 u32 rqueue; /* 0x.314 - Receive queue control register */
776 u32 rir0; /* 0x.318 - Ring mapping register 0 */
777 u32 rir1; /* 0x.31c - Ring mapping register 1 */
778 u32 rir2; /* 0x.320 - Ring mapping register 2 */
779 u32 rir3; /* 0x.324 - Ring mapping register 3 */
780 u8 res13[8];
781 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
782 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
783 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
784 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
785 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
786 u8 res14[56];
787 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
788 u8 res15a[4];
789 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
790 u8 res15b[4];
791 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
792 u8 res15c[4];
793 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
794 u8 res15d[4];
795 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
796 u8 res15e[4];
797 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
798 u8 res15f[4];
799 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
800 u8 res15g[4];
801 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
802 u8 res15h[4];
803 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
804 u8 res16[64];
828 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ argument
829 u32 ifctrl; /* 0x.538 - Interface control register */
830 u32 ifstat; /* 0x.53c - Interface Status Register */
831 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
832 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
833 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
834 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
835 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
836 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
837 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
838 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
839 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
840 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
841 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
842 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
843 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
844 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
845 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
846 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
847 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
848 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
849 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
850 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
851 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
852 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
853 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
854 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
855 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
856 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
857 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
858 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
859 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
860 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
861 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
862 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
863 u8 res20[192];
864 struct rmon_mib rmon; /* 0x.680-0x.73c */
865 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
866 u8 res21[188];
867 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
868 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
869 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
870 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
871 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
872 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
873 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
874 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
875 u8 res22[96];
876 u32 gaddr0; /* 0x.880 - Group address register 0 */
877 u32 gaddr1; /* 0x.884 - Group address register 1 */
878 u32 gaddr2; /* 0x.888 - Group address register 2 */
879 u32 gaddr3; /* 0x.88c - Group address register 3 */
880 u32 gaddr4; /* 0x.890 - Group address register 4 */
881 u32 gaddr5; /* 0x.894 - Group address register 5 */
882 u32 gaddr6; /* 0x.898 - Group address register 6 */
883 u32 gaddr7; /* 0x.89c - Group address register 7 */
884 u8 res23a[352];
885 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
886 u8 res23b[252];
887 u8 res23c[248];
888 u32 attr; /* 0x.bf8 - Attributes Register */
889 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
890 u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
891 u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
892 u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
893 u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
894 u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
895 u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
896 u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
897 u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
898 u8 res24[36];
899 u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
900 u8 res24a[4];
901 u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
902 u8 res24b[4];
903 u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
904 u8 res24c[4];
905 u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
906 u8 res24d[4];
907 u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
908 u8 res24e[4];
909 u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
910 u8 res24f[4];
911 u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
912 u8 res24g[4];
913 u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
914 u8 res24h[4];
915 u8 res24x[556];
916 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
917 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
918 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
919 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
920 u8 res25[16];
921 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
922 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
923 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
924 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
925 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
926 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
927 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
928 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
929 u8 res26[32];
930 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
931 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
932 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
933 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
934 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
935 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
936 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
937 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
938 u8 res27[208];