51 /* SGMII Control defines */
59 /* SGMII Device Ability for SGMII defines */
69 /* SGMII IF Mode defines */
522 	/* SGMII mode */  in setup_sgmii_internal_phy()
545 	/* Device ability according to SGMII specification */  in setup_sgmii_internal_phy()
549 	/* Adjust link timer for SGMII  -  in setup_sgmii_internal_phy()
550 	 * According to Cisco SGMII specification the timer should be 1.6 ms.  in setup_sgmii_internal_phy()
552 	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so  in setup_sgmii_internal_phy()
555 	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so  in setup_sgmii_internal_phy()
558 	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,  in setup_sgmii_internal_phy()
559 	 * we always set up here a value of 2.5 SGMII.  in setup_sgmii_internal_phy()
581 	/* Adjust link timer for SGMII  -  in setup_sgmii_internal_phy_base_x()
584 	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so  in setup_sgmii_internal_phy_base_x()
587 	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so  in setup_sgmii_internal_phy_base_x()
590 	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,  in setup_sgmii_internal_phy_base_x()
591 	 * we always set up here a value of 2.5 SGMII.  in setup_sgmii_internal_phy_base_x()
1084 		/* Configure internal SGMII PHY */  in memac_init()
1090 		/* Configure 4 internal SGMII PHYs */  in memac_init()