196 	u32 tctrl;		/* 0x040 Transmit control register */  member
868 		iowrite32be(ioread32be(&regs->tctrl) &  in graceful_start()
869 				~TCTRL_GTS, &regs->tctrl);  in graceful_start()
900 			tmp = ioread32be(&regs->tctrl) | TCTRL_GTS;  in graceful_stop()
901 			iowrite32be(tmp, &regs->tctrl);  in graceful_stop()
967 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_set_tx_pause_frames()
1008 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_accept_rx_pause_frames()
1035 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_modify_mac_address()
1139 	u32 rctrl, tctrl;  in dtsec_set_tstamp()  local
1145 	tctrl = ioread32be(&regs->tctrl);  in dtsec_set_tstamp()
1149 		tctrl |= TCTRL_TTSE;  in dtsec_set_tstamp()
1152 		tctrl &= ~TCTRL_TTSE;  in dtsec_set_tstamp()
1156 	iowrite32be(tctrl, &regs->tctrl);  in dtsec_set_tstamp()
1272 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_adjust_link()