Lines Matching +full:eee +full:- +full:broken +full:- +full:100 +full:tx
1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
88 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
164 .name = "imx25-fec",
167 .name = "imx27-fec",
170 .name = "imx28-fec",
173 .name = "imx6q-fec",
176 .name = "mvf600-fec",
179 .name = "imx6sx-fec",
182 .name = "imx6ul-fec",
185 .name = "imx8mq-fec",
188 .name = "imx8qm-fec",
209 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
210 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
211 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
212 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
213 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
214 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
215 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
216 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
217 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
229 * if this is non-zero then assume it is the address to get MAC from.
251 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
305 #define FEC_MAX_TSO_SEGS 100
309 ((addr >= txq->tso_hdrs_dma) && \
310 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
317 return (bdp >= bd->last) ? bd->base in fec_enet_get_nextdesc()
318 : (struct bufdesc *)(((void *)bdp) + bd->dsize); in fec_enet_get_nextdesc()
324 return (bdp <= bd->base) ? bd->last in fec_enet_get_prevdesc()
325 : (struct bufdesc *)(((void *)bdp) - bd->dsize); in fec_enet_get_prevdesc()
331 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; in fec_enet_get_bd_index()
338 entries = (((const char *)txq->dirty_tx - in fec_enet_get_free_txdesc_num()
339 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; in fec_enet_get_free_txdesc_num()
341 return entries >= 0 ? entries : entries + txq->bd.ring_size; in fec_enet_get_free_txdesc_num()
370 netdev_info(ndev, "TX ring dump\n"); in fec_dump()
373 txq = fep->tx_queue[0]; in fec_dump()
374 bdp = txq->bd.base; in fec_dump()
379 bdp == txq->bd.cur ? 'S' : ' ', in fec_dump()
380 bdp == txq->dirty_tx ? 'H' : ' ', in fec_dump()
381 fec16_to_cpu(bdp->cbd_sc), in fec_dump()
382 fec32_to_cpu(bdp->cbd_bufaddr), in fec_dump()
383 fec16_to_cpu(bdp->cbd_datlen), in fec_dump()
384 txq->tx_skbuff[index]); in fec_dump()
385 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_dump()
387 } while (bdp != txq->bd.base); in fec_dump()
392 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; in is_ipv4_pkt()
399 if (skb->ip_summed != CHECKSUM_PARTIAL) in fec_enet_clear_csum()
403 return -1; in fec_enet_clear_csum()
406 ip_hdr(skb)->check = 0; in fec_enet_clear_csum()
407 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; in fec_enet_clear_csum()
418 struct bufdesc *bdp = txq->bd.cur; in fec_enet_txq_submit_frag_skb()
420 int nr_frags = skb_shinfo(skb)->nr_frags; in fec_enet_txq_submit_frag_skb()
431 this_frag = &skb_shinfo(skb)->frags[frag]; in fec_enet_txq_submit_frag_skb()
432 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_txq_submit_frag_skb()
435 status = fec16_to_cpu(bdp->cbd_sc); in fec_enet_txq_submit_frag_skb()
438 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); in fec_enet_txq_submit_frag_skb()
441 if (frag == nr_frags - 1) { in fec_enet_txq_submit_frag_skb()
443 if (fep->bufdesc_ex) { in fec_enet_txq_submit_frag_skb()
445 if (unlikely(skb_shinfo(skb)->tx_flags & in fec_enet_txq_submit_frag_skb()
446 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) in fec_enet_txq_submit_frag_skb()
451 if (fep->bufdesc_ex) { in fec_enet_txq_submit_frag_skb()
452 if (fep->quirks & FEC_QUIRK_HAS_AVB) in fec_enet_txq_submit_frag_skb()
453 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); in fec_enet_txq_submit_frag_skb()
454 if (skb->ip_summed == CHECKSUM_PARTIAL) in fec_enet_txq_submit_frag_skb()
457 ebdp->cbd_bdu = 0; in fec_enet_txq_submit_frag_skb()
458 ebdp->cbd_esc = cpu_to_fec32(estatus); in fec_enet_txq_submit_frag_skb()
463 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_txq_submit_frag_skb()
464 if (((unsigned long) bufaddr) & fep->tx_align || in fec_enet_txq_submit_frag_skb()
465 fep->quirks & FEC_QUIRK_SWAP_FRAME) { in fec_enet_txq_submit_frag_skb()
466 memcpy(txq->tx_bounce[index], bufaddr, frag_len); in fec_enet_txq_submit_frag_skb()
467 bufaddr = txq->tx_bounce[index]; in fec_enet_txq_submit_frag_skb()
469 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) in fec_enet_txq_submit_frag_skb()
473 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, in fec_enet_txq_submit_frag_skb()
475 if (dma_mapping_error(&fep->pdev->dev, addr)) { in fec_enet_txq_submit_frag_skb()
477 netdev_err(ndev, "Tx DMA memory map failed\n"); in fec_enet_txq_submit_frag_skb()
481 bdp->cbd_bufaddr = cpu_to_fec32(addr); in fec_enet_txq_submit_frag_skb()
482 bdp->cbd_datlen = cpu_to_fec16(frag_len); in fec_enet_txq_submit_frag_skb()
487 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_txq_submit_frag_skb()
492 bdp = txq->bd.cur; in fec_enet_txq_submit_frag_skb()
494 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_txq_submit_frag_skb()
495 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_txq_submit_frag_skb()
496 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); in fec_enet_txq_submit_frag_skb()
498 return ERR_PTR(-ENOMEM); in fec_enet_txq_submit_frag_skb()
505 int nr_frags = skb_shinfo(skb)->nr_frags; in fec_enet_txq_submit_skb()
523 /* Protocol checksum off-load for TCP and UDP. */ in fec_enet_txq_submit_skb()
529 /* Fill in a Tx ring entry */ in fec_enet_txq_submit_skb()
530 bdp = txq->bd.cur; in fec_enet_txq_submit_skb()
532 status = fec16_to_cpu(bdp->cbd_sc); in fec_enet_txq_submit_skb()
536 bufaddr = skb->data; in fec_enet_txq_submit_skb()
539 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_txq_submit_skb()
540 if (((unsigned long) bufaddr) & fep->tx_align || in fec_enet_txq_submit_skb()
541 fep->quirks & FEC_QUIRK_SWAP_FRAME) { in fec_enet_txq_submit_skb()
542 memcpy(txq->tx_bounce[index], skb->data, buflen); in fec_enet_txq_submit_skb()
543 bufaddr = txq->tx_bounce[index]; in fec_enet_txq_submit_skb()
545 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) in fec_enet_txq_submit_skb()
550 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); in fec_enet_txq_submit_skb()
551 if (dma_mapping_error(&fep->pdev->dev, addr)) { in fec_enet_txq_submit_skb()
554 netdev_err(ndev, "Tx DMA memory map failed\n"); in fec_enet_txq_submit_skb()
561 dma_unmap_single(&fep->pdev->dev, addr, in fec_enet_txq_submit_skb()
568 if (fep->bufdesc_ex) { in fec_enet_txq_submit_skb()
570 if (unlikely(skb_shinfo(skb)->tx_flags & in fec_enet_txq_submit_skb()
571 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) in fec_enet_txq_submit_skb()
575 bdp->cbd_bufaddr = cpu_to_fec32(addr); in fec_enet_txq_submit_skb()
576 bdp->cbd_datlen = cpu_to_fec16(buflen); in fec_enet_txq_submit_skb()
578 if (fep->bufdesc_ex) { in fec_enet_txq_submit_skb()
582 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && in fec_enet_txq_submit_skb()
583 fep->hwts_tx_en)) in fec_enet_txq_submit_skb()
584 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in fec_enet_txq_submit_skb()
586 if (fep->quirks & FEC_QUIRK_HAS_AVB) in fec_enet_txq_submit_skb()
587 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); in fec_enet_txq_submit_skb()
589 if (skb->ip_summed == CHECKSUM_PARTIAL) in fec_enet_txq_submit_skb()
592 ebdp->cbd_bdu = 0; in fec_enet_txq_submit_skb()
593 ebdp->cbd_esc = cpu_to_fec32(estatus); in fec_enet_txq_submit_skb()
596 index = fec_enet_get_bd_index(last_bdp, &txq->bd); in fec_enet_txq_submit_skb()
598 txq->tx_skbuff[index] = skb; in fec_enet_txq_submit_skb()
609 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_txq_submit_skb()
612 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); in fec_enet_txq_submit_skb()
617 * txq->bd.cur. in fec_enet_txq_submit_skb()
620 txq->bd.cur = bdp; in fec_enet_txq_submit_skb()
623 writel(0, txq->bd.reg_desc_active); in fec_enet_txq_submit_skb()
640 status = fec16_to_cpu(bdp->cbd_sc); in fec_enet_txq_put_data_tso()
645 if (((unsigned long) data) & fep->tx_align || in fec_enet_txq_put_data_tso()
646 fep->quirks & FEC_QUIRK_SWAP_FRAME) { in fec_enet_txq_put_data_tso()
647 memcpy(txq->tx_bounce[index], data, size); in fec_enet_txq_put_data_tso()
648 data = txq->tx_bounce[index]; in fec_enet_txq_put_data_tso()
650 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) in fec_enet_txq_put_data_tso()
654 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); in fec_enet_txq_put_data_tso()
655 if (dma_mapping_error(&fep->pdev->dev, addr)) { in fec_enet_txq_put_data_tso()
658 netdev_err(ndev, "Tx DMA memory map failed\n"); in fec_enet_txq_put_data_tso()
662 bdp->cbd_datlen = cpu_to_fec16(size); in fec_enet_txq_put_data_tso()
663 bdp->cbd_bufaddr = cpu_to_fec32(addr); in fec_enet_txq_put_data_tso()
665 if (fep->bufdesc_ex) { in fec_enet_txq_put_data_tso()
666 if (fep->quirks & FEC_QUIRK_HAS_AVB) in fec_enet_txq_put_data_tso()
667 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); in fec_enet_txq_put_data_tso()
668 if (skb->ip_summed == CHECKSUM_PARTIAL) in fec_enet_txq_put_data_tso()
670 ebdp->cbd_bdu = 0; in fec_enet_txq_put_data_tso()
671 ebdp->cbd_esc = cpu_to_fec32(estatus); in fec_enet_txq_put_data_tso()
679 if (fep->bufdesc_ex) in fec_enet_txq_put_data_tso()
680 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); in fec_enet_txq_put_data_tso()
683 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_txq_put_data_tso()
701 status = fec16_to_cpu(bdp->cbd_sc); in fec_enet_txq_put_hdr_tso()
705 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; in fec_enet_txq_put_hdr_tso()
706 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; in fec_enet_txq_put_hdr_tso()
707 if (((unsigned long)bufaddr) & fep->tx_align || in fec_enet_txq_put_hdr_tso()
708 fep->quirks & FEC_QUIRK_SWAP_FRAME) { in fec_enet_txq_put_hdr_tso()
709 memcpy(txq->tx_bounce[index], skb->data, hdr_len); in fec_enet_txq_put_hdr_tso()
710 bufaddr = txq->tx_bounce[index]; in fec_enet_txq_put_hdr_tso()
712 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) in fec_enet_txq_put_hdr_tso()
715 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, in fec_enet_txq_put_hdr_tso()
717 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { in fec_enet_txq_put_hdr_tso()
720 netdev_err(ndev, "Tx DMA memory map failed\n"); in fec_enet_txq_put_hdr_tso()
725 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); in fec_enet_txq_put_hdr_tso()
726 bdp->cbd_datlen = cpu_to_fec16(hdr_len); in fec_enet_txq_put_hdr_tso()
728 if (fep->bufdesc_ex) { in fec_enet_txq_put_hdr_tso()
729 if (fep->quirks & FEC_QUIRK_HAS_AVB) in fec_enet_txq_put_hdr_tso()
730 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); in fec_enet_txq_put_hdr_tso()
731 if (skb->ip_summed == CHECKSUM_PARTIAL) in fec_enet_txq_put_hdr_tso()
733 ebdp->cbd_bdu = 0; in fec_enet_txq_put_hdr_tso()
734 ebdp->cbd_esc = cpu_to_fec32(estatus); in fec_enet_txq_put_hdr_tso()
737 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_txq_put_hdr_tso()
748 struct bufdesc *bdp = txq->bd.cur; in fec_enet_txq_submit_tso()
760 /* Protocol checksum off-load for TCP and UDP. */ in fec_enet_txq_submit_tso()
769 total_len = skb->len - hdr_len; in fec_enet_txq_submit_tso()
773 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_txq_submit_tso()
774 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); in fec_enet_txq_submit_tso()
775 total_len -= data_left; in fec_enet_txq_submit_tso()
778 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; in fec_enet_txq_submit_tso()
788 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_txq_submit_tso()
789 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_txq_submit_tso()
798 data_left -= size; in fec_enet_txq_submit_tso()
802 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_txq_submit_tso()
806 txq->tx_skbuff[index] = skb; in fec_enet_txq_submit_tso()
809 txq->bd.cur = bdp; in fec_enet_txq_submit_tso()
812 if (!(fep->quirks & FEC_QUIRK_ERR007885) || in fec_enet_txq_submit_tso()
813 !readl(txq->bd.reg_desc_active) || in fec_enet_txq_submit_tso()
814 !readl(txq->bd.reg_desc_active) || in fec_enet_txq_submit_tso()
815 !readl(txq->bd.reg_desc_active) || in fec_enet_txq_submit_tso()
816 !readl(txq->bd.reg_desc_active)) in fec_enet_txq_submit_tso()
817 writel(0, txq->bd.reg_desc_active); in fec_enet_txq_submit_tso()
837 txq = fep->tx_queue[queue]; in fec_enet_start_xmit()
848 if (entries_free <= txq->tx_stop_threshold) in fec_enet_start_xmit()
854 /* Init RX & TX buffer descriptors
865 for (q = 0; q < fep->num_rx_queues; q++) { in fec_enet_bd_init()
867 rxq = fep->rx_queue[q]; in fec_enet_bd_init()
868 bdp = rxq->bd.base; in fec_enet_bd_init()
870 for (i = 0; i < rxq->bd.ring_size; i++) { in fec_enet_bd_init()
873 if (bdp->cbd_bufaddr) in fec_enet_bd_init()
874 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); in fec_enet_bd_init()
876 bdp->cbd_sc = cpu_to_fec16(0); in fec_enet_bd_init()
877 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); in fec_enet_bd_init()
881 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); in fec_enet_bd_init()
882 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); in fec_enet_bd_init()
884 rxq->bd.cur = rxq->bd.base; in fec_enet_bd_init()
887 for (q = 0; q < fep->num_tx_queues; q++) { in fec_enet_bd_init()
889 txq = fep->tx_queue[q]; in fec_enet_bd_init()
890 bdp = txq->bd.base; in fec_enet_bd_init()
891 txq->bd.cur = bdp; in fec_enet_bd_init()
893 for (i = 0; i < txq->bd.ring_size; i++) { in fec_enet_bd_init()
895 bdp->cbd_sc = cpu_to_fec16(0); in fec_enet_bd_init()
896 if (bdp->cbd_bufaddr && in fec_enet_bd_init()
897 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) in fec_enet_bd_init()
898 dma_unmap_single(&fep->pdev->dev, in fec_enet_bd_init()
899 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_bd_init()
900 fec16_to_cpu(bdp->cbd_datlen), in fec_enet_bd_init()
902 if (txq->tx_skbuff[i]) { in fec_enet_bd_init()
903 dev_kfree_skb_any(txq->tx_skbuff[i]); in fec_enet_bd_init()
904 txq->tx_skbuff[i] = NULL; in fec_enet_bd_init()
906 bdp->cbd_bufaddr = cpu_to_fec32(0); in fec_enet_bd_init()
907 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_bd_init()
911 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); in fec_enet_bd_init()
912 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); in fec_enet_bd_init()
913 txq->dirty_tx = bdp; in fec_enet_bd_init()
922 for (i = 0; i < fep->num_rx_queues; i++) in fec_enet_active_rxring()
923 writel(0, fep->rx_queue[i]->bd.reg_desc_active); in fec_enet_active_rxring()
933 for (i = 0; i < fep->num_rx_queues; i++) { in fec_enet_enable_ring()
934 rxq = fep->rx_queue[i]; in fec_enet_enable_ring()
935 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); in fec_enet_enable_ring()
936 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); in fec_enet_enable_ring()
941 fep->hwp + FEC_RCMR(i)); in fec_enet_enable_ring()
944 for (i = 0; i < fep->num_tx_queues; i++) { in fec_enet_enable_ring()
945 txq = fep->tx_queue[i]; in fec_enet_enable_ring()
946 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); in fec_enet_enable_ring()
951 fep->hwp + FEC_DMA_CFG(i)); in fec_enet_enable_ring()
961 for (i = 0; i < fep->num_tx_queues; i++) { in fec_enet_reset_skb()
962 txq = fep->tx_queue[i]; in fec_enet_reset_skb()
964 for (j = 0; j < txq->bd.ring_size; j++) { in fec_enet_reset_skb()
965 if (txq->tx_skbuff[j]) { in fec_enet_reset_skb()
966 dev_kfree_skb_any(txq->tx_skbuff[j]); in fec_enet_reset_skb()
967 txq->tx_skbuff[j] = NULL; in fec_enet_reset_skb()
990 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || in fec_restart()
991 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { in fec_restart()
992 writel(0, fep->hwp + FEC_ECNTRL); in fec_restart()
994 writel(1, fep->hwp + FEC_ECNTRL); in fec_restart()
999 * enet-mac reset will reset mac address registers too, in fec_restart()
1002 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); in fec_restart()
1004 fep->hwp + FEC_ADDR_LOW); in fec_restart()
1006 fep->hwp + FEC_ADDR_HIGH); in fec_restart()
1009 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); in fec_restart()
1015 /* Reset tx SKB buffers. */ in fec_restart()
1019 if (fep->full_duplex == DUPLEX_FULL) { in fec_restart()
1021 writel(0x04, fep->hwp + FEC_X_CNTRL); in fec_restart()
1025 writel(0x0, fep->hwp + FEC_X_CNTRL); in fec_restart()
1029 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); in fec_restart()
1032 if (fep->quirks & FEC_QUIRK_HAS_RACC) { in fec_restart()
1033 u32 val = readl(fep->hwp + FEC_RACC); in fec_restart()
1037 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) in fec_restart()
1042 writel(val, fep->hwp + FEC_RACC); in fec_restart()
1043 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); in fec_restart()
1049 * differently on enet-mac. in fec_restart()
1051 if (fep->quirks & FEC_QUIRK_ENET_MAC) { in fec_restart()
1056 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || in fec_restart()
1057 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || in fec_restart()
1058 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || in fec_restart()
1059 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) in fec_restart()
1061 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) in fec_restart()
1066 /* 1G, 100M or 10M */ in fec_restart()
1067 if (ndev->phydev) { in fec_restart()
1068 if (ndev->phydev->speed == SPEED_1000) in fec_restart()
1070 else if (ndev->phydev->speed == SPEED_100) in fec_restart()
1077 if (fep->quirks & FEC_QUIRK_USE_GASKET) { in fec_restart()
1080 writel(0, fep->hwp + FEC_MIIGSK_ENR); in fec_restart()
1081 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) in fec_restart()
1089 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) in fec_restart()
1091 if (ndev->phydev && ndev->phydev->speed == SPEED_10) in fec_restart()
1093 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); in fec_restart()
1095 /* re-enable the gasket */ in fec_restart()
1096 writel(2, fep->hwp + FEC_MIIGSK_ENR); in fec_restart()
1103 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || in fec_restart()
1104 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && in fec_restart()
1105 ndev->phydev && ndev->phydev->pause)) { in fec_restart()
1109 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); in fec_restart()
1110 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); in fec_restart()
1111 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); in fec_restart()
1112 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); in fec_restart()
1115 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); in fec_restart()
1121 writel(rcntl, fep->hwp + FEC_R_CNTRL); in fec_restart()
1126 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); in fec_restart()
1127 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); in fec_restart()
1130 if (fep->quirks & FEC_QUIRK_ENET_MAC) { in fec_restart()
1134 writel(1 << 8, fep->hwp + FEC_X_WMRK); in fec_restart()
1137 if (fep->bufdesc_ex) in fec_restart()
1140 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && in fec_restart()
1141 fep->rgmii_txc_dly) in fec_restart()
1143 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT && in fec_restart()
1144 fep->rgmii_rxc_dly) in fec_restart()
1149 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); in fec_restart()
1153 writel(ecntl, fep->hwp + FEC_ECNTRL); in fec_restart()
1156 if (fep->bufdesc_ex) in fec_restart()
1160 if (fep->link) in fec_restart()
1161 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); in fec_restart()
1163 writel(0, fep->hwp + FEC_IMASK); in fec_restart()
1172 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; in fec_enet_stop_mode()
1173 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; in fec_enet_stop_mode()
1175 if (stop_gpr->gpr) { in fec_enet_stop_mode()
1177 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, in fec_enet_stop_mode()
1178 BIT(stop_gpr->bit), in fec_enet_stop_mode()
1179 BIT(stop_gpr->bit)); in fec_enet_stop_mode()
1181 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, in fec_enet_stop_mode()
1182 BIT(stop_gpr->bit), 0); in fec_enet_stop_mode()
1183 } else if (pdata && pdata->sleep_mode_enable) { in fec_enet_stop_mode()
1184 pdata->sleep_mode_enable(enabled); in fec_enet_stop_mode()
1192 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); in fec_stop()
1196 if (fep->link) { in fec_stop()
1197 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ in fec_stop()
1199 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) in fec_stop()
1207 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { in fec_stop()
1208 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { in fec_stop()
1209 writel(0, fep->hwp + FEC_ECNTRL); in fec_stop()
1211 writel(1, fep->hwp + FEC_ECNTRL); in fec_stop()
1214 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); in fec_stop()
1216 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); in fec_stop()
1217 val = readl(fep->hwp + FEC_ECNTRL); in fec_stop()
1219 writel(val, fep->hwp + FEC_ECNTRL); in fec_stop()
1222 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); in fec_stop()
1225 if (fep->quirks & FEC_QUIRK_ENET_MAC && in fec_stop()
1226 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { in fec_stop()
1227 writel(2, fep->hwp + FEC_ECNTRL); in fec_stop()
1228 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); in fec_stop()
1240 ndev->stats.tx_errors++; in fec_timeout()
1242 schedule_work(&fep->tx_timeout_work); in fec_timeout()
1249 struct net_device *ndev = fep->netdev; in fec_enet_timeout_work()
1253 napi_disable(&fep->napi); in fec_enet_timeout_work()
1258 napi_enable(&fep->napi); in fec_enet_timeout_work()
1270 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_enet_hwtstamp()
1271 ns = timecounter_cyc2time(&fep->tc, ts); in fec_enet_hwtstamp()
1272 spin_unlock_irqrestore(&fep->tmreg_lock, flags); in fec_enet_hwtstamp()
1275 hwtstamps->hwtstamp = ns_to_ktime(ns); in fec_enet_hwtstamp()
1292 txq = fep->tx_queue[queue_id]; in fec_enet_tx_queue()
1295 bdp = txq->dirty_tx; in fec_enet_tx_queue()
1298 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_tx_queue()
1300 while (bdp != READ_ONCE(txq->bd.cur)) { in fec_enet_tx_queue()
1303 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); in fec_enet_tx_queue()
1307 index = fec_enet_get_bd_index(bdp, &txq->bd); in fec_enet_tx_queue()
1309 skb = txq->tx_skbuff[index]; in fec_enet_tx_queue()
1310 txq->tx_skbuff[index] = NULL; in fec_enet_tx_queue()
1311 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) in fec_enet_tx_queue()
1312 dma_unmap_single(&fep->pdev->dev, in fec_enet_tx_queue()
1313 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_tx_queue()
1314 fec16_to_cpu(bdp->cbd_datlen), in fec_enet_tx_queue()
1316 bdp->cbd_bufaddr = cpu_to_fec32(0); in fec_enet_tx_queue()
1324 ndev->stats.tx_errors++; in fec_enet_tx_queue()
1326 ndev->stats.tx_heartbeat_errors++; in fec_enet_tx_queue()
1328 ndev->stats.tx_window_errors++; in fec_enet_tx_queue()
1330 ndev->stats.tx_aborted_errors++; in fec_enet_tx_queue()
1332 ndev->stats.tx_fifo_errors++; in fec_enet_tx_queue()
1334 ndev->stats.tx_carrier_errors++; in fec_enet_tx_queue()
1336 ndev->stats.tx_packets++; in fec_enet_tx_queue()
1337 ndev->stats.tx_bytes += skb->len; in fec_enet_tx_queue()
1344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && in fec_enet_tx_queue()
1345 fep->hwts_tx_en) && in fec_enet_tx_queue()
1346 fep->bufdesc_ex) { in fec_enet_tx_queue()
1350 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); in fec_enet_tx_queue()
1358 ndev->stats.collisions++; in fec_enet_tx_queue()
1367 txq->dirty_tx = bdp; in fec_enet_tx_queue()
1370 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_tx_queue()
1376 if (entries_free >= txq->tx_wake_threshold) in fec_enet_tx_queue()
1382 if (bdp != txq->bd.cur && in fec_enet_tx_queue()
1383 readl(txq->bd.reg_desc_active) == 0) in fec_enet_tx_queue()
1384 writel(0, txq->bd.reg_desc_active); in fec_enet_tx_queue()
1393 for (i = fep->num_tx_queues - 1; i >= 0; i--) in fec_enet_tx()
1403 off = ((unsigned long)skb->data) & fep->rx_align; in fec_enet_new_rxbdp()
1405 skb_reserve(skb, fep->rx_align + 1 - off); in fec_enet_new_rxbdp()
1407 …bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fe… in fec_enet_new_rxbdp()
1408 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { in fec_enet_new_rxbdp()
1411 return -ENOMEM; in fec_enet_new_rxbdp()
1423 if (length > fep->rx_copybreak) in fec_enet_copybreak()
1430 dma_sync_single_for_cpu(&fep->pdev->dev, in fec_enet_copybreak()
1431 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_copybreak()
1432 FEC_ENET_RX_FRSIZE - fep->rx_align, in fec_enet_copybreak()
1435 memcpy(new_skb->data, (*skb)->data, length); in fec_enet_copybreak()
1437 swap_buffer2(new_skb->data, (*skb)->data, length); in fec_enet_copybreak()
1465 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; in fec_enet_rx_queue()
1470 rxq = fep->rx_queue[queue_id]; in fec_enet_rx_queue()
1475 bdp = rxq->bd.cur; in fec_enet_rx_queue()
1477 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { in fec_enet_rx_queue()
1483 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT); in fec_enet_rx_queue()
1490 ndev->stats.rx_errors++; in fec_enet_rx_queue()
1493 ndev->stats.rx_fifo_errors++; in fec_enet_rx_queue()
1499 ndev->stats.rx_length_errors++; in fec_enet_rx_queue()
1504 ndev->stats.rx_crc_errors++; in fec_enet_rx_queue()
1507 ndev->stats.rx_frame_errors++; in fec_enet_rx_queue()
1512 ndev->stats.rx_packets++; in fec_enet_rx_queue()
1513 pkt_len = fec16_to_cpu(bdp->cbd_datlen); in fec_enet_rx_queue()
1514 ndev->stats.rx_bytes += pkt_len; in fec_enet_rx_queue()
1516 index = fec_enet_get_bd_index(bdp, &rxq->bd); in fec_enet_rx_queue()
1517 skb = rxq->rx_skbuff[index]; in fec_enet_rx_queue()
1523 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, in fec_enet_rx_queue()
1528 ndev->stats.rx_dropped++; in fec_enet_rx_queue()
1531 dma_unmap_single(&fep->pdev->dev, in fec_enet_rx_queue()
1532 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_rx_queue()
1533 FEC_ENET_RX_FRSIZE - fep->rx_align, in fec_enet_rx_queue()
1537 prefetch(skb->data - NET_IP_ALIGN); in fec_enet_rx_queue()
1538 skb_put(skb, pkt_len - 4); in fec_enet_rx_queue()
1539 data = skb->data; in fec_enet_rx_queue()
1545 if (fep->quirks & FEC_QUIRK_HAS_RACC) in fec_enet_rx_queue()
1551 if (fep->bufdesc_ex) in fec_enet_rx_queue()
1556 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && in fec_enet_rx_queue()
1557 fep->bufdesc_ex && in fec_enet_rx_queue()
1558 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { in fec_enet_rx_queue()
1562 vlan_tag = ntohs(vlan_header->h_vlan_TCI); in fec_enet_rx_queue()
1566 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); in fec_enet_rx_queue()
1570 skb->protocol = eth_type_trans(skb, ndev); in fec_enet_rx_queue()
1573 if (fep->hwts_rx_en && fep->bufdesc_ex) in fec_enet_rx_queue()
1574 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), in fec_enet_rx_queue()
1577 if (fep->bufdesc_ex && in fec_enet_rx_queue()
1578 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { in fec_enet_rx_queue()
1579 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { in fec_enet_rx_queue()
1581 skb->ip_summed = CHECKSUM_UNNECESSARY; in fec_enet_rx_queue()
1594 napi_gro_receive(&fep->napi, skb); in fec_enet_rx_queue()
1597 dma_sync_single_for_device(&fep->pdev->dev, in fec_enet_rx_queue()
1598 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_rx_queue()
1599 FEC_ENET_RX_FRSIZE - fep->rx_align, in fec_enet_rx_queue()
1602 rxq->rx_skbuff[index] = skb_new; in fec_enet_rx_queue()
1613 if (fep->bufdesc_ex) { in fec_enet_rx_queue()
1616 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); in fec_enet_rx_queue()
1617 ebdp->cbd_prot = 0; in fec_enet_rx_queue()
1618 ebdp->cbd_bdu = 0; in fec_enet_rx_queue()
1624 bdp->cbd_sc = cpu_to_fec16(status); in fec_enet_rx_queue()
1627 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); in fec_enet_rx_queue()
1633 writel(0, rxq->bd.reg_desc_active); in fec_enet_rx_queue()
1635 rxq->bd.cur = bdp; in fec_enet_rx_queue()
1645 for (i = fep->num_rx_queues - 1; i >= 0; i--) in fec_enet_rx()
1646 done += fec_enet_rx_queue(ndev, budget - done, i); in fec_enet_rx()
1655 int_events = readl(fep->hwp + FEC_IEVENT); in fec_enet_collect_events()
1660 writel(int_events, fep->hwp + FEC_IEVENT); in fec_enet_collect_events()
1672 if (fec_enet_collect_events(fep) && fep->link) { in fec_enet_interrupt()
1675 if (napi_schedule_prep(&fep->napi)) { in fec_enet_interrupt()
1677 writel(0, fep->hwp + FEC_IMASK); in fec_enet_interrupt()
1678 __napi_schedule(&fep->napi); in fec_enet_interrupt()
1687 struct net_device *ndev = napi->dev; in fec_enet_rx_napi()
1692 done += fec_enet_rx(ndev, budget - done); in fec_enet_rx_napi()
1698 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); in fec_enet_rx_napi()
1704 /* ------------------------------------------------------------------------- */
1723 struct device_node *np = fep->pdev->dev.of_node; in fec_get_mac()
1728 else if (ret == -EPROBE_DEFER) in fec_get_mac()
1741 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); in fec_get_mac()
1744 iap = (unsigned char *)&pdata->mac; in fec_get_mac()
1753 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); in fec_get_mac()
1755 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); in fec_get_mac()
1764 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); in fec_get_mac()
1766 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", in fec_get_mac()
1767 ndev->dev_addr); in fec_get_mac()
1771 memcpy(ndev->dev_addr, iap, ETH_ALEN); in fec_get_mac()
1775 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; in fec_get_mac()
1780 /* ------------------------------------------------------------------------- */
1788 struct phy_device *phy_dev = ndev->phydev; in fec_enet_adjust_link()
1797 fep->link = 0; in fec_enet_adjust_link()
1798 } else if (phy_dev->link) { in fec_enet_adjust_link()
1799 if (!fep->link) { in fec_enet_adjust_link()
1800 fep->link = phy_dev->link; in fec_enet_adjust_link()
1804 if (fep->full_duplex != phy_dev->duplex) { in fec_enet_adjust_link()
1805 fep->full_duplex = phy_dev->duplex; in fec_enet_adjust_link()
1809 if (phy_dev->speed != fep->speed) { in fec_enet_adjust_link()
1810 fep->speed = phy_dev->speed; in fec_enet_adjust_link()
1816 napi_disable(&fep->napi); in fec_enet_adjust_link()
1821 napi_enable(&fep->napi); in fec_enet_adjust_link()
1824 if (fep->link) { in fec_enet_adjust_link()
1825 napi_disable(&fep->napi); in fec_enet_adjust_link()
1829 napi_enable(&fep->napi); in fec_enet_adjust_link()
1830 fep->link = phy_dev->link; in fec_enet_adjust_link()
1844 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, in fec_enet_mdio_wait()
1848 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); in fec_enet_mdio_wait()
1855 struct fec_enet_private *fep = bus->priv; in fec_enet_mdio_read()
1856 struct device *dev = &fep->pdev->dev; in fec_enet_mdio_read()
1872 fep->hwp + FEC_MII_DATA); in fec_enet_mdio_read()
1877 netdev_err(fep->netdev, "MDIO address write timeout\n"); in fec_enet_mdio_read()
1893 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); in fec_enet_mdio_read()
1898 netdev_err(fep->netdev, "MDIO read timeout\n"); in fec_enet_mdio_read()
1902 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); in fec_enet_mdio_read()
1914 struct fec_enet_private *fep = bus->priv; in fec_enet_mdio_write()
1915 struct device *dev = &fep->pdev->dev; in fec_enet_mdio_write()
1931 fep->hwp + FEC_MII_DATA); in fec_enet_mdio_write()
1936 netdev_err(fep->netdev, "MDIO address write timeout\n"); in fec_enet_mdio_write()
1949 fep->hwp + FEC_MII_DATA); in fec_enet_mdio_write()
1954 netdev_err(fep->netdev, "MDIO write timeout\n"); in fec_enet_mdio_write()
1966 struct phy_device *phy_dev = ndev->phydev; in fec_enet_phy_reset_after_clk_enable()
1970 } else if (fep->phy_node) { in fec_enet_phy_reset_after_clk_enable()
1978 phy_dev = of_phy_find_device(fep->phy_node); in fec_enet_phy_reset_after_clk_enable()
1980 put_device(&phy_dev->mdio.dev); in fec_enet_phy_reset_after_clk_enable()
1990 ret = clk_prepare_enable(fep->clk_enet_out); in fec_enet_clk_enable()
1994 if (fep->clk_ptp) { in fec_enet_clk_enable()
1995 mutex_lock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
1996 ret = clk_prepare_enable(fep->clk_ptp); in fec_enet_clk_enable()
1998 mutex_unlock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2001 fep->ptp_clk_on = true; in fec_enet_clk_enable()
2003 mutex_unlock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2006 ret = clk_prepare_enable(fep->clk_ref); in fec_enet_clk_enable()
2010 ret = clk_prepare_enable(fep->clk_2x_txclk); in fec_enet_clk_enable()
2016 clk_disable_unprepare(fep->clk_enet_out); in fec_enet_clk_enable()
2017 if (fep->clk_ptp) { in fec_enet_clk_enable()
2018 mutex_lock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2019 clk_disable_unprepare(fep->clk_ptp); in fec_enet_clk_enable()
2020 fep->ptp_clk_on = false; in fec_enet_clk_enable()
2021 mutex_unlock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2023 clk_disable_unprepare(fep->clk_ref); in fec_enet_clk_enable()
2024 clk_disable_unprepare(fep->clk_2x_txclk); in fec_enet_clk_enable()
2030 if (fep->clk_ref) in fec_enet_clk_enable()
2031 clk_disable_unprepare(fep->clk_ref); in fec_enet_clk_enable()
2033 if (fep->clk_ptp) { in fec_enet_clk_enable()
2034 mutex_lock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2035 clk_disable_unprepare(fep->clk_ptp); in fec_enet_clk_enable()
2036 fep->ptp_clk_on = false; in fec_enet_clk_enable()
2037 mutex_unlock(&fep->ptp_clk_mutex); in fec_enet_clk_enable()
2040 clk_disable_unprepare(fep->clk_enet_out); in fec_enet_clk_enable()
2050 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */ in fec_enet_parse_rgmii_delay()
2051 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) { in fec_enet_parse_rgmii_delay()
2053 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps"); in fec_enet_parse_rgmii_delay()
2054 return -EINVAL; in fec_enet_parse_rgmii_delay()
2056 fep->rgmii_txc_dly = true; in fec_enet_parse_rgmii_delay()
2061 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) { in fec_enet_parse_rgmii_delay()
2063 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps"); in fec_enet_parse_rgmii_delay()
2064 return -EINVAL; in fec_enet_parse_rgmii_delay()
2066 fep->rgmii_rxc_dly = true; in fec_enet_parse_rgmii_delay()
2080 int dev_id = fep->dev_id; in fec_enet_mii_probe()
2082 if (fep->phy_node) { in fec_enet_mii_probe()
2083 phy_dev = of_phy_connect(ndev, fep->phy_node, in fec_enet_mii_probe()
2085 fep->phy_interface); in fec_enet_mii_probe()
2088 return -ENODEV; in fec_enet_mii_probe()
2093 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) in fec_enet_mii_probe()
2095 if (dev_id--) in fec_enet_mii_probe()
2097 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); in fec_enet_mii_probe()
2103 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); in fec_enet_mii_probe()
2110 fep->phy_interface); in fec_enet_mii_probe()
2119 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { in fec_enet_mii_probe()
2128 phy_set_max_speed(phy_dev, 100); in fec_enet_mii_probe()
2130 fep->link = 0; in fec_enet_mii_probe()
2131 fep->full_duplex = 0; in fec_enet_mii_probe()
2133 phy_dev->mac_managed_pm = 1; in fec_enet_mii_probe()
2147 int err = -ENXIO; in fec_enet_mii_init()
2155 * - fec0 supports MII & RMII modes while fec1 only supports RMII in fec_enet_mii_init()
2156 * - fec0 acts as the 1588 time master while fec1 is slave in fec_enet_mii_init()
2157 * - external phys can only be configured by fec0 in fec_enet_mii_init()
2167 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { in fec_enet_mii_init()
2170 fep->mii_bus = fec0_mii_bus; in fec_enet_mii_init()
2174 return -ENOENT; in fec_enet_mii_init()
2178 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); in fec_enet_mii_init()
2180 of_property_read_u32(node, "clock-frequency", &bus_freq); in fec_enet_mii_init()
2182 "suppress-preamble"); in fec_enet_mii_init()
2189 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 in fec_enet_mii_init()
2193 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); in fec_enet_mii_init()
2194 if (fep->quirks & FEC_QUIRK_ENET_MAC) in fec_enet_mii_init()
2195 mii_speed--; in fec_enet_mii_init()
2197 dev_err(&pdev->dev, in fec_enet_mii_init()
2199 clk_get_rate(fep->clk_ipg)); in fec_enet_mii_init()
2200 err = -EINVAL; in fec_enet_mii_init()
2216 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; in fec_enet_mii_init()
2218 fep->phy_speed = mii_speed << 1 | holdtime << 8; in fec_enet_mii_init()
2221 fep->phy_speed |= BIT(7); in fec_enet_mii_init()
2223 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { in fec_enet_mii_init()
2226 * - writing MSCR: in fec_enet_mii_init()
2227 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & in fec_enet_mii_init()
2229 * - writing MMFR: in fec_enet_mii_init()
2230 * - mscr[7:0]_not_zero in fec_enet_mii_init()
2232 writel(0, fep->hwp + FEC_MII_DATA); in fec_enet_mii_init()
2235 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); in fec_enet_mii_init()
2238 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); in fec_enet_mii_init()
2240 fep->mii_bus = mdiobus_alloc(); in fec_enet_mii_init()
2241 if (fep->mii_bus == NULL) { in fec_enet_mii_init()
2242 err = -ENOMEM; in fec_enet_mii_init()
2246 fep->mii_bus->name = "fec_enet_mii_bus"; in fec_enet_mii_init()
2247 fep->mii_bus->read = fec_enet_mdio_read; in fec_enet_mii_init()
2248 fep->mii_bus->write = fec_enet_mdio_write; in fec_enet_mii_init()
2249 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", in fec_enet_mii_init()
2250 pdev->name, fep->dev_id + 1); in fec_enet_mii_init()
2251 fep->mii_bus->priv = fep; in fec_enet_mii_init()
2252 fep->mii_bus->parent = &pdev->dev; in fec_enet_mii_init()
2254 err = of_mdiobus_register(fep->mii_bus, node); in fec_enet_mii_init()
2262 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) in fec_enet_mii_init()
2263 fec0_mii_bus = fep->mii_bus; in fec_enet_mii_init()
2268 mdiobus_free(fep->mii_bus); in fec_enet_mii_init()
2276 if (--mii_cnt == 0) { in fec_enet_mii_remove()
2277 mdiobus_unregister(fep->mii_bus); in fec_enet_mii_remove()
2278 mdiobus_free(fep->mii_bus); in fec_enet_mii_remove()
2287 strlcpy(info->driver, fep->pdev->dev.driver->name, in fec_enet_get_drvinfo()
2288 sizeof(info->driver)); in fec_enet_get_drvinfo()
2289 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); in fec_enet_get_drvinfo()
2298 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); in fec_enet_get_regs_len()
2358 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; in fec_enet_get_regs()
2359 struct device *dev = &fep->pdev->dev; in fec_enet_get_regs()
2368 regs->version = fec_enet_register_version; in fec_enet_get_regs()
2370 memset(buf, 0, regs->len); in fec_enet_get_regs()
2376 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) in fec_enet_get_regs()
2392 if (fep->bufdesc_ex) { in fec_enet_get_ts_info()
2394 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in fec_enet_get_ts_info()
2400 if (fep->ptp_clock) in fec_enet_get_ts_info()
2401 info->phc_index = ptp_clock_index(fep->ptp_clock); in fec_enet_get_ts_info()
2403 info->phc_index = -1; in fec_enet_get_ts_info()
2405 info->tx_types = (1 << HWTSTAMP_TX_OFF) | in fec_enet_get_ts_info()
2408 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in fec_enet_get_ts_info()
2423 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; in fec_enet_get_pauseparam()
2424 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; in fec_enet_get_pauseparam()
2425 pause->rx_pause = pause->tx_pause; in fec_enet_get_pauseparam()
2433 if (!ndev->phydev) in fec_enet_set_pauseparam()
2434 return -ENODEV; in fec_enet_set_pauseparam()
2436 if (pause->tx_pause != pause->rx_pause) { in fec_enet_set_pauseparam()
2438 "hardware only support enable/disable both tx and rx"); in fec_enet_set_pauseparam()
2439 return -EINVAL; in fec_enet_set_pauseparam()
2442 fep->pause_flag = 0; in fec_enet_set_pauseparam()
2444 /* tx pause must be same as rx pause */ in fec_enet_set_pauseparam()
2445 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; in fec_enet_set_pauseparam()
2446 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; in fec_enet_set_pauseparam()
2448 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, in fec_enet_set_pauseparam()
2449 pause->autoneg); in fec_enet_set_pauseparam()
2451 if (pause->autoneg) { in fec_enet_set_pauseparam()
2454 phy_start_aneg(ndev->phydev); in fec_enet_set_pauseparam()
2457 napi_disable(&fep->napi); in fec_enet_set_pauseparam()
2462 napi_enable(&fep->napi); in fec_enet_set_pauseparam()
2472 /* RMON TX */
2492 /* IEEE TX */
2542 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); in fec_enet_update_ethtool_stats()
2553 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); in fec_enet_get_ethtool_stats()
2580 return -EOPNOTSUPP; in fec_enet_get_sset_count()
2590 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); in fec_enet_clear_ethtool_stats()
2593 writel(0, fep->hwp + fec_stats[i].offset); in fec_enet_clear_ethtool_stats()
2596 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); in fec_enet_clear_ethtool_stats()
2618 return us * (fep->itr_clk_rate / 64000) / 1000; in fec_enet_us_to_itr_clock()
2628 if (!fep->rx_time_itr || !fep->rx_pkts_itr || in fec_enet_itr_coal_set()
2629 !fep->tx_time_itr || !fep->tx_pkts_itr) in fec_enet_itr_coal_set()
2639 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); in fec_enet_itr_coal_set()
2640 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); in fec_enet_itr_coal_set()
2641 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); in fec_enet_itr_coal_set()
2642 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); in fec_enet_itr_coal_set()
2647 writel(tx_itr, fep->hwp + FEC_TXIC0); in fec_enet_itr_coal_set()
2648 writel(rx_itr, fep->hwp + FEC_RXIC0); in fec_enet_itr_coal_set()
2649 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { in fec_enet_itr_coal_set()
2650 writel(tx_itr, fep->hwp + FEC_TXIC1); in fec_enet_itr_coal_set()
2651 writel(rx_itr, fep->hwp + FEC_RXIC1); in fec_enet_itr_coal_set()
2652 writel(tx_itr, fep->hwp + FEC_TXIC2); in fec_enet_itr_coal_set()
2653 writel(rx_itr, fep->hwp + FEC_RXIC2); in fec_enet_itr_coal_set()
2664 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) in fec_enet_get_coalesce()
2665 return -EOPNOTSUPP; in fec_enet_get_coalesce()
2667 ec->rx_coalesce_usecs = fep->rx_time_itr; in fec_enet_get_coalesce()
2668 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; in fec_enet_get_coalesce()
2670 ec->tx_coalesce_usecs = fep->tx_time_itr; in fec_enet_get_coalesce()
2671 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; in fec_enet_get_coalesce()
2682 struct device *dev = &fep->pdev->dev; in fec_enet_set_coalesce()
2685 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) in fec_enet_set_coalesce()
2686 return -EOPNOTSUPP; in fec_enet_set_coalesce()
2688 if (ec->rx_max_coalesced_frames > 255) { in fec_enet_set_coalesce()
2690 return -EINVAL; in fec_enet_set_coalesce()
2693 if (ec->tx_max_coalesced_frames > 255) { in fec_enet_set_coalesce()
2694 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); in fec_enet_set_coalesce()
2695 return -EINVAL; in fec_enet_set_coalesce()
2698 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); in fec_enet_set_coalesce()
2701 return -EINVAL; in fec_enet_set_coalesce()
2704 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); in fec_enet_set_coalesce()
2706 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); in fec_enet_set_coalesce()
2707 return -EINVAL; in fec_enet_set_coalesce()
2710 fep->rx_time_itr = ec->rx_coalesce_usecs; in fec_enet_set_coalesce()
2711 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; in fec_enet_set_coalesce()
2713 fep->tx_time_itr = ec->tx_coalesce_usecs; in fec_enet_set_coalesce()
2714 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; in fec_enet_set_coalesce()
2741 switch (tuna->id) { in fec_enet_get_tunable()
2743 *(u32 *)data = fep->rx_copybreak; in fec_enet_get_tunable()
2746 ret = -EINVAL; in fec_enet_get_tunable()
2760 switch (tuna->id) { in fec_enet_set_tunable()
2762 fep->rx_copybreak = *(u32 *)data; in fec_enet_set_tunable()
2765 ret = -EINVAL; in fec_enet_set_tunable()
2772 /* LPI Sleep Ts count base on tx clk (clk_ref).
2779 return us * (fep->clk_ref_rate / 1000) / 1000; in fec_enet_us_to_tx_cycle()
2785 struct ethtool_eee *p = &fep->eee; in fec_enet_eee_mode_set()
2790 ret = phy_init_eee(ndev->phydev, 0); in fec_enet_eee_mode_set()
2794 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer); in fec_enet_eee_mode_set()
2801 p->tx_lpi_enabled = enable; in fec_enet_eee_mode_set()
2802 p->eee_enabled = enable; in fec_enet_eee_mode_set()
2803 p->eee_active = enable; in fec_enet_eee_mode_set()
2805 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); in fec_enet_eee_mode_set()
2806 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); in fec_enet_eee_mode_set()
2815 struct ethtool_eee *p = &fep->eee; in fec_enet_get_eee()
2817 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) in fec_enet_get_eee()
2818 return -EOPNOTSUPP; in fec_enet_get_eee()
2821 return -ENETDOWN; in fec_enet_get_eee()
2823 edata->eee_enabled = p->eee_enabled; in fec_enet_get_eee()
2824 edata->eee_active = p->eee_active; in fec_enet_get_eee()
2825 edata->tx_lpi_timer = p->tx_lpi_timer; in fec_enet_get_eee()
2826 edata->tx_lpi_enabled = p->tx_lpi_enabled; in fec_enet_get_eee()
2828 return phy_ethtool_get_eee(ndev->phydev, edata); in fec_enet_get_eee()
2835 struct ethtool_eee *p = &fep->eee; in fec_enet_set_eee()
2838 if (!(fep->quirks & FEC_QUIRK_HAS_EEE)) in fec_enet_set_eee()
2839 return -EOPNOTSUPP; in fec_enet_set_eee()
2842 return -ENETDOWN; in fec_enet_set_eee()
2844 p->tx_lpi_timer = edata->tx_lpi_timer; in fec_enet_set_eee()
2846 if (!edata->eee_enabled || !edata->tx_lpi_enabled || in fec_enet_set_eee()
2847 !edata->tx_lpi_timer) in fec_enet_set_eee()
2855 return phy_ethtool_set_eee(ndev->phydev, edata); in fec_enet_set_eee()
2863 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { in fec_enet_get_wol()
2864 wol->supported = WAKE_MAGIC; in fec_enet_get_wol()
2865 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; in fec_enet_get_wol()
2867 wol->supported = wol->wolopts = 0; in fec_enet_get_wol()
2876 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) in fec_enet_set_wol()
2877 return -EINVAL; in fec_enet_set_wol()
2879 if (wol->wolopts & ~WAKE_MAGIC) in fec_enet_set_wol()
2880 return -EINVAL; in fec_enet_set_wol()
2882 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); in fec_enet_set_wol()
2883 if (device_may_wakeup(&ndev->dev)) { in fec_enet_set_wol()
2884 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; in fec_enet_set_wol()
2885 if (fep->wake_irq > 0) in fec_enet_set_wol()
2886 enable_irq_wake(fep->wake_irq); in fec_enet_set_wol()
2888 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); in fec_enet_set_wol()
2889 if (fep->wake_irq > 0) in fec_enet_set_wol()
2890 disable_irq_wake(fep->wake_irq); in fec_enet_set_wol()
2928 struct phy_device *phydev = ndev->phydev; in fec_enet_ioctl()
2931 return -EINVAL; in fec_enet_ioctl()
2934 return -ENODEV; in fec_enet_ioctl()
2936 if (fep->bufdesc_ex) { in fec_enet_ioctl()
2962 for (q = 0; q < fep->num_rx_queues; q++) { in fec_enet_free_buffers()
2963 rxq = fep->rx_queue[q]; in fec_enet_free_buffers()
2964 bdp = rxq->bd.base; in fec_enet_free_buffers()
2965 for (i = 0; i < rxq->bd.ring_size; i++) { in fec_enet_free_buffers()
2966 skb = rxq->rx_skbuff[i]; in fec_enet_free_buffers()
2967 rxq->rx_skbuff[i] = NULL; in fec_enet_free_buffers()
2969 dma_unmap_single(&fep->pdev->dev, in fec_enet_free_buffers()
2970 fec32_to_cpu(bdp->cbd_bufaddr), in fec_enet_free_buffers()
2971 FEC_ENET_RX_FRSIZE - fep->rx_align, in fec_enet_free_buffers()
2975 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); in fec_enet_free_buffers()
2979 for (q = 0; q < fep->num_tx_queues; q++) { in fec_enet_free_buffers()
2980 txq = fep->tx_queue[q]; in fec_enet_free_buffers()
2981 for (i = 0; i < txq->bd.ring_size; i++) { in fec_enet_free_buffers()
2982 kfree(txq->tx_bounce[i]); in fec_enet_free_buffers()
2983 txq->tx_bounce[i] = NULL; in fec_enet_free_buffers()
2984 skb = txq->tx_skbuff[i]; in fec_enet_free_buffers()
2985 txq->tx_skbuff[i] = NULL; in fec_enet_free_buffers()
2997 for (i = 0; i < fep->num_tx_queues; i++) in fec_enet_free_queue()
2998 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { in fec_enet_free_queue()
2999 txq = fep->tx_queue[i]; in fec_enet_free_queue()
3000 dma_free_coherent(&fep->pdev->dev, in fec_enet_free_queue()
3001 txq->bd.ring_size * TSO_HEADER_SIZE, in fec_enet_free_queue()
3002 txq->tso_hdrs, in fec_enet_free_queue()
3003 txq->tso_hdrs_dma); in fec_enet_free_queue()
3006 for (i = 0; i < fep->num_rx_queues; i++) in fec_enet_free_queue()
3007 kfree(fep->rx_queue[i]); in fec_enet_free_queue()
3008 for (i = 0; i < fep->num_tx_queues; i++) in fec_enet_free_queue()
3009 kfree(fep->tx_queue[i]); in fec_enet_free_queue()
3019 for (i = 0; i < fep->num_tx_queues; i++) { in fec_enet_alloc_queue()
3022 ret = -ENOMEM; in fec_enet_alloc_queue()
3026 fep->tx_queue[i] = txq; in fec_enet_alloc_queue()
3027 txq->bd.ring_size = TX_RING_SIZE; in fec_enet_alloc_queue()
3028 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; in fec_enet_alloc_queue()
3030 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; in fec_enet_alloc_queue()
3031 txq->tx_wake_threshold = in fec_enet_alloc_queue()
3032 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; in fec_enet_alloc_queue()
3034 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, in fec_enet_alloc_queue()
3035 txq->bd.ring_size * TSO_HEADER_SIZE, in fec_enet_alloc_queue()
3036 &txq->tso_hdrs_dma, in fec_enet_alloc_queue()
3038 if (!txq->tso_hdrs) { in fec_enet_alloc_queue()
3039 ret = -ENOMEM; in fec_enet_alloc_queue()
3044 for (i = 0; i < fep->num_rx_queues; i++) { in fec_enet_alloc_queue()
3045 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), in fec_enet_alloc_queue()
3047 if (!fep->rx_queue[i]) { in fec_enet_alloc_queue()
3048 ret = -ENOMEM; in fec_enet_alloc_queue()
3052 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; in fec_enet_alloc_queue()
3053 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; in fec_enet_alloc_queue()
3071 rxq = fep->rx_queue[queue]; in fec_enet_alloc_rxq_buffers()
3072 bdp = rxq->bd.base; in fec_enet_alloc_rxq_buffers()
3073 for (i = 0; i < rxq->bd.ring_size; i++) { in fec_enet_alloc_rxq_buffers()
3083 rxq->rx_skbuff[i] = skb; in fec_enet_alloc_rxq_buffers()
3084 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); in fec_enet_alloc_rxq_buffers()
3086 if (fep->bufdesc_ex) { in fec_enet_alloc_rxq_buffers()
3088 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); in fec_enet_alloc_rxq_buffers()
3091 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); in fec_enet_alloc_rxq_buffers()
3095 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); in fec_enet_alloc_rxq_buffers()
3096 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); in fec_enet_alloc_rxq_buffers()
3101 return -ENOMEM; in fec_enet_alloc_rxq_buffers()
3112 txq = fep->tx_queue[queue]; in fec_enet_alloc_txq_buffers()
3113 bdp = txq->bd.base; in fec_enet_alloc_txq_buffers()
3114 for (i = 0; i < txq->bd.ring_size; i++) { in fec_enet_alloc_txq_buffers()
3115 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); in fec_enet_alloc_txq_buffers()
3116 if (!txq->tx_bounce[i]) in fec_enet_alloc_txq_buffers()
3119 bdp->cbd_sc = cpu_to_fec16(0); in fec_enet_alloc_txq_buffers()
3120 bdp->cbd_bufaddr = cpu_to_fec32(0); in fec_enet_alloc_txq_buffers()
3122 if (fep->bufdesc_ex) { in fec_enet_alloc_txq_buffers()
3124 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); in fec_enet_alloc_txq_buffers()
3127 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); in fec_enet_alloc_txq_buffers()
3131 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); in fec_enet_alloc_txq_buffers()
3132 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); in fec_enet_alloc_txq_buffers()
3138 return -ENOMEM; in fec_enet_alloc_txq_buffers()
3146 for (i = 0; i < fep->num_rx_queues; i++) in fec_enet_alloc_buffers()
3148 return -ENOMEM; in fec_enet_alloc_buffers()
3150 for (i = 0; i < fep->num_tx_queues; i++) in fec_enet_alloc_buffers()
3152 return -ENOMEM; in fec_enet_alloc_buffers()
3163 ret = pm_runtime_resume_and_get(&fep->pdev->dev); in fec_enet_open()
3167 pinctrl_pm_select_default_state(&fep->pdev->dev); in fec_enet_open()
3178 if (ndev->phydev && ndev->phydev->drv) in fec_enet_open()
3205 if (fep->quirks & FEC_QUIRK_ERR006687) in fec_enet_open()
3208 napi_enable(&fep->napi); in fec_enet_open()
3209 phy_start(ndev->phydev); in fec_enet_open()
3212 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & in fec_enet_open()
3222 pm_runtime_mark_last_busy(&fep->pdev->dev); in fec_enet_open()
3223 pm_runtime_put_autosuspend(&fep->pdev->dev); in fec_enet_open()
3224 pinctrl_pm_select_sleep_state(&fep->pdev->dev); in fec_enet_open()
3233 phy_stop(ndev->phydev); in fec_enet_close()
3236 napi_disable(&fep->napi); in fec_enet_close()
3241 phy_disconnect(ndev->phydev); in fec_enet_close()
3243 if (fep->quirks & FEC_QUIRK_ERR006687) in fec_enet_close()
3249 pinctrl_pm_select_sleep_state(&fep->pdev->dev); in fec_enet_close()
3250 pm_runtime_mark_last_busy(&fep->pdev->dev); in fec_enet_close()
3251 pm_runtime_put_autosuspend(&fep->pdev->dev); in fec_enet_close()
3278 if (ndev->flags & IFF_PROMISC) { in set_multicast_list()
3279 tmp = readl(fep->hwp + FEC_R_CNTRL); in set_multicast_list()
3281 writel(tmp, fep->hwp + FEC_R_CNTRL); in set_multicast_list()
3285 tmp = readl(fep->hwp + FEC_R_CNTRL); in set_multicast_list()
3287 writel(tmp, fep->hwp + FEC_R_CNTRL); in set_multicast_list()
3289 if (ndev->flags & IFF_ALLMULTI) { in set_multicast_list()
3293 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); in set_multicast_list()
3294 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); in set_multicast_list()
3302 crc = ether_crc_le(ndev->addr_len, ha->addr); in set_multicast_list()
3307 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; in set_multicast_list()
3310 hash_high |= 1 << (hash - 32); in set_multicast_list()
3315 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); in set_multicast_list()
3316 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); in set_multicast_list()
3327 if (!is_valid_ether_addr(addr->sa_data)) in fec_set_mac_address()
3328 return -EADDRNOTAVAIL; in fec_set_mac_address()
3329 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); in fec_set_mac_address()
3340 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | in fec_set_mac_address()
3341 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), in fec_set_mac_address()
3342 fep->hwp + FEC_ADDR_LOW); in fec_set_mac_address()
3343 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), in fec_set_mac_address()
3344 fep->hwp + FEC_ADDR_HIGH); in fec_set_mac_address()
3350 * fec_poll_controller - FEC Poll controller function
3362 if (fep->irq[i] > 0) { in fec_poll_controller()
3363 disable_irq(fep->irq[i]); in fec_poll_controller()
3364 fec_enet_interrupt(fep->irq[i], dev); in fec_poll_controller()
3365 enable_irq(fep->irq[i]); in fec_poll_controller()
3375 netdev_features_t changed = features ^ netdev->features; in fec_enet_set_netdev_features()
3377 netdev->features = features; in fec_enet_set_netdev_features()
3382 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; in fec_enet_set_netdev_features()
3384 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; in fec_enet_set_netdev_features()
3392 netdev_features_t changed = features ^ netdev->features; in fec_set_features()
3395 napi_disable(&fep->napi); in fec_set_features()
3402 napi_enable(&fep->napi); in fec_set_features()
3415 if (skb->protocol == htons(ETH_P_ALL)) { in fec_enet_get_raw_vlan_tci()
3416 vhdr = (struct vlan_ethhdr *)(skb->data); in fec_enet_get_raw_vlan_tci()
3417 vlan_TCI = ntohs(vhdr->h_vlan_TCI); in fec_enet_get_raw_vlan_tci()
3429 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) in fec_enet_select_queue()
3474 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : in fec_enet_init()
3481 fep->rx_align = 0xf; in fec_enet_init()
3482 fep->tx_align = 0xf; in fec_enet_init()
3484 fep->rx_align = 0x3; in fec_enet_init()
3485 fep->tx_align = 0x3; in fec_enet_init()
3489 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); in fec_enet_init()
3491 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); in fec_enet_init()
3499 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; in fec_enet_init()
3502 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, in fec_enet_init()
3505 ret = -ENOMEM; in fec_enet_init()
3518 for (i = 0; i < fep->num_rx_queues; i++) { in fec_enet_init()
3519 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; in fec_enet_init()
3520 unsigned size = dsize * rxq->bd.ring_size; in fec_enet_init()
3522 rxq->bd.qid = i; in fec_enet_init()
3523 rxq->bd.base = cbd_base; in fec_enet_init()
3524 rxq->bd.cur = cbd_base; in fec_enet_init()
3525 rxq->bd.dma = bd_dma; in fec_enet_init()
3526 rxq->bd.dsize = dsize; in fec_enet_init()
3527 rxq->bd.dsize_log2 = dsize_log2; in fec_enet_init()
3528 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; in fec_enet_init()
3531 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); in fec_enet_init()
3534 for (i = 0; i < fep->num_tx_queues; i++) { in fec_enet_init()
3535 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; in fec_enet_init()
3536 unsigned size = dsize * txq->bd.ring_size; in fec_enet_init()
3538 txq->bd.qid = i; in fec_enet_init()
3539 txq->bd.base = cbd_base; in fec_enet_init()
3540 txq->bd.cur = cbd_base; in fec_enet_init()
3541 txq->bd.dma = bd_dma; in fec_enet_init()
3542 txq->bd.dsize = dsize; in fec_enet_init()
3543 txq->bd.dsize_log2 = dsize_log2; in fec_enet_init()
3544 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; in fec_enet_init()
3547 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); in fec_enet_init()
3552 ndev->watchdog_timeo = TX_TIMEOUT; in fec_enet_init()
3553 ndev->netdev_ops = &fec_netdev_ops; in fec_enet_init()
3554 ndev->ethtool_ops = &fec_enet_ethtool_ops; in fec_enet_init()
3556 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); in fec_enet_init()
3557 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); in fec_enet_init()
3559 if (fep->quirks & FEC_QUIRK_HAS_VLAN) in fec_enet_init()
3561 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; in fec_enet_init()
3563 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { in fec_enet_init()
3564 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; in fec_enet_init()
3567 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM in fec_enet_init()
3569 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; in fec_enet_init()
3572 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { in fec_enet_init()
3573 fep->tx_align = 0; in fec_enet_init()
3574 fep->rx_align = 0x3f; in fec_enet_init()
3577 ndev->hw_features = ndev->features; in fec_enet_init()
3581 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) in fec_enet_init()
3599 struct device_node *np = pdev->dev.of_node; in fec_reset_phy()
3604 err = of_property_read_u32(np, "phy-reset-duration", &msec); in fec_reset_phy()
3609 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); in fec_reset_phy()
3610 if (phy_reset == -EPROBE_DEFER) in fec_reset_phy()
3615 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); in fec_reset_phy()
3618 return -EINVAL; in fec_reset_phy()
3620 active_high = of_property_read_bool(np, "phy-reset-active-high"); in fec_reset_phy()
3622 err = devm_gpio_request_one(&pdev->dev, phy_reset, in fec_reset_phy()
3624 "phy-reset"); in fec_reset_phy()
3626 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); in fec_reset_phy()
3662 struct device_node *np = pdev->dev.of_node; in fec_enet_get_queue_num()
3669 /* parse the num of tx and rx queues */ in fec_enet_get_queue_num()
3670 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); in fec_enet_get_queue_num()
3672 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); in fec_enet_get_queue_num()
3675 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", in fec_enet_get_queue_num()
3682 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", in fec_enet_get_queue_num()
3708 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2) in fec_enet_get_wakeup_irq()
3709 fep->wake_irq = fep->irq[2]; in fec_enet_get_wakeup_irq()
3711 fep->wake_irq = fep->irq[0]; in fec_enet_get_wakeup_irq()
3721 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); in fec_enet_init_stop_mode()
3725 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, in fec_enet_init_stop_mode()
3728 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); in fec_enet_init_stop_mode()
3732 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); in fec_enet_init_stop_mode()
3733 if (IS_ERR(fep->stop_gpr.gpr)) { in fec_enet_init_stop_mode()
3734 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); in fec_enet_init_stop_mode()
3735 ret = PTR_ERR(fep->stop_gpr.gpr); in fec_enet_init_stop_mode()
3736 fep->stop_gpr.gpr = NULL; in fec_enet_init_stop_mode()
3740 fep->stop_gpr.reg = out_val[1]; in fec_enet_init_stop_mode()
3741 fep->stop_gpr.bit = out_val[2]; in fec_enet_init_stop_mode()
3759 struct device_node *np = pdev->dev.of_node, *phy_node; in fec_probe()
3772 return -ENOMEM; in fec_probe()
3774 SET_NETDEV_DEV(ndev, &pdev->dev); in fec_probe()
3779 of_id = of_match_device(fec_dt_ids, &pdev->dev); in fec_probe()
3781 pdev->id_entry = of_id->data; in fec_probe()
3782 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; in fec_probe()
3784 fep->quirks = dev_info->quirks; in fec_probe()
3786 fep->netdev = ndev; in fec_probe()
3787 fep->num_rx_queues = num_rx_qs; in fec_probe()
3788 fep->num_tx_queues = num_tx_qs; in fec_probe()
3792 if (fep->quirks & FEC_QUIRK_HAS_GBIT) in fec_probe()
3793 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; in fec_probe()
3797 pinctrl_pm_select_default_state(&pdev->dev); in fec_probe()
3799 fep->hwp = devm_platform_ioremap_resource(pdev, 0); in fec_probe()
3800 if (IS_ERR(fep->hwp)) { in fec_probe()
3801 ret = PTR_ERR(fep->hwp); in fec_probe()
3805 fep->pdev = pdev; in fec_probe()
3806 fep->dev_id = dev_id++; in fec_probe()
3812 !of_property_read_bool(np, "fsl,err006687-workaround-present")) in fec_probe()
3813 fep->quirks |= FEC_QUIRK_ERR006687; in fec_probe()
3815 if (of_get_property(np, "fsl,magic-packet", NULL)) in fec_probe()
3816 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; in fec_probe()
3822 phy_node = of_parse_phandle(np, "phy-handle", 0); in fec_probe()
3826 dev_err(&pdev->dev, in fec_probe()
3827 "broken fixed-link specification\n"); in fec_probe()
3832 fep->phy_node = phy_node; in fec_probe()
3834 ret = of_get_phy_mode(pdev->dev.of_node, &interface); in fec_probe()
3836 pdata = dev_get_platdata(&pdev->dev); in fec_probe()
3838 fep->phy_interface = pdata->phy; in fec_probe()
3840 fep->phy_interface = PHY_INTERFACE_MODE_MII; in fec_probe()
3842 fep->phy_interface = interface; in fec_probe()
3849 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in fec_probe()
3850 if (IS_ERR(fep->clk_ipg)) { in fec_probe()
3851 ret = PTR_ERR(fep->clk_ipg); in fec_probe()
3855 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in fec_probe()
3856 if (IS_ERR(fep->clk_ahb)) { in fec_probe()
3857 ret = PTR_ERR(fep->clk_ahb); in fec_probe()
3861 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); in fec_probe()
3864 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); in fec_probe()
3865 if (IS_ERR(fep->clk_enet_out)) in fec_probe()
3866 fep->clk_enet_out = NULL; in fec_probe()
3868 fep->ptp_clk_on = false; in fec_probe()
3869 mutex_init(&fep->ptp_clk_mutex); in fec_probe()
3872 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); in fec_probe()
3873 if (IS_ERR(fep->clk_ref)) in fec_probe()
3874 fep->clk_ref = NULL; in fec_probe()
3875 fep->clk_ref_rate = clk_get_rate(fep->clk_ref); in fec_probe()
3878 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) { in fec_probe()
3879 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk"); in fec_probe()
3880 if (IS_ERR(fep->clk_2x_txclk)) in fec_probe()
3881 fep->clk_2x_txclk = NULL; in fec_probe()
3884 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; in fec_probe()
3885 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); in fec_probe()
3886 if (IS_ERR(fep->clk_ptp)) { in fec_probe()
3887 fep->clk_ptp = NULL; in fec_probe()
3888 fep->bufdesc_ex = false; in fec_probe()
3895 ret = clk_prepare_enable(fep->clk_ipg); in fec_probe()
3898 ret = clk_prepare_enable(fep->clk_ahb); in fec_probe()
3902 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); in fec_probe()
3903 if (!IS_ERR(fep->reg_phy)) { in fec_probe()
3904 ret = regulator_enable(fep->reg_phy); in fec_probe()
3906 dev_err(&pdev->dev, in fec_probe()
3911 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { in fec_probe()
3912 ret = -EPROBE_DEFER; in fec_probe()
3915 fep->reg_phy = NULL; in fec_probe()
3918 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); in fec_probe()
3919 pm_runtime_use_autosuspend(&pdev->dev); in fec_probe()
3920 pm_runtime_get_noresume(&pdev->dev); in fec_probe()
3921 pm_runtime_set_active(&pdev->dev); in fec_probe()
3922 pm_runtime_enable(&pdev->dev); in fec_probe()
3929 if (fep->bufdesc_ex) in fec_probe()
3945 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, in fec_probe()
3946 0, pdev->name, ndev); in fec_probe()
3950 fep->irq[i] = irq; in fec_probe()
3963 pinctrl_pm_select_sleep_state(&pdev->dev); in fec_probe()
3965 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; in fec_probe()
3971 device_init_wakeup(&ndev->dev, fep->wol_flag & in fec_probe()
3974 if (fep->bufdesc_ex && fep->ptp_clock) in fec_probe()
3975 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); in fec_probe()
3977 fep->rx_copybreak = COPYBREAK_DEFAULT; in fec_probe()
3978 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); in fec_probe()
3980 pm_runtime_mark_last_busy(&pdev->dev); in fec_probe()
3981 pm_runtime_put_autosuspend(&pdev->dev); in fec_probe()
3992 pm_runtime_put_noidle(&pdev->dev); in fec_probe()
3993 pm_runtime_disable(&pdev->dev); in fec_probe()
3994 if (fep->reg_phy) in fec_probe()
3995 regulator_disable(fep->reg_phy); in fec_probe()
3997 clk_disable_unprepare(fep->clk_ahb); in fec_probe()
3999 clk_disable_unprepare(fep->clk_ipg); in fec_probe()
4009 dev_id--; in fec_probe()
4021 struct device_node *np = pdev->dev.of_node; in fec_drv_remove()
4024 ret = pm_runtime_resume_and_get(&pdev->dev); in fec_drv_remove()
4028 cancel_work_sync(&fep->tx_timeout_work); in fec_drv_remove()
4032 if (fep->reg_phy) in fec_drv_remove()
4033 regulator_disable(fep->reg_phy); in fec_drv_remove()
4037 of_node_put(fep->phy_node); in fec_drv_remove()
4039 clk_disable_unprepare(fep->clk_ahb); in fec_drv_remove()
4040 clk_disable_unprepare(fep->clk_ipg); in fec_drv_remove()
4041 pm_runtime_put_noidle(&pdev->dev); in fec_drv_remove()
4042 pm_runtime_disable(&pdev->dev); in fec_drv_remove()
4055 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) in fec_suspend()
4056 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; in fec_suspend()
4057 phy_stop(ndev->phydev); in fec_suspend()
4058 napi_disable(&fep->napi); in fec_suspend()
4064 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) in fec_suspend()
4065 pinctrl_pm_select_sleep_state(&fep->pdev->dev); in fec_suspend()
4069 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) in fec_suspend()
4070 regulator_disable(fep->reg_phy); in fec_suspend()
4075 if (fep->clk_enet_out || fep->reg_phy) in fec_suspend()
4076 fep->link = 0; in fec_suspend()
4088 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { in fec_resume()
4089 ret = regulator_enable(fep->reg_phy); in fec_resume()
4101 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { in fec_resume()
4104 val = readl(fep->hwp + FEC_ECNTRL); in fec_resume()
4106 writel(val, fep->hwp + FEC_ECNTRL); in fec_resume()
4107 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; in fec_resume()
4109 pinctrl_pm_select_default_state(&fep->pdev->dev); in fec_resume()
4115 napi_enable(&fep->napi); in fec_resume()
4116 phy_init_hw(ndev->phydev); in fec_resume()
4117 phy_start(ndev->phydev); in fec_resume()
4124 if (fep->reg_phy) in fec_resume()
4125 regulator_disable(fep->reg_phy); in fec_resume()
4134 clk_disable_unprepare(fep->clk_ahb); in fec_runtime_suspend()
4135 clk_disable_unprepare(fep->clk_ipg); in fec_runtime_suspend()
4146 ret = clk_prepare_enable(fep->clk_ahb); in fec_runtime_resume()
4149 ret = clk_prepare_enable(fep->clk_ipg); in fec_runtime_resume()
4156 clk_disable_unprepare(fep->clk_ahb); in fec_runtime_resume()