Lines Matching +full:srom +full:- +full:timing
41 Digital Semiconductor SROM Specification. The driver currently
44 DC21040 (no SROM)
56 SMC9332 (w/new SROM)
72 measurement. Their error is +/-20k on a quiet (private) network and also
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
140 I've changed the timing routines to use the kernel timer and scheduling
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
165 (with the latest SROM complying with the SROM spec V3: their first was
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
196 autonegotiation feature in the SROM autoconf code, this detection will
201 and media. The only lexical constraints are: the board name (dev->name)
208 sub-parameters:
211 Case sensitivity is important for the sub-parameters. They *must* be
224 correct in relation to what the adapter SROM says it has. There's no way
234 insmod "args" line; for built-in kernels either change the driver to do
239 ------
242 ----------------
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
284 selection using kernel scheduling/timing.
285 Re-formatted.
290 checking is done now - assume BIOS is good!
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
298 0.42 26-Apr-96 Fix MII write TA bit error.
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
308 Fix TX under-run bug for non DC21140 chips.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
329 0.5 30-Jan-97 Added SROM decoding functions.
333 Added multi-MAC, one SROM feature from discussion
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
343 Fix initialisation problem with lp->timeout in
347 0.52 26-Apr-97 Some changes may not credit the right people -
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
361 Fix multi-MAC, one SROM, to work with 2114x chips:
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
389 case where a 21140 under SROM control uses, e.g. AUI
395 when using SROM control from problem report by
404 lp->rst not run because lp->ibn not initialised -
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
420 Change dev->interrupt to lp->interrupt to ensure
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
428 0.545 28-Nov-99 Further Moto SROM bug fix from
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
442 <maz@wild-wind.fr.eu.org>
467 #include <linux/dma-mapping.h>
494 int ta; /* One cycle TA time - 802.3u is confusing here */
512 u_char *gep; /* Start of GEP sequence block in SROM */
513 u_char *rst; /* Start of reset sequence in SROM */
525 u_char ext; /* csr13-15 valid when set */
548 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
552 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
555 ** Define special SROM detection cases
566 ** SROM Repair definitions. If a broken SROM is detected a card may
660 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
661 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
662 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
663 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
664 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
665 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
683 imr |= lp->irq_en;\
689 imr &= ~lp->irq_en;\
694 imr |= lp->irq_mask;\
700 imr &= ~lp->irq_mask;\
730 ** SROM Structure
837 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
839 struct de4x5_srom srom; /* A copy of the SROM */ member
842 bool useSROM; /* For non-DEC card use SROM */
847 int defMedium; /* SROM default medium */
850 int infoleaf_offset; /* SROM infoleaf for controller */
851 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
864 ** To get around certain poxy cards that don't provide an SROM
866 ** chip's address. I'll assume there's not a bad SROM iff:
889 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
890 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
891 lp->tx_old -lp->tx_new-1)
893 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
1014 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1027 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1032 ** List the SROM infoleaf functions and chipsets
1047 ** List the SROM info block functions
1059 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1106 if (lp->bus == EISA) { in de4x5_hw_init()
1117 return -ENXIO; /* Hardware could not reset */ in de4x5_hw_init()
1123 lp->useSROM = false; in de4x5_hw_init()
1124 if (lp->bus == PCI) { in de4x5_hw_init()
1131 return -ENXIO; in de4x5_hw_init()
1134 dev->base_addr = iobase; in de4x5_hw_init()
1138 printk(", h/w address %pM\n", dev->dev_addr); in de4x5_hw_init()
1142 return -ENXIO; in de4x5_hw_init()
1144 skb_queue_head_init(&lp->cache.queue); in de4x5_hw_init()
1145 lp->cache.gepc = GEP_INIT; in de4x5_hw_init()
1146 lp->asBit = GEP_SLNK; in de4x5_hw_init()
1147 lp->asPolarity = GEP_SLNK; in de4x5_hw_init()
1148 lp->asBitValid = ~0; in de4x5_hw_init()
1149 lp->timeout = -1; in de4x5_hw_init()
1150 lp->gendev = gendev; in de4x5_hw_init()
1151 spin_lock_init(&lp->lock); in de4x5_hw_init()
1152 timer_setup(&lp->timer, de4x5_ast, 0); in de4x5_hw_init()
1158 lp->autosense = lp->params.autosense; in de4x5_hw_init()
1159 if (lp->chipset != DC21140) { in de4x5_hw_init()
1160 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) { in de4x5_hw_init()
1161 lp->params.autosense = TP; in de4x5_hw_init()
1163 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) { in de4x5_hw_init()
1164 lp->params.autosense = BNC; in de4x5_hw_init()
1167 lp->fdx = lp->params.fdx; in de4x5_hw_init()
1168 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev)); in de4x5_hw_init()
1170 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc); in de4x5_hw_init()
1172 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN; in de4x5_hw_init()
1174 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size, in de4x5_hw_init()
1175 &lp->dma_rings, GFP_ATOMIC); in de4x5_hw_init()
1176 if (lp->rx_ring == NULL) { in de4x5_hw_init()
1177 return -ENOMEM; in de4x5_hw_init()
1180 lp->tx_ring = lp->rx_ring + NUM_RX_DESC; in de4x5_hw_init()
1188 lp->rx_ring[i].status = 0; in de4x5_hw_init()
1189 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); in de4x5_hw_init()
1190 lp->rx_ring[i].buf = 0; in de4x5_hw_init()
1191 lp->rx_ring[i].next = 0; in de4x5_hw_init()
1192 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */ in de4x5_hw_init()
1199 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC) in de4x5_hw_init()
1202 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC in de4x5_hw_init()
1205 lp->rx_ring[i].status = 0; in de4x5_hw_init()
1206 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); in de4x5_hw_init()
1207 lp->rx_ring[i].buf = in de4x5_hw_init()
1209 lp->rx_ring[i].next = 0; in de4x5_hw_init()
1210 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */ in de4x5_hw_init()
1218 lp->rxRingSize = NUM_RX_DESC; in de4x5_hw_init()
1219 lp->txRingSize = NUM_TX_DESC; in de4x5_hw_init()
1222 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); in de4x5_hw_init()
1223 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER); in de4x5_hw_init()
1226 outl(lp->dma_rings, DE4X5_RRBA); in de4x5_hw_init()
1227 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), in de4x5_hw_init()
1231 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM; in de4x5_hw_init()
1232 lp->irq_en = IMR_NIM | IMR_AIM; in de4x5_hw_init()
1235 create_packet(dev, lp->frame, sizeof(lp->frame)); in de4x5_hw_init()
1238 i = lp->cfrv & 0x000000fe; in de4x5_hw_init()
1239 if ((lp->chipset == DC21140) && (i == 0x20)) { in de4x5_hw_init()
1240 lp->rx_ovf = 1; in de4x5_hw_init()
1243 /* Initialise the SROM pointers if possible */ in de4x5_hw_init()
1244 if (lp->useSROM) { in de4x5_hw_init()
1245 lp->state = INITIALISED; in de4x5_hw_init()
1247 dma_free_coherent (gendev, lp->dma_size, in de4x5_hw_init()
1248 lp->rx_ring, lp->dma_rings); in de4x5_hw_init()
1249 return -ENXIO; in de4x5_hw_init()
1254 lp->state = CLOSED; in de4x5_hw_init()
1259 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) { in de4x5_hw_init()
1263 printk(" and requires IRQ%d (provided by %s).\n", dev->irq, in de4x5_hw_init()
1264 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG")); in de4x5_hw_init()
1271 /* The DE4X5-specific entries in the device structure. */ in de4x5_hw_init()
1273 dev->netdev_ops = &de4x5_netdev_ops; in de4x5_hw_init()
1274 dev->mem_start = 0; in de4x5_hw_init()
1278 dma_free_coherent (gendev, lp->dma_size, in de4x5_hw_init()
1279 lp->rx_ring, lp->dma_rings); in de4x5_hw_init()
1294 u_long iobase = dev->base_addr; in de4x5_open()
1299 for (i=0; i<lp->rxRingSize; i++) { in de4x5_open()
1302 return -EAGAIN; in de4x5_open()
1312 ** Re-initialize the DE4X5... in de4x5_open()
1315 spin_lock_init(&lp->lock); in de4x5_open()
1316 lp->state = OPEN; in de4x5_open()
1319 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED, in de4x5_open()
1320 lp->adapter_name, dev)) { in de4x5_open()
1321 printk("de4x5_open(): Requested IRQ%d is busy - attempting FAST/SHARE...", dev->irq); in de4x5_open()
1322 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED, in de4x5_open()
1323 lp->adapter_name, dev)) { in de4x5_open()
1324 printk("\n Cannot get IRQ- reconfigure your hardware.\n"); in de4x5_open()
1329 lp->state = CLOSED; in de4x5_open()
1330 return -EAGAIN; in de4x5_open()
1337 lp->interrupt = UNMASK_INTERRUPTS; in de4x5_open()
1384 u_long iobase = dev->base_addr; in de4x5_sw_reset()
1389 if (!lp->useSROM) { in de4x5_sw_reset()
1390 if (lp->phy[lp->active].id != 0) { in de4x5_sw_reset()
1391 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD; in de4x5_sw_reset()
1393 lp->infoblock_csr6 = OMR_SDP | OMR_TTM; in de4x5_sw_reset()
1403 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN; in de4x5_sw_reset()
1404 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0); in de4x5_sw_reset()
1408 if (lp->chipset == DC21140) { in de4x5_sw_reset()
1411 lp->setup_f = PERFECT; in de4x5_sw_reset()
1412 outl(lp->dma_rings, DE4X5_RRBA); in de4x5_sw_reset()
1413 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), in de4x5_sw_reset()
1416 lp->rx_new = lp->rx_old = 0; in de4x5_sw_reset()
1417 lp->tx_new = lp->tx_old = 0; in de4x5_sw_reset()
1419 for (i = 0; i < lp->rxRingSize; i++) { in de4x5_sw_reset()
1420 lp->rx_ring[i].status = cpu_to_le32(R_OWN); in de4x5_sw_reset()
1423 for (i = 0; i < lp->txRingSize; i++) { in de4x5_sw_reset()
1424 lp->tx_ring[i].status = cpu_to_le32(0); in de4x5_sw_reset()
1432 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1); in de4x5_sw_reset()
1439 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1; in de4x5_sw_reset()
1444 printk("%s: Setup frame timed out, status %08x\n", dev->name, in de4x5_sw_reset()
1446 status = -EIO; in de4x5_sw_reset()
1449 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in de4x5_sw_reset()
1450 lp->tx_old = lp->tx_new; in de4x5_sw_reset()
1462 u_long iobase = dev->base_addr; in de4x5_queue_pkt()
1466 if (!lp->tx_enable) /* Cannot send for now */ in de4x5_queue_pkt()
1470 ** Clean out the TX ring asynchronously to interrupts - sometimes the in de4x5_queue_pkt()
1474 spin_lock_irqsave(&lp->lock, flags); in de4x5_queue_pkt()
1476 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_queue_pkt()
1478 /* Test if cache is already locked - requeue skb if so */ in de4x5_queue_pkt()
1479 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt) in de4x5_queue_pkt()
1483 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) { in de4x5_queue_pkt()
1484 if (lp->interrupt) { in de4x5_queue_pkt()
1490 …\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5… in de4x5_queue_pkt()
1492 } else if (skb->len > 0) { in de4x5_queue_pkt()
1494 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) { in de4x5_queue_pkt()
1500 (u_long) lp->tx_skb[lp->tx_new] <= 1) { in de4x5_queue_pkt()
1501 spin_lock_irqsave(&lp->lock, flags); in de4x5_queue_pkt()
1503 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb); in de4x5_queue_pkt()
1504 lp->stats.tx_bytes += skb->len; in de4x5_queue_pkt()
1507 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in de4x5_queue_pkt()
1513 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_queue_pkt()
1518 lp->cache.lock = 0; in de4x5_queue_pkt()
1530 ** so that the asserted interrupt always has some real data to work with -
1547 spin_lock(&lp->lock); in de4x5_interrupt()
1548 iobase = dev->base_addr; in de4x5_interrupt()
1550 DISABLE_IRQs; /* Ensure non re-entrancy */ in de4x5_interrupt()
1552 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt)) in de4x5_interrupt()
1553 printk("%s: Re-entering the interrupt handler.\n", dev->name); in de4x5_interrupt()
1555 synchronize_irq(dev->irq); in de4x5_interrupt()
1561 if (!(sts & lp->irq_mask)) break;/* All done */ in de4x5_interrupt()
1571 lp->irq_mask &= ~IMR_LFM; in de4x5_interrupt()
1581 dev->name, sts); in de4x5_interrupt()
1582 spin_unlock(&lp->lock); in de4x5_interrupt()
1588 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) { in de4x5_interrupt()
1589 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) { in de4x5_interrupt()
1592 lp->cache.lock = 0; in de4x5_interrupt()
1595 lp->interrupt = UNMASK_INTERRUPTS; in de4x5_interrupt()
1597 spin_unlock(&lp->lock); in de4x5_interrupt()
1606 u_long iobase = dev->base_addr; in de4x5_rx()
1610 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0; in de4x5_rx()
1611 entry=lp->rx_new) { in de4x5_rx()
1612 status = (s32)le32_to_cpu(lp->rx_ring[entry].status); in de4x5_rx()
1614 if (lp->rx_ovf) { in de4x5_rx()
1622 lp->rx_old = entry; in de4x5_rx()
1626 if (lp->tx_enable) lp->linkOK++; in de4x5_rx()
1628 lp->stats.rx_errors++; /* Update the error stats. */ in de4x5_rx()
1629 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++; in de4x5_rx()
1630 if (status & RD_CE) lp->stats.rx_crc_errors++; in de4x5_rx()
1631 if (status & RD_OF) lp->stats.rx_fifo_errors++; in de4x5_rx()
1632 if (status & RD_TL) lp->stats.rx_length_errors++; in de4x5_rx()
1633 if (status & RD_RF) lp->pktStats.rx_runt_frames++; in de4x5_rx()
1634 if (status & RD_CS) lp->pktStats.rx_collision++; in de4x5_rx()
1635 if (status & RD_DB) lp->pktStats.rx_dribble++; in de4x5_rx()
1636 if (status & RD_OF) lp->pktStats.rx_overflow++; in de4x5_rx()
1639 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status) in de4x5_rx()
1640 >> 16) - 4; in de4x5_rx()
1644 dev->name); in de4x5_rx()
1645 lp->stats.rx_dropped++; in de4x5_rx()
1650 skb->protocol=eth_type_trans(skb,dev); in de4x5_rx()
1651 de4x5_local_stats(dev, skb->data, pkt_len); in de4x5_rx()
1655 lp->stats.rx_packets++; in de4x5_rx()
1656 lp->stats.rx_bytes += pkt_len; in de4x5_rx()
1661 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) { in de4x5_rx()
1662 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN); in de4x5_rx()
1665 lp->rx_ring[entry].status = cpu_to_le32(R_OWN); in de4x5_rx()
1672 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize; in de4x5_rx()
1681 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf), in de4x5_free_tx_buff()
1682 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1, in de4x5_free_tx_buff()
1684 if ((u_long) lp->tx_skb[entry] > 1) in de4x5_free_tx_buff()
1685 dev_kfree_skb_irq(lp->tx_skb[entry]); in de4x5_free_tx_buff()
1686 lp->tx_skb[entry] = NULL; in de4x5_free_tx_buff()
1690 ** Buffer sent - check for TX buffer errors.
1696 u_long iobase = dev->base_addr; in de4x5_tx()
1700 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) { in de4x5_tx()
1701 status = (s32)le32_to_cpu(lp->tx_ring[entry].status); in de4x5_tx()
1706 lp->stats.tx_errors++; in de4x5_tx()
1707 if (status & TD_NC) lp->stats.tx_carrier_errors++; in de4x5_tx()
1708 if (status & TD_LC) lp->stats.tx_window_errors++; in de4x5_tx()
1709 if (status & TD_UF) lp->stats.tx_fifo_errors++; in de4x5_tx()
1710 if (status & TD_EC) lp->pktStats.excessive_collisions++; in de4x5_tx()
1711 if (status & TD_DE) lp->stats.tx_aborted_errors++; in de4x5_tx()
1717 lp->stats.tx_packets++; in de4x5_tx()
1718 if (lp->tx_enable) lp->linkOK++; in de4x5_tx()
1721 lp->stats.collisions += ((status & TD_EC) ? 16 : in de4x5_tx()
1725 if (lp->tx_skb[entry] != NULL) in de4x5_tx()
1730 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize; in de4x5_tx()
1735 if (lp->interrupt) in de4x5_tx()
1748 struct net_device *dev = dev_get_drvdata(lp->gendev); in de4x5_ast()
1752 if (lp->useSROM) in de4x5_ast()
1754 else if (lp->chipset == DC21140) in de4x5_ast()
1756 else if (lp->chipset == DC21041) in de4x5_ast()
1758 else if (lp->chipset == DC21040) in de4x5_ast()
1760 lp->linkOK = 0; in de4x5_ast()
1767 mod_timer(&lp->timer, jiffies + dt); in de4x5_ast()
1774 u_long iobase = dev->base_addr; in de4x5_txur()
1778 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) { in de4x5_txur()
1797 u_long iobase = dev->base_addr; in de4x5_rx_ovfc()
1804 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) { in de4x5_rx_ovfc()
1805 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN); in de4x5_rx_ovfc()
1806 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize; in de4x5_rx_ovfc()
1818 u_long iobase = dev->base_addr; in de4x5_close()
1827 dev->name, inl(DE4X5_STS)); in de4x5_close()
1837 free_irq(dev->irq, dev); in de4x5_close()
1838 lp->state = CLOSED; in de4x5_close()
1854 u_long iobase = dev->base_addr; in de4x5_get_stats()
1856 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR)); in de4x5_get_stats()
1858 return &lp->stats; in de4x5_get_stats()
1867 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) { in de4x5_local_stats()
1869 lp->pktStats.bins[i]++; in de4x5_local_stats()
1875 lp->pktStats.broadcast++; in de4x5_local_stats()
1877 lp->pktStats.multicast++; in de4x5_local_stats()
1879 } else if (ether_addr_equal(buf, dev->dev_addr)) { in de4x5_local_stats()
1880 lp->pktStats.unicast++; in de4x5_local_stats()
1883 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */ in de4x5_local_stats()
1884 if (lp->pktStats.bins[0] == 0) { /* Reset counters */ in de4x5_local_stats()
1885 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats)); in de4x5_local_stats()
1901 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1); in load_packet()
1902 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE); in load_packet()
1904 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma); in load_packet()
1905 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER); in load_packet()
1906 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags); in load_packet()
1907 lp->tx_skb[lp->tx_new] = skb; in load_packet()
1908 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC); in load_packet()
1911 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN); in load_packet()
1922 u_long iobase = dev->base_addr; in set_multicast_list()
1925 if (lp->state == OPEN) { in set_multicast_list()
1926 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ in set_multicast_list()
1933 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | in set_multicast_list()
1936 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in set_multicast_list()
1953 u_long iobase = dev->base_addr; in SetMulticastFilter()
1964 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) { in SetMulticastFilter()
1966 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */ in SetMulticastFilter()
1968 crc = ether_crc_le(ETH_ALEN, ha->addr); in SetMulticastFilter()
1971 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */ in SetMulticastFilter()
1972 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */ in SetMulticastFilter()
1976 byte -= 1; in SetMulticastFilter()
1978 lp->setup_frame[byte] |= bit; in SetMulticastFilter()
1982 addrs = ha->addr; in SetMulticastFilter()
2008 iobase = edev->base_addr; in de4x5_eisa_probe()
2011 return -EBUSY; in de4x5_eisa_probe()
2015 status = -EBUSY; in de4x5_eisa_probe()
2020 status = -ENOMEM; in de4x5_eisa_probe()
2026 lp->cfrv = (u_short) inl(PCI_CFRV); in de4x5_eisa_probe()
2055 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); in de4x5_eisa_probe()
2057 lp->chipset = device; in de4x5_eisa_probe()
2058 lp->bus = EISA; in de4x5_eisa_probe()
2067 dev->irq = irq; in de4x5_eisa_probe()
2088 iobase = dev->base_addr; in de4x5_eisa_remove()
2118 ** SROM, so that in multiport cards that have one SROM shared between multiple
2119 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2133 list_for_each_entry(this_dev, &pdev->bus->devices, bus_list) { in srom_search()
2134 vendor = this_dev->vendor; in srom_search()
2135 device = this_dev->device << 8; in srom_search()
2139 pb = this_dev->bus->number; in srom_search()
2142 lp->device = PCI_SLOT(this_dev->devfn); in srom_search()
2143 lp->bus_num = pb; in srom_search()
2147 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK in srom_search()
2150 lp->chipset = device; in srom_search()
2156 irq = this_dev->irq; in srom_search()
2157 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue; in srom_search()
2163 /* Search for a valid SROM attached to this DECchip */ in srom_search()
2166 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i); in srom_search()
2173 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i); in srom_search()
2207 dev_num = PCI_SLOT(pdev->devfn); in de4x5_pci_probe()
2208 pb = pdev->bus->number; in de4x5_pci_probe()
2214 return -ENODEV; in de4x5_pci_probe()
2217 vendor = pdev->vendor; in de4x5_pci_probe()
2218 device = pdev->device << 8; in de4x5_pci_probe()
2220 return -ENODEV; in de4x5_pci_probe()
2227 error = -ENOMEM; in de4x5_pci_probe()
2232 lp->bus = PCI; in de4x5_pci_probe()
2233 lp->bus_num = 0; in de4x5_pci_probe()
2235 /* Search for an SROM on this bus */ in de4x5_pci_probe()
2236 if (lp->bus_num != pb) { in de4x5_pci_probe()
2237 lp->bus_num = pb; in de4x5_pci_probe()
2242 lp->cfrv = pdev->revision; in de4x5_pci_probe()
2245 lp->device = dev_num; in de4x5_pci_probe()
2246 lp->bus_num = pb; in de4x5_pci_probe()
2250 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); in de4x5_pci_probe()
2252 lp->chipset = device; in de4x5_pci_probe()
2258 irq = pdev->irq; in de4x5_pci_probe()
2259 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) { in de4x5_pci_probe()
2260 error = -ENODEV; in de4x5_pci_probe()
2274 error = -ENODEV; in de4x5_pci_probe()
2284 error = -ENODEV; in de4x5_pci_probe()
2297 error = -EBUSY; in de4x5_pci_probe()
2301 dev->irq = irq; in de4x5_pci_probe()
2303 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) { in de4x5_pci_probe()
2324 iobase = dev->base_addr; in de4x5_pci_remove()
2364 u_long iobase = dev->base_addr; in autoconf_media()
2368 lp->c_media = AUTO; /* Bogus last media */ in autoconf_media()
2370 lp->media = INIT; in autoconf_media()
2371 lp->tcount = 0; in autoconf_media()
2373 de4x5_ast(&lp->timer); in autoconf_media()
2375 return lp->media; in autoconf_media()
2385 ** be queued to the hardware. Re-enable everything only when the media is
2394 u_long iobase = dev->base_addr; in dc21040_autoconf()
2398 switch (lp->media) { in dc21040_autoconf()
2401 lp->tx_enable = false; in dc21040_autoconf()
2402 lp->timeout = -1; in dc21040_autoconf()
2404 if ((lp->autosense == AUTO) || (lp->autosense == TP)) { in dc21040_autoconf()
2405 lp->media = TP; in dc21040_autoconf()
2406 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) { in dc21040_autoconf()
2407 lp->media = BNC_AUI; in dc21040_autoconf()
2408 } else if (lp->autosense == EXT_SIA) { in dc21040_autoconf()
2409 lp->media = EXT_SIA; in dc21040_autoconf()
2411 lp->media = NC; in dc21040_autoconf()
2413 lp->local_state = 0; in dc21040_autoconf()
2449 if (lp->media != lp->c_media) { in dc21040_autoconf()
2451 lp->c_media = lp->media; in dc21040_autoconf()
2453 lp->media = INIT; in dc21040_autoconf()
2454 lp->tx_enable = false; in dc21040_autoconf()
2470 switch (lp->local_state) { in dc21040_state()
2473 lp->local_state++; in dc21040_state()
2478 if (!lp->tx_enable) { in dc21040_state()
2483 if (linkBad && (lp->autosense == AUTO)) { in dc21040_state()
2484 lp->local_state = 0; in dc21040_state()
2485 lp->media = next_state; in dc21040_state()
2490 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21040_state()
2491 lp->media = suspect_state; in dc21040_state()
2509 switch (lp->local_state) { in de4x5_suspect_state()
2511 if (lp->linkOK) { in de4x5_suspect_state()
2512 lp->media = prev_state; in de4x5_suspect_state()
2514 lp->local_state++; in de4x5_suspect_state()
2524 lp->local_state--; in de4x5_suspect_state()
2525 lp->media = prev_state; in de4x5_suspect_state()
2527 lp->media = INIT; in de4x5_suspect_state()
2528 lp->tcount++; in de4x5_suspect_state()
2541 ** any more packets to be queued to the hardware. Re-enable everything only
2548 u_long iobase = dev->base_addr; in dc21041_autoconf()
2552 switch (lp->media) { in dc21041_autoconf()
2555 lp->tx_enable = false; in dc21041_autoconf()
2556 lp->timeout = -1; in dc21041_autoconf()
2558 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) { in dc21041_autoconf()
2559 lp->media = TP; /* On chip auto negotiation is broken */ in dc21041_autoconf()
2560 } else if (lp->autosense == TP) { in dc21041_autoconf()
2561 lp->media = TP; in dc21041_autoconf()
2562 } else if (lp->autosense == BNC) { in dc21041_autoconf()
2563 lp->media = BNC; in dc21041_autoconf()
2564 } else if (lp->autosense == AUI) { in dc21041_autoconf()
2565 lp->media = AUI; in dc21041_autoconf()
2567 lp->media = NC; in dc21041_autoconf()
2569 lp->local_state = 0; in dc21041_autoconf()
2574 if (lp->timeout < 0) { in dc21041_autoconf()
2585 lp->media = ANS; in dc21041_autoconf()
2587 lp->media = AUI; in dc21041_autoconf()
2594 if (!lp->tx_enable) { in dc21041_autoconf()
2601 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) { in dc21041_autoconf()
2602 lp->media = TP; in dc21041_autoconf()
2605 lp->local_state = 1; in dc21041_autoconf()
2609 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21041_autoconf()
2610 lp->media = ANS_SUSPECT; in dc21041_autoconf()
2620 if (!lp->tx_enable) { in dc21041_autoconf()
2621 if (lp->timeout < 0) { in dc21041_autoconf()
2631 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) { in dc21041_autoconf()
2633 lp->media = AUI; /* Non selected port activity */ in dc21041_autoconf()
2635 lp->media = BNC; in dc21041_autoconf()
2639 lp->local_state = 1; in dc21041_autoconf()
2643 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21041_autoconf()
2644 lp->media = TP_SUSPECT; in dc21041_autoconf()
2654 if (!lp->tx_enable) { in dc21041_autoconf()
2655 if (lp->timeout < 0) { in dc21041_autoconf()
2665 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) { in dc21041_autoconf()
2666 lp->media = BNC; in dc21041_autoconf()
2669 lp->local_state = 1; in dc21041_autoconf()
2673 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21041_autoconf()
2674 lp->media = AUI_SUSPECT; in dc21041_autoconf()
2684 switch (lp->local_state) { in dc21041_autoconf()
2686 if (lp->timeout < 0) { in dc21041_autoconf()
2696 lp->local_state++; /* Ensure media connected */ in dc21041_autoconf()
2702 if (!lp->tx_enable) { in dc21041_autoconf()
2707 lp->local_state = 0; in dc21041_autoconf()
2708 lp->media = NC; in dc21041_autoconf()
2713 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21041_autoconf()
2714 lp->media = BNC_SUSPECT; in dc21041_autoconf()
2729 if (lp->media != lp->c_media) { in dc21041_autoconf()
2731 lp->c_media = lp->media; in dc21041_autoconf()
2733 lp->media = INIT; in dc21041_autoconf()
2734 lp->tx_enable = false; in dc21041_autoconf()
2752 u_long imr, omr, iobase = dev->base_addr; in dc21140m_autoconf()
2754 switch(lp->media) { in dc21140m_autoconf()
2756 if (lp->timeout < 0) { in dc21140m_autoconf()
2758 lp->tx_enable = false; in dc21140m_autoconf()
2759 lp->linkOK = 0; in dc21140m_autoconf()
2765 if (lp->useSROM) { in dc21140m_autoconf()
2767 lp->tcount++; in dc21140m_autoconf()
2770 srom_exec(dev, lp->phy[lp->active].gep); in dc21140m_autoconf()
2771 if (lp->infoblock_media == ANS) { in dc21140m_autoconf()
2772 ana = lp->phy[lp->active].ana | MII_ANA_CSMA; in dc21140m_autoconf()
2773 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2776 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */ in dc21140m_autoconf()
2778 if (lp->autosense == _100Mb) { in dc21140m_autoconf()
2779 lp->media = _100Mb; in dc21140m_autoconf()
2780 } else if (lp->autosense == _10Mb) { in dc21140m_autoconf()
2781 lp->media = _10Mb; in dc21140m_autoconf()
2782 } else if ((lp->autosense == AUTO) && in dc21140m_autoconf()
2785 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM); in dc21140m_autoconf()
2786 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2787 lp->media = ANS; in dc21140m_autoconf()
2788 } else if (lp->autosense == AUTO) { in dc21140m_autoconf()
2789 lp->media = SPD_DET; in dc21140m_autoconf()
2791 lp->media = _100Mb; in dc21140m_autoconf()
2793 lp->media = NC; in dc21140m_autoconf()
2796 lp->local_state = 0; in dc21140m_autoconf()
2802 switch (lp->local_state) { in dc21140m_autoconf()
2804 if (lp->timeout < 0) { in dc21140m_autoconf()
2805 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2812 lp->local_state = 0; in dc21140m_autoconf()
2813 lp->media = SPD_DET; in dc21140m_autoconf()
2815 lp->local_state++; in dc21140m_autoconf()
2825 lp->media = SPD_DET; in dc21140m_autoconf()
2826 lp->local_state = 0; in dc21140m_autoconf()
2828 lp->tmp = MII_SR_ASSC; in dc21140m_autoconf()
2829 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2830 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2834 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0; in dc21140m_autoconf()
2835 lp->media = _100Mb; in dc21140m_autoconf()
2837 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0; in dc21140m_autoconf()
2839 lp->media = _10Mb; in dc21140m_autoconf()
2850 if (lp->timeout < 0) { in dc21140m_autoconf()
2851 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS : in dc21140m_autoconf()
2859 lp->media = _100Mb; in dc21140m_autoconf()
2860 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) { in dc21140m_autoconf()
2861 lp->media = _10Mb; in dc21140m_autoconf()
2863 lp->media = NC; in dc21140m_autoconf()
2871 if (!lp->tx_enable) { in dc21140m_autoconf()
2875 if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21140m_autoconf()
2876 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) { in dc21140m_autoconf()
2877 lp->media = INIT; in dc21140m_autoconf()
2878 lp->tcount++; in dc21140m_autoconf()
2889 if (!lp->tx_enable) { in dc21140m_autoconf()
2893 if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21140m_autoconf()
2894 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) { in dc21140m_autoconf()
2895 lp->media = INIT; in dc21140m_autoconf()
2896 lp->tcount++; in dc21140m_autoconf()
2904 if (lp->media != lp->c_media) { in dc21140m_autoconf()
2906 lp->c_media = lp->media; in dc21140m_autoconf()
2908 lp->media = INIT; in dc21140m_autoconf()
2909 lp->tx_enable = false; in dc21140m_autoconf()
2918 ** changing how I figure out the media - but trying to keep it backwards
2919 ** compatible with the de500-xa and de500-aa.
2924 ** When autonegotiation is working, the ANS part searches the SROM for
2934 u_long iobase = dev->base_addr; in dc2114x_autoconf()
2938 switch (lp->media) { in dc2114x_autoconf()
2940 if (lp->timeout < 0) { in dc2114x_autoconf()
2942 lp->tx_enable = false; in dc2114x_autoconf()
2943 lp->linkOK = 0; in dc2114x_autoconf()
2944 lp->timeout = -1; in dc2114x_autoconf()
2946 if (lp->params.autosense & ~AUTO) { in dc2114x_autoconf()
2948 if (lp->media != lp->params.autosense) { in dc2114x_autoconf()
2949 lp->tcount++; in dc2114x_autoconf()
2950 lp->media = INIT; in dc2114x_autoconf()
2953 lp->media = INIT; in dc2114x_autoconf()
2959 if (lp->autosense == _100Mb) { in dc2114x_autoconf()
2960 lp->media = _100Mb; in dc2114x_autoconf()
2961 } else if (lp->autosense == _10Mb) { in dc2114x_autoconf()
2962 lp->media = _10Mb; in dc2114x_autoconf()
2963 } else if (lp->autosense == TP) { in dc2114x_autoconf()
2964 lp->media = TP; in dc2114x_autoconf()
2965 } else if (lp->autosense == BNC) { in dc2114x_autoconf()
2966 lp->media = BNC; in dc2114x_autoconf()
2967 } else if (lp->autosense == AUI) { in dc2114x_autoconf()
2968 lp->media = AUI; in dc2114x_autoconf()
2970 lp->media = SPD_DET; in dc2114x_autoconf()
2971 if ((lp->infoblock_media == ANS) && in dc2114x_autoconf()
2974 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM); in dc2114x_autoconf()
2975 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc2114x_autoconf()
2976 lp->media = ANS; in dc2114x_autoconf()
2979 lp->local_state = 0; in dc2114x_autoconf()
2985 switch (lp->local_state) { in dc2114x_autoconf()
2987 if (lp->timeout < 0) { in dc2114x_autoconf()
2988 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); in dc2114x_autoconf()
2995 lp->local_state = 0; in dc2114x_autoconf()
2996 lp->media = SPD_DET; in dc2114x_autoconf()
2998 lp->local_state++; in dc2114x_autoconf()
3009 lp->media = SPD_DET; in dc2114x_autoconf()
3010 lp->local_state = 0; in dc2114x_autoconf()
3012 lp->tmp = MII_SR_ASSC; in dc2114x_autoconf()
3013 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII); in dc2114x_autoconf()
3014 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc2114x_autoconf()
3018 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0; in dc2114x_autoconf()
3019 lp->media = _100Mb; in dc2114x_autoconf()
3021 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0; in dc2114x_autoconf()
3022 lp->media = _10Mb; in dc2114x_autoconf()
3033 if (!lp->tx_enable) { in dc2114x_autoconf()
3034 if (lp->timeout < 0) { in dc2114x_autoconf()
3044 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3045 lp->media = BNC; in dc2114x_autoconf()
3048 lp->local_state = 1; in dc2114x_autoconf()
3052 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3053 lp->media = AUI_SUSPECT; in dc2114x_autoconf()
3063 switch (lp->local_state) { in dc2114x_autoconf()
3065 if (lp->timeout < 0) { in dc2114x_autoconf()
3075 lp->local_state++; /* Ensure media connected */ in dc2114x_autoconf()
3081 if (!lp->tx_enable) { in dc2114x_autoconf()
3086 lp->local_state = 0; in dc2114x_autoconf()
3087 lp->tcount++; in dc2114x_autoconf()
3088 lp->media = INIT; in dc2114x_autoconf()
3093 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3094 lp->media = BNC_SUSPECT; in dc2114x_autoconf()
3107 lp->tcount++; in dc2114x_autoconf()
3108 lp->media = INIT; in dc2114x_autoconf()
3111 if (lp->media == _100Mb) { in dc2114x_autoconf()
3113 lp->media = SPD_DET; in dc2114x_autoconf()
3118 lp->media = SPD_DET; in dc2114x_autoconf()
3122 if (lp->media == ANS) { /* Do MII parallel detection */ in dc2114x_autoconf()
3124 lp->media = _100Mb; in dc2114x_autoconf()
3126 lp->media = _10Mb; in dc2114x_autoconf()
3129 } else if (((lp->media == _100Mb) && is_100_up(dev)) || in dc2114x_autoconf()
3130 (((lp->media == _10Mb) || (lp->media == TP) || in dc2114x_autoconf()
3131 (lp->media == BNC) || (lp->media == AUI)) && in dc2114x_autoconf()
3135 lp->tcount++; in dc2114x_autoconf()
3136 lp->media = INIT; in dc2114x_autoconf()
3142 if (!lp->tx_enable) { in dc2114x_autoconf()
3146 if (!lp->linkOK && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3147 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) { in dc2114x_autoconf()
3148 lp->media = INIT; in dc2114x_autoconf()
3149 lp->tcount++; in dc2114x_autoconf()
3158 if (!lp->tx_enable) { in dc2114x_autoconf()
3162 if (!lp->linkOK && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3163 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) { in dc2114x_autoconf()
3164 lp->media = INIT; in dc2114x_autoconf()
3165 lp->tcount++; in dc2114x_autoconf()
3173 lp->tcount++; in dc2114x_autoconf()
3174 printk("Huh?: media:%02x\n", lp->media); in dc2114x_autoconf()
3175 lp->media = INIT; in dc2114x_autoconf()
3187 return lp->infoleaf_fn(dev); in srom_autoconf()
3193 ** The early return avoids a media state / SROM media space clash.
3200 lp->fdx = false; in srom_map_media()
3201 if (lp->infoblock_media == lp->media) in srom_map_media()
3204 switch(lp->infoblock_media) { in srom_map_media()
3206 if (!lp->params.fdx) return -1; in srom_map_media()
3207 lp->fdx = true; in srom_map_media()
3211 if (lp->params.fdx && !lp->fdx) return -1; in srom_map_media()
3212 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) { in srom_map_media()
3213 lp->media = _10Mb; in srom_map_media()
3215 lp->media = TP; in srom_map_media()
3220 lp->media = BNC; in srom_map_media()
3224 lp->media = AUI; in srom_map_media()
3228 if (!lp->params.fdx) return -1; in srom_map_media()
3229 lp->fdx = true; in srom_map_media()
3233 if (lp->params.fdx && !lp->fdx) return -1; in srom_map_media()
3234 lp->media = _100Mb; in srom_map_media()
3238 lp->media = _100Mb; in srom_map_media()
3242 if (!lp->params.fdx) return -1; in srom_map_media()
3243 lp->fdx = true; in srom_map_media()
3247 if (lp->params.fdx && !lp->fdx) return -1; in srom_map_media()
3248 lp->media = _100Mb; in srom_map_media()
3252 lp->media = ANS; in srom_map_media()
3253 lp->fdx = lp->params.fdx; in srom_map_media()
3257 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name, in srom_map_media()
3258 lp->infoblock_media); in srom_map_media()
3259 return -1; in srom_map_media()
3269 u_long iobase = dev->base_addr; in de4x5_init_connection()
3272 if (lp->media != lp->c_media) { in de4x5_init_connection()
3274 lp->c_media = lp->media; /* Stop scrolling media messages */ in de4x5_init_connection()
3277 spin_lock_irqsave(&lp->lock, flags); in de4x5_init_connection()
3280 lp->tx_enable = true; in de4x5_init_connection()
3281 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_init_connection()
3296 u_long iobase = dev->base_addr; in de4x5_reset_phy()
3299 if ((lp->useSROM) || (lp->phy[lp->active].id)) { in de4x5_reset_phy()
3300 if (lp->timeout < 0) { in de4x5_reset_phy()
3301 if (lp->useSROM) { in de4x5_reset_phy()
3302 if (lp->phy[lp->active].rst) { in de4x5_reset_phy()
3303 srom_exec(dev, lp->phy[lp->active].rst); in de4x5_reset_phy()
3304 srom_exec(dev, lp->phy[lp->active].rst); in de4x5_reset_phy()
3305 } else if (lp->rst) { /* Type 5 infoblock reset */ in de4x5_reset_phy()
3306 srom_exec(dev, lp->rst); in de4x5_reset_phy()
3307 srom_exec(dev, lp->rst); in de4x5_reset_phy()
3312 if (lp->useMII) { in de4x5_reset_phy()
3313 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); in de4x5_reset_phy()
3316 if (lp->useMII) { in de4x5_reset_phy()
3319 } else if (lp->chipset == DC21140) { in de4x5_reset_phy()
3330 u_long iobase = dev->base_addr; in test_media()
3333 if (lp->timeout < 0) { in test_media()
3334 lp->timeout = msec/100; in test_media()
3335 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */ in test_media()
3347 if ((lp->chipset == DC21041) || lp->useSROM) { in test_media()
3355 if (!(sts & irqs) && --lp->timeout) { in test_media()
3358 lp->timeout = -1; in test_media()
3368 u_long iobase = dev->base_addr; in test_tp()
3371 if (lp->timeout < 0) { in test_tp()
3372 lp->timeout = msec/100; in test_tp()
3377 if (sisr && --lp->timeout) { in test_tp()
3380 lp->timeout = -1; in test_tp()
3397 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK); in test_for_100Mb()
3399 if (lp->timeout < 0) { in test_for_100Mb()
3402 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL; in test_for_100Mb()
3406 lp->timeout = msec/SAMPLE_INTERVAL; in test_for_100Mb()
3410 if (lp->phy[lp->active].id || lp->useSROM) { in test_for_100Mb()
3415 if (!(gep & ret) && --lp->timeout) { in test_for_100Mb()
3418 lp->timeout = -1; in test_for_100Mb()
3429 if (lp->timeout < 0) { in wait_for_link()
3430 lp->timeout = 1; in wait_for_link()
3433 if (lp->timeout--) { in wait_for_link()
3436 lp->timeout = -1; in wait_for_link()
3451 u_long iobase = dev->base_addr; in test_mii_reg()
3453 if (lp->timeout < 0) { in test_mii_reg()
3454 lp->timeout = msec/100; in test_mii_reg()
3457 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask; in test_mii_reg()
3460 if (test && --lp->timeout) { in test_mii_reg()
3463 lp->timeout = -1; in test_mii_reg()
3473 u_long iobase = dev->base_addr; in is_spd_100()
3476 if (lp->useMII) { in is_spd_100()
3477 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII); in is_spd_100()
3478 spd = ~(spd ^ lp->phy[lp->active].spd.value); in is_spd_100()
3479 spd &= lp->phy[lp->active].spd.mask; in is_spd_100()
3480 } else if (!lp->useSROM) { /* de500-xa */ in is_spd_100()
3483 if ((lp->ibn == 2) || !lp->asBitValid) in is_spd_100()
3484 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0; in is_spd_100()
3486 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) | in is_spd_100()
3487 (lp->linkOK & ~lp->asBitValid); in is_spd_100()
3497 u_long iobase = dev->base_addr; in is_100_up()
3499 if (lp->useMII) { in is_100_up()
3501 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); in is_100_up()
3502 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS; in is_100_up()
3503 } else if (!lp->useSROM) { /* de500-xa */ in is_100_up()
3506 if ((lp->ibn == 2) || !lp->asBitValid) in is_100_up()
3507 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0; in is_100_up()
3509 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | in is_100_up()
3510 (lp->linkOK & ~lp->asBitValid); in is_100_up()
3518 u_long iobase = dev->base_addr; in is_10_up()
3520 if (lp->useMII) { in is_10_up()
3522 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); in is_10_up()
3523 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS; in is_10_up()
3524 } else if (!lp->useSROM) { /* de500-xa */ in is_10_up()
3527 if ((lp->ibn == 2) || !lp->asBitValid) in is_10_up()
3528 return ((lp->chipset & ~0x00ff) == DC2114x) ? in is_10_up()
3532 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | in is_10_up()
3533 (lp->linkOK & ~lp->asBitValid); in is_10_up()
3541 u_long iobase = dev->base_addr; in is_anc_capable()
3543 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { in is_anc_capable()
3544 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); in is_anc_capable()
3545 } else if ((lp->chipset & ~0x00ff) == DC2114x) { in is_anc_capable()
3560 u_long iobase = dev->base_addr; in ping_media()
3563 if (lp->timeout < 0) { in ping_media()
3564 lp->timeout = msec/100; in ping_media()
3566 lp->tmp = lp->tx_new; /* Remember the ring position */ in ping_media()
3567 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1); in ping_media()
3568 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in ping_media()
3575 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) && in ping_media()
3576 (--lp->timeout)) { in ping_media()
3580 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) && in ping_media()
3581 lp->timeout) { in ping_media()
3586 lp->timeout = -1; in ping_media()
3610 tmp = virt_to_bus(p->data); in de4x5_alloc_rx_buff()
3611 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp; in de4x5_alloc_rx_buff()
3613 lp->rx_ring[index].buf = cpu_to_le32(tmp + i); in de4x5_alloc_rx_buff()
3615 ret = lp->rx_skb[index]; in de4x5_alloc_rx_buff()
3616 lp->rx_skb[index] = p; in de4x5_alloc_rx_buff()
3625 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */ in de4x5_alloc_rx_buff()
3631 if (index < lp->rx_old) { /* Wrapped buffer */ in de4x5_alloc_rx_buff()
3632 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ; in de4x5_alloc_rx_buff()
3633 skb_put_data(p, lp->rx_bufs + lp->rx_old * RX_BUFF_SZ, tlen); in de4x5_alloc_rx_buff()
3634 skb_put_data(p, lp->rx_bufs, len - tlen); in de4x5_alloc_rx_buff()
3636 skb_put_data(p, lp->rx_bufs + lp->rx_old * RX_BUFF_SZ, len); in de4x5_alloc_rx_buff()
3649 for (i=0; i<lp->rxRingSize; i++) { in de4x5_free_rx_buffs()
3650 if ((u_long) lp->rx_skb[i] > 1) { in de4x5_free_rx_buffs()
3651 dev_kfree_skb(lp->rx_skb[i]); in de4x5_free_rx_buffs()
3653 lp->rx_ring[i].status = 0; in de4x5_free_rx_buffs()
3654 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */ in de4x5_free_rx_buffs()
3664 for (i=0; i<lp->txRingSize; i++) { in de4x5_free_tx_buffs()
3665 if (lp->tx_skb[i]) in de4x5_free_tx_buffs()
3667 lp->tx_ring[i].status = 0; in de4x5_free_tx_buffs()
3671 __skb_queue_purge(&lp->cache.queue); in de4x5_free_tx_buffs()
3676 ** 'running - waiting for end of transmission' state. This means that we
3685 u_long iobase = dev->base_addr; in de4x5_save_skbs()
3688 if (!lp->cache.save_cnt) { in de4x5_save_skbs()
3695 lp->cache.save_cnt++; in de4x5_save_skbs()
3704 u_long iobase = dev->base_addr; in de4x5_rst_desc_ring()
3708 if (lp->cache.save_cnt) { in de4x5_rst_desc_ring()
3710 outl(lp->dma_rings, DE4X5_RRBA); in de4x5_rst_desc_ring()
3711 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), in de4x5_rst_desc_ring()
3714 lp->rx_new = lp->rx_old = 0; in de4x5_rst_desc_ring()
3715 lp->tx_new = lp->tx_old = 0; in de4x5_rst_desc_ring()
3717 for (i = 0; i < lp->rxRingSize; i++) { in de4x5_rst_desc_ring()
3718 lp->rx_ring[i].status = cpu_to_le32(R_OWN); in de4x5_rst_desc_ring()
3721 for (i = 0; i < lp->txRingSize; i++) { in de4x5_rst_desc_ring()
3722 lp->tx_ring[i].status = cpu_to_le32(0); in de4x5_rst_desc_ring()
3726 lp->cache.save_cnt--; in de4x5_rst_desc_ring()
3735 u_long iobase = dev->base_addr; in de4x5_cache_state()
3739 lp->cache.csr0 = inl(DE4X5_BMR); in de4x5_cache_state()
3740 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR)); in de4x5_cache_state()
3741 lp->cache.csr7 = inl(DE4X5_IMR); in de4x5_cache_state()
3745 outl(lp->cache.csr0, DE4X5_BMR); in de4x5_cache_state()
3746 outl(lp->cache.csr6, DE4X5_OMR); in de4x5_cache_state()
3747 outl(lp->cache.csr7, DE4X5_IMR); in de4x5_cache_state()
3748 if (lp->chipset == DC21140) { in de4x5_cache_state()
3749 gep_wr(lp->cache.gepc, dev); in de4x5_cache_state()
3750 gep_wr(lp->cache.gep, dev); in de4x5_cache_state()
3752 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, in de4x5_cache_state()
3753 lp->cache.csr15); in de4x5_cache_state()
3764 __skb_queue_tail(&lp->cache.queue, skb); in de4x5_put_cache()
3772 __skb_queue_head(&lp->cache.queue, skb); in de4x5_putb_cache()
3780 return __skb_dequeue(&lp->cache.queue); in de4x5_get_cache()
3785 ** is received and the auto-negotiation status is NWAY OK.
3791 u_long iobase = dev->base_addr; in test_ans()
3794 if (lp->timeout < 0) { in test_ans()
3795 lp->timeout = msec/100; in test_ans()
3806 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) { in test_ans()
3809 lp->timeout = -1; in test_ans()
3819 u_long iobase = dev->base_addr; in de4x5_setup_intr()
3838 u_long iobase = dev->base_addr; in reset_init_sia()
3841 if (lp->useSROM) { in reset_init_sia()
3842 if (lp->ibn == 3) { in reset_init_sia()
3843 srom_exec(dev, lp->phy[lp->active].rst); in reset_init_sia()
3844 srom_exec(dev, lp->phy[lp->active].gep); in reset_init_sia()
3848 csr15 = lp->cache.csr15; in reset_init_sia()
3849 csr14 = lp->cache.csr14; in reset_init_sia()
3850 csr13 = lp->cache.csr13; in reset_init_sia()
3851 outl(csr15 | lp->cache.gepc, DE4X5_SIGR); in reset_init_sia()
3852 outl(csr15 | lp->cache.gep, DE4X5_SIGR); in reset_init_sia()
3873 *buf++ = dev->dev_addr[i]; in create_packet()
3876 *buf++ = dev->dev_addr[i]; in create_packet()
3894 i = edev->id.driver_data; in EISA_signature()
3912 if (lp->chipset == DC21040) { in PCI_signature()
3915 } else { /* Search for a DEC name in the SROM */ in PCI_signature()
3916 int tmp = *((char *)&lp->srom + 19) * 3; in PCI_signature()
3917 strncpy(name, (char *)&lp->srom + 26 + tmp, 8); in PCI_signature()
3927 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" : in PCI_signature()
3928 ((lp->chipset == DC21041) ? "DC21041" : in PCI_signature()
3929 ((lp->chipset == DC21140) ? "DC21140" : in PCI_signature()
3930 ((lp->chipset == DC21142) ? "DC21142" : in PCI_signature()
3931 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN" in PCI_signature()
3934 if (lp->chipset != DC21041) { in PCI_signature()
3935 lp->useSROM = true; /* card is not recognisably DEC */ in PCI_signature()
3937 } else if ((lp->chipset & ~0x00ff) == DC2114x) { in PCI_signature()
3938 lp->useSROM = true; in PCI_signature()
3944 ** the DC21040, else read the SROM for the other chips.
3945 ** The SROM may not be present in a multi-MAC card, so first read the
3947 ** immediately with the prior srom contents intact (the h/w address will
3956 if (lp->chipset == DC21040) { in DevicePresent()
3957 if (lp->bus == EISA) { in DevicePresent()
3962 } else { /* Read new srom */ in DevicePresent()
3964 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD); in DevicePresent()
3971 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */ in DevicePresent()
3975 p = (__le16 *)&lp->srom; in DevicePresent()
3980 de4x5_dbg_srom(&lp->srom); in DevicePresent()
4007 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) { in enet_addr_rst()
4022 ** For the bad status case and no SROM, then add one to the previous
4025 ** as the first three are invariant - assigned to an organisation.
4030 u_long iobase = dev->base_addr; in get_hw_addr()
4039 if (k > 0xffff) k-=0xffff; in get_hw_addr()
4041 if (lp->bus == PCI) { in get_hw_addr()
4042 if (lp->chipset == DC21040) { in get_hw_addr()
4045 dev->dev_addr[i++] = (u_char) tmp; in get_hw_addr()
4048 dev->dev_addr[i++] = (u_char) tmp; in get_hw_addr()
4050 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++; in get_hw_addr()
4051 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++; in get_hw_addr()
4053 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++; in get_hw_addr()
4054 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++; in get_hw_addr()
4058 dev->dev_addr[i++] = (u_char) tmp; in get_hw_addr()
4060 dev->dev_addr[i++] = (u_char) tmp; in get_hw_addr()
4063 if (k > 0xffff) k-=0xffff; in get_hw_addr()
4067 if (lp->bus == PCI) { in get_hw_addr()
4068 if (lp->chipset == DC21040) { in get_hw_addr()
4073 if ((k != chksum) && (dec_only)) status = -1; in get_hw_addr()
4078 if ((k != chksum) && (dec_only)) status = -1; in get_hw_addr()
4081 /* If possible, try to fix a broken card - SMC only so far */ in get_hw_addr()
4086 ** If the address starts with 00 a0, we have to bit-reverse in get_hw_addr()
4090 (dev->dev_addr[0] == 0) && in get_hw_addr()
4091 (dev->dev_addr[1] == 0xa0) ) in get_hw_addr()
4095 int x = dev->dev_addr[i]; in get_hw_addr()
4098 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1); in get_hw_addr()
4118 if (!memcmp(&lp->srom, &enet_det[i], 3) && in de4x5_bad_srom()
4119 !memcmp((char *)&lp->srom+0x10, &enet_det[i], 3)) { in de4x5_bad_srom()
4139 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom)); in srom_repair()
4140 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN); in srom_repair()
4141 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100); in srom_repair()
4142 lp->useSROM = true; in srom_repair()
4148 ** Assume that the irq's do not follow the PCI spec - this is seems
4157 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i]; in test_bad_enet()
4159 if ((lp->chipset == last.chipset) && in test_bad_enet()
4160 (lp->bus_num == last.bus) && (lp->bus_num > 0)) { in test_bad_enet()
4161 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i]; in test_bad_enet()
4162 for (i=ETH_ALEN-1; i>2; --i) { in test_bad_enet()
4163 dev->dev_addr[i] += 1; in test_bad_enet()
4164 if (dev->dev_addr[i] != 0) break; in test_bad_enet()
4166 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i]; in test_bad_enet()
4168 dev->irq = last.irq; in test_bad_enet()
4174 last.chipset = lp->chipset; in test_bad_enet()
4175 last.bus = lp->bus_num; in test_bad_enet()
4176 last.irq = dev->irq; in test_bad_enet()
4177 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i]; in test_bad_enet()
4189 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) && in an_exception()
4190 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) { in an_exception()
4191 return -1; in an_exception()
4198 ** SROM Read
4303 if (lp->chipset == infoleaf_array[i].chipset) break; in srom_infoleaf_info()
4306 lp->useSROM = false; in srom_infoleaf_info()
4307 printk("%s: Cannot find correct chipset for SROM decoding!\n", in srom_infoleaf_info()
4308 dev->name); in srom_infoleaf_info()
4309 return -ENXIO; in srom_infoleaf_info()
4312 lp->infoleaf_fn = infoleaf_array[i].fn; in srom_infoleaf_info()
4315 count = *((u_char *)&lp->srom + 19); in srom_infoleaf_info()
4316 p = (u_char *)&lp->srom + 26; in srom_infoleaf_info()
4319 for (i=count; i; --i, p+=3) { in srom_infoleaf_info()
4320 if (lp->device == *p) break; in srom_infoleaf_info()
4323 lp->useSROM = false; in srom_infoleaf_info()
4324 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n", in srom_infoleaf_info()
4325 dev->name, lp->device); in srom_infoleaf_info()
4326 return -ENXIO; in srom_infoleaf_info()
4330 lp->infoleaf_offset = get_unaligned_le16(p + 1); in srom_infoleaf_info()
4340 ** will follow the discovery process from MII address 1-31 then 0.
4346 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; in srom_init()
4350 if (lp->chipset == DC21140) { in srom_init()
4351 lp->cache.gepc = (*p++ | GEP_CTRL); in srom_init()
4352 gep_wr(lp->cache.gepc, dev); in srom_init()
4359 for (;count; --count) { in srom_init()
4389 u_long iobase = dev->base_addr; in srom_exec()
4393 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return; in srom_exec()
4395 if (lp->chipset != DC21140) RESET_SIA; in srom_exec()
4397 while (count--) { in srom_exec()
4398 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ? in srom_exec()
4403 if (lp->chipset != DC21140) { in srom_exec()
4404 outl(lp->cache.csr14, DE4X5_STRR); in srom_exec()
4405 outl(lp->cache.csr13, DE4X5_SICR); in srom_exec()
4411 ** unless I implement the DC21041 SROM functions. There's no need
4425 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; in dc21140_infoleaf()
4432 lp->cache.gepc = (*p++ | GEP_CTRL); in dc21140_infoleaf()
4444 if (lp->tcount == count) { in dc21140_infoleaf()
4445 lp->media = NC; in dc21140_infoleaf()
4446 if (lp->media != lp->c_media) { in dc21140_infoleaf()
4448 lp->c_media = lp->media; in dc21140_infoleaf()
4450 lp->media = INIT; in dc21140_infoleaf()
4451 lp->tcount = 0; in dc21140_infoleaf()
4452 lp->tx_enable = false; in dc21140_infoleaf()
4463 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; in dc21142_infoleaf()
4479 if (lp->tcount == count) { in dc21142_infoleaf()
4480 lp->media = NC; in dc21142_infoleaf()
4481 if (lp->media != lp->c_media) { in dc21142_infoleaf()
4483 lp->c_media = lp->media; in dc21142_infoleaf()
4485 lp->media = INIT; in dc21142_infoleaf()
4486 lp->tcount = 0; in dc21142_infoleaf()
4487 lp->tx_enable = false; in dc21142_infoleaf()
4498 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; in dc21143_infoleaf()
4513 if (lp->tcount == count) { in dc21143_infoleaf()
4514 lp->media = NC; in dc21143_infoleaf()
4515 if (lp->media != lp->c_media) { in dc21143_infoleaf()
4517 lp->c_media = lp->media; in dc21143_infoleaf()
4519 lp->media = INIT; in dc21143_infoleaf()
4520 lp->tcount = 0; in dc21143_infoleaf()
4521 lp->tx_enable = false; in dc21143_infoleaf()
4538 if (--count > lp->tcount) { in compact_infoblock()
4546 if ((lp->media == INIT) && (lp->timeout < 0)) { in compact_infoblock()
4547 lp->ibn = COMPACT; in compact_infoblock()
4548 lp->active = 0; in compact_infoblock()
4549 gep_wr(lp->cache.gepc, dev); in compact_infoblock()
4550 lp->infoblock_media = (*p++) & COMPACT_MC; in compact_infoblock()
4551 lp->cache.gep = *p++; in compact_infoblock()
4555 lp->asBitValid = (flags & 0x80) ? 0 : -1; in compact_infoblock()
4556 lp->defMedium = (flags & 0x40) ? -1 : 0; in compact_infoblock()
4557 lp->asBit = 1 << ((csr6 >> 1) & 0x07); in compact_infoblock()
4558 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; in compact_infoblock()
4559 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); in compact_infoblock()
4560 lp->useMII = false; in compact_infoblock()
4578 if (--count > lp->tcount) { in type0_infoblock()
4586 if ((lp->media == INIT) && (lp->timeout < 0)) { in type0_infoblock()
4587 lp->ibn = 0; in type0_infoblock()
4588 lp->active = 0; in type0_infoblock()
4589 gep_wr(lp->cache.gepc, dev); in type0_infoblock()
4591 lp->infoblock_media = (*p++) & BLOCK0_MC; in type0_infoblock()
4592 lp->cache.gep = *p++; in type0_infoblock()
4596 lp->asBitValid = (flags & 0x80) ? 0 : -1; in type0_infoblock()
4597 lp->defMedium = (flags & 0x40) ? -1 : 0; in type0_infoblock()
4598 lp->asBit = 1 << ((csr6 >> 1) & 0x07); in type0_infoblock()
4599 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; in type0_infoblock()
4600 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); in type0_infoblock()
4601 lp->useMII = false; in type0_infoblock()
4618 if (--count > lp->tcount) { in type1_infoblock()
4627 if (lp->state == INITIALISED) { in type1_infoblock()
4628 lp->ibn = 1; in type1_infoblock()
4629 lp->active = *p++; in type1_infoblock()
4630 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1); in type1_infoblock()
4631 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1); in type1_infoblock()
4632 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2; in type1_infoblock()
4633 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2; in type1_infoblock()
4634 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2; in type1_infoblock()
4635 lp->phy[lp->active].ttm = get_unaligned_le16(p); in type1_infoblock()
4637 } else if ((lp->media == INIT) && (lp->timeout < 0)) { in type1_infoblock()
4638 lp->ibn = 1; in type1_infoblock()
4639 lp->active = *p; in type1_infoblock()
4640 lp->infoblock_csr6 = OMR_MII_100; in type1_infoblock()
4641 lp->useMII = true; in type1_infoblock()
4642 lp->infoblock_media = ANS; in type1_infoblock()
4657 if (--count > lp->tcount) { in type2_infoblock()
4665 if ((lp->media == INIT) && (lp->timeout < 0)) { in type2_infoblock()
4666 lp->ibn = 2; in type2_infoblock()
4667 lp->active = 0; in type2_infoblock()
4669 lp->infoblock_media = (*p) & MEDIA_CODE; in type2_infoblock()
4672 lp->cache.csr13 = get_unaligned_le16(p); p += 2; in type2_infoblock()
4673 lp->cache.csr14 = get_unaligned_le16(p); p += 2; in type2_infoblock()
4674 lp->cache.csr15 = get_unaligned_le16(p); p += 2; in type2_infoblock()
4676 lp->cache.csr13 = CSR13; in type2_infoblock()
4677 lp->cache.csr14 = CSR14; in type2_infoblock()
4678 lp->cache.csr15 = CSR15; in type2_infoblock()
4680 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2; in type2_infoblock()
4681 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); in type2_infoblock()
4682 lp->infoblock_csr6 = OMR_SIA; in type2_infoblock()
4683 lp->useMII = false; in type2_infoblock()
4698 if (--count > lp->tcount) { in type3_infoblock()
4707 if (lp->state == INITIALISED) { in type3_infoblock()
4708 lp->ibn = 3; in type3_infoblock()
4709 lp->active = *p++; in type3_infoblock()
4710 if (MOTO_SROM_BUG) lp->active = 0; in type3_infoblock()
4711 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1); in type3_infoblock()
4712 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1); in type3_infoblock()
4713 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2; in type3_infoblock()
4714 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2; in type3_infoblock()
4715 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2; in type3_infoblock()
4716 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2; in type3_infoblock()
4717 lp->phy[lp->active].mci = *p; in type3_infoblock()
4719 } else if ((lp->media == INIT) && (lp->timeout < 0)) { in type3_infoblock()
4720 lp->ibn = 3; in type3_infoblock()
4721 lp->active = *p; in type3_infoblock()
4722 if (MOTO_SROM_BUG) lp->active = 0; in type3_infoblock()
4723 lp->infoblock_csr6 = OMR_MII_100; in type3_infoblock()
4724 lp->useMII = true; in type3_infoblock()
4725 lp->infoblock_media = ANS; in type3_infoblock()
4740 if (--count > lp->tcount) { in type4_infoblock()
4748 if ((lp->media == INIT) && (lp->timeout < 0)) { in type4_infoblock()
4749 lp->ibn = 4; in type4_infoblock()
4750 lp->active = 0; in type4_infoblock()
4752 lp->infoblock_media = (*p++) & MEDIA_CODE; in type4_infoblock()
4753 lp->cache.csr13 = CSR13; /* Hard coded defaults */ in type4_infoblock()
4754 lp->cache.csr14 = CSR14; in type4_infoblock()
4755 lp->cache.csr15 = CSR15; in type4_infoblock()
4756 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2; in type4_infoblock()
4757 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2; in type4_infoblock()
4761 lp->asBitValid = (flags & 0x80) ? 0 : -1; in type4_infoblock()
4762 lp->defMedium = (flags & 0x40) ? -1 : 0; in type4_infoblock()
4763 lp->asBit = 1 << ((csr6 >> 1) & 0x07); in type4_infoblock()
4764 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; in type4_infoblock()
4765 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); in type4_infoblock()
4766 lp->useMII = false; in type4_infoblock()
4785 if (--count > lp->tcount) { in type5_infoblock()
4794 if ((lp->state == INITIALISED) || (lp->media == INIT)) { in type5_infoblock()
4796 lp->rst = p; in type5_infoblock()
4797 srom_exec(dev, lp->rst); in type5_infoblock()
4815 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */ in mii_rd()
4828 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */ in mii_wr()
4877 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */ in mii_ta()
4966 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
4972 u_long iobase = dev->base_addr; in mii_get_phy()
4976 lp->active = 0; in mii_get_phy()
4977 lp->useMII = true; in mii_get_phy()
4980 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) { in mii_get_phy()
4981 lp->phy[lp->active].addr = i; in mii_get_phy()
4988 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++); in mii_get_phy()
4990 memcpy((char *)&lp->phy[k], in mii_get_phy()
4992 lp->phy[k].addr = i; in mii_get_phy()
4993 lp->mii_cnt++; in mii_get_phy()
4994 lp->active++; in mii_get_phy()
5001 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++); in mii_get_phy()
5002 lp->phy[k].addr = i; in mii_get_phy()
5003 lp->phy[k].id = id; in mii_get_phy()
5004 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */ in mii_get_phy()
5005 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */ in mii_get_phy()
5006 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */ in mii_get_phy()
5007 lp->mii_cnt++; in mii_get_phy()
5008 lp->active++; in mii_get_phy()
5009 …ntrol. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name); in mii_get_phy()
5018 lp->active = 0; in mii_get_phy()
5019 if (lp->phy[0].id) { /* Reset the PHY devices */ in mii_get_phy()
5020 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/ in mii_get_phy()
5021 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII); in mii_get_phy()
5022 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST); in mii_get_phy()
5027 if (!lp->mii_cnt) lp->useMII = false; in mii_get_phy()
5029 return lp->mii_cnt; in mii_get_phy()
5037 char *pa = lp->setup_frame; in build_setup_frame()
5041 memset(lp->setup_frame, 0, SETUP_FRAME_LEN); in build_setup_frame()
5044 if (lp->setup_f == HASH_PERF) { in build_setup_frame()
5045 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) { in build_setup_frame()
5046 *(pa + i) = dev->dev_addr[i]; /* Host address */ in build_setup_frame()
5049 *(lp->setup_frame + (DE4X5_HASH_TABLE_LEN >> 3) - 3) = 0x80; in build_setup_frame()
5052 *(pa + (i&1)) = dev->dev_addr[i]; in build_setup_frame()
5068 del_timer_sync(&lp->timer); in disable_ast()
5075 u_long iobase = dev->base_addr; in de4x5_switch_mac_port()
5083 omr |= lp->infoblock_csr6; in de4x5_switch_mac_port()
5090 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */ in de4x5_switch_mac_port()
5091 if (lp->chipset == DC21140) { in de4x5_switch_mac_port()
5092 gep_wr(lp->cache.gepc, dev); in de4x5_switch_mac_port()
5093 gep_wr(lp->cache.gep, dev); in de4x5_switch_mac_port()
5094 } else if ((lp->chipset & ~0x0ff) == DC2114x) { in de4x5_switch_mac_port()
5095 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15); in de4x5_switch_mac_port()
5111 u_long iobase = dev->base_addr; in gep_wr()
5113 if (lp->chipset == DC21140) { in gep_wr()
5115 } else if ((lp->chipset & ~0x00ff) == DC2114x) { in gep_wr()
5116 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR); in gep_wr()
5124 u_long iobase = dev->base_addr; in gep_rd()
5126 if (lp->chipset == DC21140) { in gep_rd()
5128 } else if ((lp->chipset & ~0x00ff) == DC2114x) { in gep_rd()
5139 u_long iobase = dev->base_addr; in yawn()
5141 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return; in yawn()
5143 if(lp->bus == EISA) { in yawn()
5160 struct pci_dev *pdev = to_pci_dev (lp->gendev); in yawn()
5185 lp->params.fdx = false; in de4x5_parse_params()
5186 lp->params.autosense = AUTO; in de4x5_parse_params()
5190 if ((p = strstr(args, dev->name))) { in de4x5_parse_params()
5191 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p); in de4x5_parse_params()
5195 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = true; in de4x5_parse_params()
5199 lp->params.autosense = TP_NW; in de4x5_parse_params()
5201 lp->params.autosense = TP; in de4x5_parse_params()
5203 lp->params.autosense = BNC; in de4x5_parse_params()
5205 lp->params.autosense = BNC; in de4x5_parse_params()
5207 lp->params.autosense = AUI; in de4x5_parse_params()
5209 lp->params.autosense = _10Mb; in de4x5_parse_params()
5211 lp->params.autosense = _100Mb; in de4x5_parse_params()
5213 lp->params.autosense = AUTO; in de4x5_parse_params()
5227 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq); in de4x5_dbg_open()
5228 printk("\tphysical address: %pM\n", dev->dev_addr); in de4x5_dbg_open()
5230 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring); in de4x5_dbg_open()
5232 for (i=0;i<lp->rxRingSize-1;i++){ in de4x5_dbg_open()
5234 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status); in de4x5_dbg_open()
5237 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status); in de4x5_dbg_open()
5239 for (i=0;i<lp->txRingSize-1;i++){ in de4x5_dbg_open()
5241 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status); in de4x5_dbg_open()
5244 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status); in de4x5_dbg_open()
5246 for (i=0;i<lp->rxRingSize-1;i++){ in de4x5_dbg_open()
5248 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf)); in de4x5_dbg_open()
5251 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf)); in de4x5_dbg_open()
5253 for (i=0;i<lp->txRingSize-1;i++){ in de4x5_dbg_open()
5255 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf)); in de4x5_dbg_open()
5258 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf)); in de4x5_dbg_open()
5260 (short)lp->rxRingSize, in de4x5_dbg_open()
5261 (short)lp->txRingSize); in de4x5_dbg_open()
5269 u_long iobase = dev->base_addr; in de4x5_dbg_mii()
5272 printk("\nMII device address: %d\n", lp->phy[k].addr); in de4x5_dbg_mii()
5273 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5274 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5275 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5276 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5277 if (lp->phy[k].id != BROADCOM_T4) { in de4x5_dbg_mii()
5278 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5279 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5281 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5282 if (lp->phy[k].id != BROADCOM_T4) { in de4x5_dbg_mii()
5283 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5284 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5286 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5296 if (lp->media != lp->c_media) { in de4x5_dbg_media()
5298 printk("%s: media is %s%s\n", dev->name, in de4x5_dbg_media()
5299 (lp->media == NC ? "unconnected, link down or incompatible connection" : in de4x5_dbg_media()
5300 (lp->media == TP ? "TP" : in de4x5_dbg_media()
5301 (lp->media == ANS ? "TP/Nway" : in de4x5_dbg_media()
5302 (lp->media == BNC ? "BNC" : in de4x5_dbg_media()
5303 (lp->media == AUI ? "AUI" : in de4x5_dbg_media()
5304 (lp->media == BNC_AUI ? "BNC/AUI" : in de4x5_dbg_media()
5305 (lp->media == EXT_SIA ? "EXT SIA" : in de4x5_dbg_media()
5306 (lp->media == _100Mb ? "100Mb/s" : in de4x5_dbg_media()
5307 (lp->media == _10Mb ? "10Mb/s" : in de4x5_dbg_media()
5309 ))))))))), (lp->fdx?" full duplex.":".")); in de4x5_dbg_media()
5311 lp->c_media = lp->media; in de4x5_dbg_media()
5321 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id)); in de4x5_dbg_srom()
5322 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id)); in de4x5_dbg_srom()
5323 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc)); in de4x5_dbg_srom()
5324 printk("SROM version: %02x\n", (u_char)(p->version)); in de4x5_dbg_srom()
5325 printk("# controllers: %02x\n", (u_char)(p->num_controllers)); in de4x5_dbg_srom()
5327 printk("Hardware Address: %pM\n", p->ieee_addr); in de4x5_dbg_srom()
5328 printk("CRC checksum: %04x\n", (u_short)(p->chksum)); in de4x5_dbg_srom()
5341 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n", in de4x5_dbg_rx()
5342 skb->data, &skb->data[6], in de4x5_dbg_rx()
5343 (u_char)skb->data[12], in de4x5_dbg_rx()
5344 (u_char)skb->data[13], in de4x5_dbg_rx()
5346 for (j=0; len>0;j+=16, len-=16) { in de4x5_dbg_rx()
5349 printk("%02x ",(u_char)skb->data[i+j]); in de4x5_dbg_rx()
5365 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru; in de4x5_siocdevprivate()
5366 u_long iobase = dev->base_addr; in de4x5_siocdevprivate()
5377 return -EOPNOTSUPP; in de4x5_siocdevprivate()
5379 switch(ioc->cmd) { in de4x5_siocdevprivate()
5381 ioc->len = ETH_ALEN; in de4x5_siocdevprivate()
5383 tmp.addr[i] = dev->dev_addr[i]; in de4x5_siocdevprivate()
5385 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; in de4x5_siocdevprivate()
5389 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_siocdevprivate()
5390 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT; in de4x5_siocdevprivate()
5392 return -EBUSY; in de4x5_siocdevprivate()
5395 dev->dev_addr[i] = tmp.addr[i]; in de4x5_siocdevprivate()
5399 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | in de4x5_siocdevprivate()
5401 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in de4x5_siocdevprivate()
5407 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_siocdevprivate()
5408 printk("%s: Boo!\n", dev->name); in de4x5_siocdevprivate()
5412 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_siocdevprivate()
5421 ioc->len = sizeof(statbuf); in de4x5_siocdevprivate()
5422 spin_lock_irqsave(&lp->lock, flags); in de4x5_siocdevprivate()
5423 memcpy(&statbuf, &lp->pktStats, ioc->len); in de4x5_siocdevprivate()
5424 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_siocdevprivate()
5425 if (copy_to_user(ioc->data, &statbuf, ioc->len)) in de4x5_siocdevprivate()
5426 return -EFAULT; in de4x5_siocdevprivate()
5430 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_siocdevprivate()
5431 spin_lock_irqsave(&lp->lock, flags); in de4x5_siocdevprivate()
5432 memset(&lp->pktStats, 0, sizeof(lp->pktStats)); in de4x5_siocdevprivate()
5433 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_siocdevprivate()
5438 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT; in de4x5_siocdevprivate()
5442 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_siocdevprivate()
5443 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT; in de4x5_siocdevprivate()
5457 ioc->len = j; in de4x5_siocdevprivate()
5458 if (copy_to_user(ioc->data, tmp.lval, ioc->len)) in de4x5_siocdevprivate()
5459 return -EFAULT; in de4x5_siocdevprivate()
5466 tmp.addr[j++] = dev->irq; in de4x5_siocdevprivate()
5468 tmp.addr[j++] = dev->dev_addr[i]; in de4x5_siocdevprivate()
5470 tmp.addr[j++] = lp->rxRingSize; in de4x5_siocdevprivate()
5471 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4; in de4x5_siocdevprivate()
5472 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4; in de4x5_siocdevprivate()
5474 for (i=0;i<lp->rxRingSize-1;i++){ in de4x5_siocdevprivate()
5476 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4; in de4x5_siocdevprivate()
5479 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4; in de4x5_siocdevprivate()
5480 for (i=0;i<lp->txRingSize-1;i++){ in de4x5_siocdevprivate()
5482 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4; in de4x5_siocdevprivate()
5485 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4; in de4x5_siocdevprivate()
5487 for (i=0;i<lp->rxRingSize-1;i++){ in de4x5_siocdevprivate()
5489 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4; in de4x5_siocdevprivate()
5492 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4; in de4x5_siocdevprivate()
5493 for (i=0;i<lp->txRingSize-1;i++){ in de4x5_siocdevprivate()
5495 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4; in de4x5_siocdevprivate()
5498 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4; in de4x5_siocdevprivate()
5500 for (i=0;i<lp->rxRingSize;i++){ in de4x5_siocdevprivate()
5501 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4; in de4x5_siocdevprivate()
5503 for (i=0;i<lp->txRingSize;i++){ in de4x5_siocdevprivate()
5504 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4; in de4x5_siocdevprivate()
5515 tmp.lval[j>>2] = lp->chipset; j+=4; in de4x5_siocdevprivate()
5516 if (lp->chipset == DC21140) { in de4x5_siocdevprivate()
5524 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4; in de4x5_siocdevprivate()
5525 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { in de4x5_siocdevprivate()
5526 tmp.lval[j>>2] = lp->active; j+=4; in de4x5_siocdevprivate()
5527 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5528 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5529 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5530 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5531 if (lp->phy[lp->active].id != BROADCOM_T4) { in de4x5_siocdevprivate()
5532 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5533 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5535 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5536 if (lp->phy[lp->active].id != BROADCOM_T4) { in de4x5_siocdevprivate()
5537 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5538 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5540 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_siocdevprivate()
5544 tmp.addr[j++] = lp->txRingSize; in de4x5_siocdevprivate()
5547 ioc->len = j; in de4x5_siocdevprivate()
5548 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; in de4x5_siocdevprivate()
5553 return -EOPNOTSUPP; in de4x5_siocdevprivate()