Lines Matching +full:1000 +full:base +full:- +full:kx
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
117 while (nregs--) { in t4_read_indirect()
125 * t4_write_indirect - write indirectly addressed registers
140 while (nregs--) { in t4_write_indirect()
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg); in t4_hw_pci_read_cfg4()
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_hw_pci_read_cfg4()
161 if (is_t4(adap->params.chip)) in t4_hw_pci_read_cfg4()
170 * read-modify-write via t4_set_reg_field().) in t4_hw_pci_read_cfg4()
176 * t4_report_fw_error - report firmware error
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", in t4_report_fw_error()
201 adap->flags &= ~CXGB4_FW_OK; in t4_report_fw_error()
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
211 for ( ; nflit; nflit--, mbox_addr += 8) in get_mbox_rpl()
223 dev_alert(adap->pdev_dev, in fw_asrt()
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
241 struct mbox_cmd_log *log = adapter->mbox_log; in t4_record_mbox()
245 entry = mbox_cmd_log_entry(log, log->cursor++); in t4_record_mbox()
246 if (log->cursor == log->size) in t4_record_mbox()
247 log->cursor = 0; in t4_record_mbox()
250 entry->cmd[i] = be64_to_cpu(cmd[i]); in t4_record_mbox()
252 entry->cmd[i++] = 0; in t4_record_mbox()
253 entry->timestamp = jiffies; in t4_record_mbox()
254 entry->seqno = log->seqno++; in t4_record_mbox()
255 entry->access = access; in t4_record_mbox()
256 entry->execute = execute; in t4_record_mbox()
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
302 return -EINVAL; in t4_wr_mbox_meat_timeout()
305 * If the device is off-line, as in EEH, commands will time out. in t4_wr_mbox_meat_timeout()
308 if (adap->pdev->error_state != pci_channel_io_normal) in t4_wr_mbox_meat_timeout()
309 return -EIO; in t4_wr_mbox_meat_timeout()
314 timeout = -timeout; in t4_wr_mbox_meat_timeout()
322 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
323 list_add_tail(&entry.list, &adap->mlist.list); in t4_wr_mbox_meat_timeout()
324 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
337 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
339 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
340 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY; in t4_wr_mbox_meat_timeout()
348 if (list_first_entry(&adap->mlist.list, struct mbox_list, in t4_wr_mbox_meat_timeout()
355 if (delay_idx < ARRAY_SIZE(delay) - 1) in t4_wr_mbox_meat_timeout()
370 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
372 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
373 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT; in t4_wr_mbox_meat_timeout()
395 if (delay_idx < ARRAY_SIZE(delay) - 1) in t4_wr_mbox_meat_timeout()
423 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
425 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
426 return -FW_CMD_RETVAL_G((int)res); in t4_wr_mbox_meat_timeout()
430 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT; in t4_wr_mbox_meat_timeout()
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", in t4_wr_mbox_meat_timeout()
435 spin_lock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
437 spin_unlock_bh(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
454 if (is_t4(adap->params.chip)) { in t4_edc_err_read()
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
492 * @mem_base: configured memory base address.
495 * Get the configured memory window's relative offset, base, and size.
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller in t4_memory_rw_init()
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5) in t4_memory_rw_init()
520 /* Each PCI-E Memory Window is programmed with a window size -- or in t4_memory_rw_init()
521 * "aperture" -- which controls the granularity of its mapping onto in t4_memory_rw_init()
524 * with the base address of the Memory Window in BAR0's address in t4_memory_rw_init()
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5 in t4_memory_rw_init()
533 return -ENXIO; in t4_memory_rw_init()
537 if (is_t4(adap->params.chip)) in t4_memory_rw_init()
538 *mem_base -= adap->t4_bar0; in t4_memory_rw_init()
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
564 * t4_memory_rw_residual - Read/Write residual data.
571 * Read/Write residual data less than 32-bits.
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
608 * firmware memory address and host buffer must be aligned on 32-bit
611 * contains data structures which contain multi-byte integers, it's the
625 return -EINVAL; in t4_memory_rw()
629 * multiple of 32-bits because we often end up transferring files to in t4_memory_rw()
634 len -= resid; in t4_memory_rw()
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); in t4_memory_rw()
646 /* Calculate our initial PCI-E Memory Window Position and Offset into in t4_memory_rw()
649 pos = addr & ~(mem_aperture - 1); in t4_memory_rw()
650 offset = addr - pos; in t4_memory_rw()
652 /* Set up initial PCI-E Memory Window to cover the start of our in t4_memory_rw()
658 * number of 32-bit transfers to complete. in t4_memory_rw()
662 * The "register" reads and writes below from/to the PCI-E Memory in t4_memory_rw()
663 * Window invoke the standard adapter Big-Endian to PCI-E Link in t4_memory_rw()
664 * Little-Endian "swizzel." As a result, if we have the following in t4_memory_rw()
670 * Then a read of the adapter memory via the PCI-E Memory Window in t4_memory_rw()
677 * If this value is stored into local memory on a Little-Endian system in t4_memory_rw()
682 * But on a Big-Endian system, the store will show up in memory in t4_memory_rw()
688 * PCI-E Memory Window below by undoing the register read/write in t4_memory_rw()
699 len -= sizeof(__be32); in t4_memory_rw()
702 * move the PCI-E Memory Window on to the next. Note that in t4_memory_rw()
704 * the PCI-E Memory Window for a possible final residual in t4_memory_rw()
715 * 32-bits, now's where we need to finish off the transfer of the in t4_memory_rw()
716 * residual amount. The PCI-E Memory Window has already been moved in t4_memory_rw()
726 /* Return the specified PCI-E Configuration Space register from our Physical
736 * retrieve the specified PCI-E Configuration Space register. in t4_read_pcie_cfg4()
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf)); in t4_read_pcie_cfg4()
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), in t4_read_pcie_cfg4()
761 /* Read the desired Configuration Space register via the PCI-E in t4_read_pcie_cfg4()
768 /* Get the window based on base passed to it.
777 if (is_t4(adap->params.chip)) { in t4_get_window()
780 /* Truncation intentional: we only read the bottom 32-bits of in t4_get_window()
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor in t4_get_window()
785 * our Configuration Space and we need to set up the PCI-E in t4_get_window()
787 * be coming across the PCI-E link. in t4_get_window()
791 adap->t4_bar0 = bar0; in t4_get_window()
817 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X)); in t4_setup_memwin()
823 * t4_get_regs_len - return the size of the chips register set
830 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in t4_get_regs_len()
841 dev_err(adapter->pdev_dev, in t4_get_regs_len()
847 * t4_get_regs - read chip registers into provided buffer
2643 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_regs()
2665 dev_err(adap->pdev_dev, in t4_get_regs()
2695 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2698 * @sz: size of function-specific area
2705 * [0..1K) -> [31K..32K)
2706 * [1K..1K+A) -> [31K-A..31K)
2707 * [1K+A..ES) -> [0..ES-A-1K)
2717 return 31744 - fn + phys_addr - 1024; in t4_eeprom_ptov()
2719 return phys_addr - 1024 - fn; in t4_eeprom_ptov()
2720 return -EINVAL; in t4_eeprom_ptov()
2724 * t4_seeprom_wp - enable/disable EEPROM write protection
2733 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v); in t4_seeprom_wp()
2738 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2752 return -ENOMEM; in t4_get_raw_vpd_params()
2757 ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val); in t4_get_raw_vpd_params()
2763 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd); in t4_get_raw_vpd_params()
2774 dev_err(adapter->pdev_dev, "VPD checksum incorrect or missing\n"); in t4_get_raw_vpd_params()
2775 ret = -EINVAL; in t4_get_raw_vpd_params()
2796 memcpy(p->id, vpd + id, min_t(int, id_len, ID_LEN)); in t4_get_raw_vpd_params()
2797 strim(p->id); in t4_get_raw_vpd_params()
2798 memcpy(p->sn, vpd + sn, min_t(int, sn_len, SERNUM_LEN)); in t4_get_raw_vpd_params()
2799 strim(p->sn); in t4_get_raw_vpd_params()
2800 memcpy(p->pn, vpd + pn, min_t(int, pn_len, PN_LEN)); in t4_get_raw_vpd_params()
2801 strim(p->pn); in t4_get_raw_vpd_params()
2802 memcpy(p->na, vpd + na, min_t(int, na_len, MACADDR_LEN)); in t4_get_raw_vpd_params()
2803 strim((char *)p->na); in t4_get_raw_vpd_params()
2808 dev_err(adapter->pdev_dev, "error reading VPD\n"); in t4_get_raw_vpd_params()
2816 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2840 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_vpd_params()
2845 p->cclk = cclk_val; in t4_get_vpd_params()
2851 * t4_get_pfres - retrieve VF resource limits
2855 * function. The results are stored in @adapter->pfres.
2859 struct pf_resources *pfres = &adapter->params.pfres; in t4_get_pfres()
2871 FW_PFVF_CMD_PFN_V(adapter->pf) | in t4_get_pfres()
2874 v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl); in t4_get_pfres()
2881 pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word); in t4_get_pfres()
2882 pfres->niq = FW_PFVF_CMD_NIQ_G(word); in t4_get_pfres()
2885 pfres->neq = FW_PFVF_CMD_NEQ_G(word); in t4_get_pfres()
2886 pfres->pmask = FW_PFVF_CMD_PMASK_G(word); in t4_get_pfres()
2889 pfres->tc = FW_PFVF_CMD_TC_G(word); in t4_get_pfres()
2890 pfres->nvi = FW_PFVF_CMD_NVI_G(word); in t4_get_pfres()
2891 pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word); in t4_get_pfres()
2894 pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word); in t4_get_pfres()
2895 pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word); in t4_get_pfres()
2896 pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word); in t4_get_pfres()
2916 * sf1_read - read data from the serial flash
2933 return -EINVAL; in sf1_read()
2935 return -EBUSY; in sf1_read()
2937 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1)); in sf1_read()
2945 * sf1_write - write data to the serial flash
2960 return -EINVAL; in sf1_write()
2962 return -EBUSY; in sf1_write()
2965 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1)); in sf1_write()
2970 * flash_wait_op - wait for a flash operation to complete
2988 if (--attempts == 0) in flash_wait_op()
2989 return -EAGAIN; in flash_wait_op()
2996 * t4_read_flash - read words from serial flash
2999 * @nwords: how many 32-bit words to read
3003 * Read the specified number of 32-bit words from the serial flash.
3005 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3013 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) in t4_read_flash()
3014 return -EINVAL; in t4_read_flash()
3022 for ( ; nwords; nwords--, data++) { in t4_read_flash()
3035 * t4_write_flash - write up to a page of data to the serial flash
3045 * (i.e. matches what on disk), otherwise in big-endian.
3054 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) in t4_write_flash()
3055 return -EINVAL; in t4_write_flash()
3063 for (left = n; left; left -= c, data += c) { in t4_write_flash()
3069 val = (val << 8) + data[c - i - 1]; in t4_write_flash()
3088 if (memcmp(data - n, (u8 *)buf + offset, n)) { in t4_write_flash()
3089 dev_err(adapter->pdev_dev, in t4_write_flash()
3092 return -EIO; in t4_write_flash()
3102 * t4_get_fw_version - read the firmware version
3116 * t4_get_bs_version - read the firmware bootstrap version
3130 * t4_get_tp_version - read the TP microcode version
3144 * t4_get_exprom_version - return the Expansion ROM version (if any)
3151 * 0 on success, -ENOENT if no Expansion ROM is present.
3170 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) in t4_get_exprom_version()
3171 return -ENOENT; in t4_get_exprom_version()
3173 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) | in t4_get_exprom_version()
3174 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) | in t4_get_exprom_version()
3175 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) | in t4_get_exprom_version()
3176 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3])); in t4_get_exprom_version()
3181 * t4_get_vpd_version - return the VPD version
3191 * to retrieve the VPD version, so we zero-out the return-value parameter
3208 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_vpd_version()
3216 * t4_get_scfg_version - return the Serial Configuration version
3226 * to retrieve the Serial Configuration version, so we zero-out the
3227 * return-value parameter in that case to avoid leaving it with
3245 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_scfg_version()
3253 * t4_get_version_info - extract various chip/firmware version information
3272 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); in t4_get_version_info()
3273 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); in t4_get_version_info()
3274 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); in t4_get_version_info()
3275 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); in t4_get_version_info()
3276 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); in t4_get_version_info()
3277 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); in t4_get_version_info()
3284 * t4_dump_version_info - dump all of the adapter configuration IDs
3294 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n", in t4_dump_version_info()
3295 adapter->params.vpd.id, in t4_dump_version_info()
3296 CHELSIO_CHIP_RELEASE(adapter->params.chip)); in t4_dump_version_info()
3297 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n", in t4_dump_version_info()
3298 adapter->params.vpd.sn, adapter->params.vpd.pn); in t4_dump_version_info()
3301 if (!adapter->params.fw_vers) in t4_dump_version_info()
3302 dev_warn(adapter->pdev_dev, "No firmware loaded\n"); in t4_dump_version_info()
3304 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n", in t4_dump_version_info()
3305 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers), in t4_dump_version_info()
3306 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers), in t4_dump_version_info()
3307 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers), in t4_dump_version_info()
3308 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers)); in t4_dump_version_info()
3313 if (!adapter->params.bs_vers) in t4_dump_version_info()
3314 dev_info(adapter->pdev_dev, "No bootstrap loaded\n"); in t4_dump_version_info()
3316 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n", in t4_dump_version_info()
3317 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers), in t4_dump_version_info()
3318 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers), in t4_dump_version_info()
3319 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers), in t4_dump_version_info()
3320 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers)); in t4_dump_version_info()
3323 if (!adapter->params.tp_vers) in t4_dump_version_info()
3324 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n"); in t4_dump_version_info()
3326 dev_info(adapter->pdev_dev, in t4_dump_version_info()
3328 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers), in t4_dump_version_info()
3329 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers), in t4_dump_version_info()
3330 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers), in t4_dump_version_info()
3331 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers)); in t4_dump_version_info()
3334 if (!adapter->params.er_vers) in t4_dump_version_info()
3335 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n"); in t4_dump_version_info()
3337 dev_info(adapter->pdev_dev, in t4_dump_version_info()
3339 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers), in t4_dump_version_info()
3340 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers), in t4_dump_version_info()
3341 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers), in t4_dump_version_info()
3342 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers)); in t4_dump_version_info()
3345 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n", in t4_dump_version_info()
3346 adapter->params.scfg_vers); in t4_dump_version_info()
3349 dev_info(adapter->pdev_dev, "VPD version: %#x\n", in t4_dump_version_info()
3350 adapter->params.vpd_vers); in t4_dump_version_info()
3354 * t4_check_fw_version - check if the FW is supported with this driver
3365 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_check_fw_version()
3367 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
3369 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++) in t4_check_fw_version()
3370 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
3375 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers); in t4_check_fw_version()
3376 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers); in t4_check_fw_version()
3377 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers); in t4_check_fw_version()
3396 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n", in t4_check_fw_version()
3397 adap->chip); in t4_check_fw_version()
3398 return -EINVAL; in t4_check_fw_version()
3403 dev_err(adap->pdev_dev, in t4_check_fw_version()
3407 return -EFAULT; in t4_check_fw_version()
3419 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) in fw_compatible()
3422 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) in fw_compatible()
3423 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && in fw_compatible()
3453 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " in should_install_fs_fw()
3472 drv_fw = &fw_info->fw_hdr; in t4_prep_fw()
3481 dev_err(adap->pdev_dev, in t4_prep_fw()
3494 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && in t4_prep_fw()
3495 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { in t4_prep_fw()
3502 be32_to_cpu(fs_fw->fw_ver), in t4_prep_fw()
3503 be32_to_cpu(card_fw->fw_ver))) { in t4_prep_fw()
3504 ret = t4_fw_upgrade(adap, adap->mbox, fw_data, in t4_prep_fw()
3507 dev_err(adap->pdev_dev, in t4_prep_fw()
3521 d = be32_to_cpu(drv_fw->fw_ver); in t4_prep_fw()
3522 c = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
3523 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; in t4_prep_fw()
3525 dev_err(adap->pdev_dev, "Cannot find a usable firmware: " in t4_prep_fw()
3536 ret = -EINVAL; in t4_prep_fw()
3541 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
3542 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); in t4_prep_fw()
3549 * t4_flash_erase_sectors - erase a range of flash sectors
3560 if (end >= adapter->params.sf_nsec) in t4_flash_erase_sectors()
3561 return -EINVAL; in t4_flash_erase_sectors()
3568 dev_err(adapter->pdev_dev, in t4_flash_erase_sectors()
3580 * t4_flash_cfg_addr - return the address of the flash configuration file
3588 if (adapter->params.sf_size == 0x100000) in t4_flash_cfg_addr()
3605 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
3606 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) || in t4_fw_matches_chip()
3607 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6)) in t4_fw_matches_chip()
3610 dev_err(adap->pdev_dev, in t4_fw_matches_chip()
3612 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); in t4_fw_matches_chip()
3617 * t4_load_fw - download firmware
3632 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_fw()
3638 dev_err(adap->pdev_dev, "FW image has no data\n"); in t4_load_fw()
3639 return -EINVAL; in t4_load_fw()
3642 dev_err(adap->pdev_dev, in t4_load_fw()
3644 return -EINVAL; in t4_load_fw()
3646 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) { in t4_load_fw()
3647 dev_err(adap->pdev_dev, in t4_load_fw()
3649 return -EINVAL; in t4_load_fw()
3652 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", in t4_load_fw()
3654 return -EFBIG; in t4_load_fw()
3657 return -EINVAL; in t4_load_fw()
3663 dev_err(adap->pdev_dev, in t4_load_fw()
3665 return -EINVAL; in t4_load_fw()
3669 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); in t4_load_fw()
3679 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); in t4_load_fw()
3685 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in t4_load_fw()
3694 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, in t4_load_fw()
3698 dev_err(adap->pdev_dev, "firmware download failed, error %d\n", in t4_load_fw()
3701 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_load_fw()
3706 * t4_phy_fw_ver - return current PHY firmware version
3720 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_phy_fw_ver()
3722 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, in t4_phy_fw_ver()
3731 * t4_load_phy_fw - download port PHY firmware
3733 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3738 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3764 * already has up-to-date PHY firmware loaded. in t4_load_phy_fw()
3773 CH_WARN(adap, "PHY Firmware already up-to-date, " in t4_load_phy_fw()
3787 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3790 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1, in t4_load_phy_fw()
3800 spin_lock_bh(&adap->win0_lock); in t4_load_phy_fw()
3804 spin_unlock_bh(&adap->win0_lock); in t4_load_phy_fw()
3815 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3817 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, in t4_load_phy_fw()
3833 return -ENXIO; in t4_load_phy_fw()
3841 * t4_fwcache - firmware cache operation
3853 FW_PARAMS_CMD_PFN_V(adap->pf) | in t4_fwcache()
3861 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); in t4_fwcache()
3935 * Capabilities which we control with separate controls -- see, for instance,
3937 * full set of Advertised Port Capabilities are, the base Advertised Port
3946 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3947 * @caps16: a 16-bit Port Capabilities value
3949 * Returns the equivalent 32-bit Port Capabilities value.
3984 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3985 * @caps32: a 32-bit Port Capabilities value
3987 * Returns the equivalent 16-bit Port Capabilities value. Note that
3988 * not all 32-bit Port Capabilities can be represented in the 16-bit
4095 * t4_link_acaps - compute Link Advertised Port Capabilities
4101 * the base Advertised Port Capabilities (which have been filtered by
4112 fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps); in t4_link_acaps()
4117 fw_fc = cc_to_fwcap_pause(lc->requested_fc); in t4_link_acaps()
4122 * sent us as part of its IEEE 802.3-based interpretation of in t4_link_acaps()
4126 if (lc->requested_fec & FEC_AUTO) in t4_link_acaps()
4127 cc_fec = fwcap_to_cc_fec(lc->def_acaps); in t4_link_acaps()
4129 cc_fec = lc->requested_fec; in t4_link_acaps()
4136 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) { in t4_link_acaps()
4137 acaps = lc->acaps | fw_fc | fw_fec; in t4_link_acaps()
4138 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG; in t4_link_acaps()
4139 lc->fec = cc_fec; in t4_link_acaps()
4140 } else if (lc->autoneg == AUTONEG_DISABLE) { in t4_link_acaps()
4141 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi; in t4_link_acaps()
4142 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG; in t4_link_acaps()
4143 lc->fec = cc_fec; in t4_link_acaps()
4145 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi; in t4_link_acaps()
4156 if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) { in t4_link_acaps()
4157 …dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\… in t4_link_acaps()
4158 acaps, lc->pcaps); in t4_link_acaps()
4159 return -EINVAL; in t4_link_acaps()
4166 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4176 * - If the PHY can auto-negotiate first decide what to advertise, then
4177 * enable/disable auto-negotiation as desired, and reset.
4178 * - If the PHY does not auto-negotiate just reset it.
4179 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4180 * otherwise do it later based on the outcome of auto-negotiation.
4186 unsigned int fw_caps = adapter->params.fw_caps_support; in t4_link_l1cfg_core()
4191 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) && in t4_link_l1cfg_core()
4192 lc->autoneg == AUTONEG_ENABLE) { in t4_link_l1cfg_core()
4193 return -EINVAL; in t4_link_l1cfg_core()
4219 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward in t4_link_l1cfg_core()
4224 dev_err(adapter->pdev_dev, in t4_link_l1cfg_core()
4226 rcap, -ret); in t4_link_l1cfg_core()
4233 * t4_restart_aneg - restart autonegotiation
4242 unsigned int fw_caps = adap->params.fw_caps_support; in t4_restart_aneg()
4266 short stat_idx; /* stat counter to increment or -1 */
4268 int_handler_t int_handler; /* platform-specific int handler */
4272 * t4_handle_intr_status - table driven interrupt handler
4291 for ( ; acts->mask; ++acts) { in t4_handle_intr_status()
4292 if (!(status & acts->mask)) in t4_handle_intr_status()
4294 if (acts->fatal) { in t4_handle_intr_status()
4296 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, in t4_handle_intr_status()
4297 status & acts->mask); in t4_handle_intr_status()
4298 } else if (acts->msg && printk_ratelimit()) in t4_handle_intr_status()
4299 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg, in t4_handle_intr_status()
4300 status & acts->mask); in t4_handle_intr_status()
4301 if (acts->int_handler) in t4_handle_intr_status()
4302 acts->int_handler(adapter); in t4_handle_intr_status()
4303 mask |= acts->mask; in t4_handle_intr_status()
4317 { RNPP_F, "RXNP array parity error", -1, 1 }, in pcie_intr_handler()
4318 { RPCP_F, "RXPC array parity error", -1, 1 }, in pcie_intr_handler()
4319 { RCIP_F, "RXCIF array parity error", -1, 1 }, in pcie_intr_handler()
4320 { RCCP_F, "Rx completions control array parity error", -1, 1 }, in pcie_intr_handler()
4321 { RFTP_F, "RXFT array parity error", -1, 1 }, in pcie_intr_handler()
4325 { TPCP_F, "TXPC array parity error", -1, 1 }, in pcie_intr_handler()
4326 { TNPP_F, "TXNP array parity error", -1, 1 }, in pcie_intr_handler()
4327 { TFTP_F, "TXFT array parity error", -1, 1 }, in pcie_intr_handler()
4328 { TCAP_F, "TXCA array parity error", -1, 1 }, in pcie_intr_handler()
4329 { TCIP_F, "TXCIF array parity error", -1, 1 }, in pcie_intr_handler()
4330 { RCAP_F, "RXCA array parity error", -1, 1 }, in pcie_intr_handler()
4331 { OTDD_F, "outbound request TLP discarded", -1, 1 }, in pcie_intr_handler()
4332 { RDPE_F, "Rx data parity error", -1, 1 }, in pcie_intr_handler()
4333 { TDUE_F, "Tx uncorrectable data error", -1, 1 }, in pcie_intr_handler()
4337 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 }, in pcie_intr_handler()
4338 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 }, in pcie_intr_handler()
4339 { MSIDATAPERR_F, "MSI data parity error", -1, 1 }, in pcie_intr_handler()
4340 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, in pcie_intr_handler()
4341 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, in pcie_intr_handler()
4342 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, in pcie_intr_handler()
4343 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, in pcie_intr_handler()
4344 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 }, in pcie_intr_handler()
4345 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 }, in pcie_intr_handler()
4346 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, in pcie_intr_handler()
4347 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 }, in pcie_intr_handler()
4348 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, in pcie_intr_handler()
4349 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, in pcie_intr_handler()
4350 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 }, in pcie_intr_handler()
4351 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, in pcie_intr_handler()
4352 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, in pcie_intr_handler()
4353 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 }, in pcie_intr_handler()
4354 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, in pcie_intr_handler()
4355 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, in pcie_intr_handler()
4356 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, in pcie_intr_handler()
4357 { FIDPERR_F, "PCI FID parity error", -1, 1 }, in pcie_intr_handler()
4358 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 }, in pcie_intr_handler()
4359 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 }, in pcie_intr_handler()
4360 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, in pcie_intr_handler()
4361 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 }, in pcie_intr_handler()
4362 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 }, in pcie_intr_handler()
4363 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 }, in pcie_intr_handler()
4364 { PCIESINT_F, "PCI core secondary fault", -1, 1 }, in pcie_intr_handler()
4365 { PCIEPINT_F, "PCI core primary fault", -1, 1 }, in pcie_intr_handler()
4367 -1, 0 }, in pcie_intr_handler()
4373 -1, 1 }, in pcie_intr_handler()
4374 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, in pcie_intr_handler()
4375 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 }, in pcie_intr_handler()
4376 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, in pcie_intr_handler()
4377 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, in pcie_intr_handler()
4378 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, in pcie_intr_handler()
4379 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, in pcie_intr_handler()
4381 -1, 1 }, in pcie_intr_handler()
4383 -1, 1 }, in pcie_intr_handler()
4384 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, in pcie_intr_handler()
4385 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, in pcie_intr_handler()
4386 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, in pcie_intr_handler()
4387 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, in pcie_intr_handler()
4389 -1, 1 }, in pcie_intr_handler()
4390 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, in pcie_intr_handler()
4391 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, in pcie_intr_handler()
4392 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, in pcie_intr_handler()
4393 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, in pcie_intr_handler()
4394 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, in pcie_intr_handler()
4395 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, in pcie_intr_handler()
4396 { FIDPERR_F, "PCI FID parity error", -1, 1 }, in pcie_intr_handler()
4397 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, in pcie_intr_handler()
4398 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, in pcie_intr_handler()
4399 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, in pcie_intr_handler()
4401 -1, 1 }, in pcie_intr_handler()
4403 -1, 1 }, in pcie_intr_handler()
4404 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, in pcie_intr_handler()
4405 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, in pcie_intr_handler()
4406 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, in pcie_intr_handler()
4407 { READRSPERR_F, "Outbound read error", -1, 0 }, in pcie_intr_handler()
4413 if (is_t4(adapter->params.chip)) in pcie_intr_handler()
4436 { 0x3fffffff, "TP parity error", -1, 1 }, in tp_intr_handler()
4437 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 }, in tp_intr_handler()
4455 "SGE received CPL exceeding IQE size", -1, 1 }, in sge_intr_handler()
4457 "SGE GTS CIDX increment too large", -1, 0 }, in sge_intr_handler()
4458 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 }, in sge_intr_handler()
4459 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full }, in sge_intr_handler()
4461 "SGE IQID > 1023 received CPL for FL", -1, 0 }, in sge_intr_handler()
4462 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1, in sge_intr_handler()
4464 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1, in sge_intr_handler()
4466 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1, in sge_intr_handler()
4468 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1, in sge_intr_handler()
4471 "SGE too many priority ingress contexts", -1, 0 }, in sge_intr_handler()
4472 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 }, in sge_intr_handler()
4473 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 }, in sge_intr_handler()
4478 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped }, in sge_intr_handler()
4479 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full }, in sge_intr_handler()
4481 "SGE too many priority egress contexts", -1, 0 }, in sge_intr_handler()
4488 dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n", in sge_intr_handler()
4495 dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n", in sge_intr_handler()
4499 if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) { in sge_intr_handler()
4505 dev_alert(adapter->pdev_dev, in sge_intr_handler()
4511 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in sge_intr_handler()
4517 dev_err(adapter->pdev_dev, "SGE error for queue %u\n", in sge_intr_handler()
4520 dev_err(adapter->pdev_dev, in sge_intr_handler()
4541 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 }, in cim_intr_handler()
4542 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, in cim_intr_handler()
4543 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, in cim_intr_handler()
4544 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 }, in cim_intr_handler()
4545 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 }, in cim_intr_handler()
4546 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 }, in cim_intr_handler()
4547 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 }, in cim_intr_handler()
4548 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 }, in cim_intr_handler()
4552 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 }, in cim_intr_handler()
4553 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 }, in cim_intr_handler()
4554 { ILLWRINT_F, "CIM illegal write", -1, 1 }, in cim_intr_handler()
4555 { ILLRDINT_F, "CIM illegal read", -1, 1 }, in cim_intr_handler()
4556 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 }, in cim_intr_handler()
4557 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 }, in cim_intr_handler()
4558 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 }, in cim_intr_handler()
4559 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 }, in cim_intr_handler()
4560 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 }, in cim_intr_handler()
4561 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 }, in cim_intr_handler()
4562 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 }, in cim_intr_handler()
4563 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 }, in cim_intr_handler()
4564 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 }, in cim_intr_handler()
4565 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 }, in cim_intr_handler()
4566 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 }, in cim_intr_handler()
4567 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 }, in cim_intr_handler()
4568 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 }, in cim_intr_handler()
4569 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 }, in cim_intr_handler()
4570 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 }, in cim_intr_handler()
4571 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 }, in cim_intr_handler()
4572 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 }, in cim_intr_handler()
4573 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 }, in cim_intr_handler()
4574 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 }, in cim_intr_handler()
4575 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 }, in cim_intr_handler()
4576 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 }, in cim_intr_handler()
4577 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 }, in cim_intr_handler()
4578 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 }, in cim_intr_handler()
4579 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 }, in cim_intr_handler()
4618 { 0x1800000, "ULPRX context error", -1, 1 }, in ulprx_intr_handler()
4619 { 0x7fffff, "ULPRX parity error", -1, 1 }, in ulprx_intr_handler()
4633 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1, in ulptx_intr_handler()
4635 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1, in ulptx_intr_handler()
4637 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1, in ulptx_intr_handler()
4639 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1, in ulptx_intr_handler()
4641 { 0xfffffff, "ULPTX parity error", -1, 1 }, in ulptx_intr_handler()
4655 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 }, in pmtx_intr_handler()
4656 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 }, in pmtx_intr_handler()
4657 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 }, in pmtx_intr_handler()
4658 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 }, in pmtx_intr_handler()
4659 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 }, in pmtx_intr_handler()
4660 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 }, in pmtx_intr_handler()
4662 -1, 1 }, in pmtx_intr_handler()
4663 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 }, in pmtx_intr_handler()
4664 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1}, in pmtx_intr_handler()
4678 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 }, in pmrx_intr_handler()
4679 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 }, in pmrx_intr_handler()
4680 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 }, in pmrx_intr_handler()
4682 -1, 1 }, in pmrx_intr_handler()
4683 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 }, in pmrx_intr_handler()
4684 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1}, in pmrx_intr_handler()
4698 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 }, in cplsw_intr_handler()
4699 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 }, in cplsw_intr_handler()
4700 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 }, in cplsw_intr_handler()
4701 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 }, in cplsw_intr_handler()
4702 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 }, in cplsw_intr_handler()
4703 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 }, in cplsw_intr_handler()
4716 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); in le_intr_handler()
4718 { LIPMISS_F, "LE LIP miss", -1, 0 }, in le_intr_handler()
4719 { LIP0_F, "LE 0 LIP error", -1, 0 }, in le_intr_handler()
4720 { PARITYERR_F, "LE parity error", -1, 1 }, in le_intr_handler()
4721 { UNKNOWNCMD_F, "LE unknown command", -1, 1 }, in le_intr_handler()
4722 { REQQPARERR_F, "LE request queue parity error", -1, 1 }, in le_intr_handler()
4727 { T6_LIPMISS_F, "LE LIP miss", -1, 0 }, in le_intr_handler()
4728 { T6_LIP0_F, "LE 0 LIP error", -1, 0 }, in le_intr_handler()
4729 { CMDTIDERR_F, "LE cmd tid error", -1, 1 }, in le_intr_handler()
4730 { TCAMINTPERR_F, "LE parity error", -1, 1 }, in le_intr_handler()
4731 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 }, in le_intr_handler()
4732 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 }, in le_intr_handler()
4733 { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 }, in le_intr_handler()
4749 { 0xffffff, "MPS Rx parity error", -1, 1 }, in mps_intr_handler()
4753 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, in mps_intr_handler()
4754 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, in mps_intr_handler()
4756 -1, 1 }, in mps_intr_handler()
4758 -1, 1 }, in mps_intr_handler()
4759 { BUBBLE_F, "MPS Tx underflow", -1, 1 }, in mps_intr_handler()
4760 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, in mps_intr_handler()
4761 { FRMERR_F, "MPS Tx framing error", -1, 1 }, in mps_intr_handler()
4765 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 }, in mps_intr_handler()
4766 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 }, in mps_intr_handler()
4768 -1, 1 }, in mps_intr_handler()
4770 -1, 1 }, in mps_intr_handler()
4772 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 }, in mps_intr_handler()
4773 { FRMERR_F, "MPS Tx framing error", -1, 1 }, in mps_intr_handler()
4777 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 }, in mps_intr_handler()
4779 -1, 1 }, in mps_intr_handler()
4780 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 }, in mps_intr_handler()
4784 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, in mps_intr_handler()
4788 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, in mps_intr_handler()
4792 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, in mps_intr_handler()
4796 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 }, in mps_intr_handler()
4797 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 }, in mps_intr_handler()
4798 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 }, in mps_intr_handler()
4807 is_t6(adapter->params.chip) in mps_intr_handler()
4843 if (is_t4(adapter->params.chip)) { in mem_intr_handler()
4857 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n", in mem_intr_handler()
4866 dev_warn(adapter->pdev_dev, in mem_intr_handler()
4871 dev_alert(adapter->pdev_dev, in mem_intr_handler()
4887 dev_alert(adap->pdev_dev, in ma_intr_handler()
4890 if (is_t5(adap->params.chip)) in ma_intr_handler()
4891 dev_alert(adap->pdev_dev, in ma_intr_handler()
4898 dev_alert(adap->pdev_dev, "MA address wrap-around error by " in ma_intr_handler()
4913 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 }, in smb_intr_handler()
4914 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 }, in smb_intr_handler()
4915 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 }, in smb_intr_handler()
4924 * NC-SI interrupt handler.
4929 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 }, in ncsi_intr_handler()
4930 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 }, in ncsi_intr_handler()
4931 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 }, in ncsi_intr_handler()
4932 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 }, in ncsi_intr_handler()
4947 if (is_t4(adap->params.chip)) in xgmac_intr_handler()
4959 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", in xgmac_intr_handler()
4962 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", in xgmac_intr_handler()
4974 { FATALPERR_F, "T4 fatal parity error", -1, 1 }, in pl_intr_handler()
4975 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 }, in pl_intr_handler()
4989 * t4_slow_intr_handler - control path interrupt handler
4992 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5030 if (is_t5(adapter->params.chip) && (cause & MC1_F)) in t4_slow_intr_handler()
5062 * t4_intr_enable - enable interrupts
5065 * Enable PF-specific interrupts for the calling function and the top-level
5071 * non PF-specific interrupts from the various HW modules. Only one PCI
5078 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4_intr_enable()
5081 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) in t4_intr_enable()
5095 * t4_intr_disable - disable interrupts
5098 * Disable interrupts. We only disable the top-level interrupt
5106 if (pci_channel_offline(adapter->pdev)) in t4_intr_disable()
5110 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ? in t4_intr_disable()
5119 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_chip_rss_size()
5126 * t4_config_rss_range - configure a portion of the RSS mapping table
5165 n -= nq; in t4_config_rss_range()
5181 nq -= 3; in t4_config_rss_range()
5192 * t4_config_glbl_rss - configure the global RSS mode
5196 * @flags: mode-specific flags
5217 return -EINVAL; in t4_config_glbl_rss()
5222 * t4_config_vi_rss - configure per VI RSS settings
5229 * Configures VI-specific RSS properties.
5255 * t4_read_rss - read the contents of the RSS mapping table
5259 * Reads the contents of the RSS hash->queue mapping table.
5279 return (adap->flags & CXGB4_FW_OK) && !adap->use_bd; in t4_use_ldst()
5283 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5313 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, in t4_tp_fw_ldst_rw()
5325 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5342 int rc = -EINVAL; in t4_tp_indirect_rw()
5376 * t4_tp_pio_read - Read TP PIO registers
5393 * t4_tp_pio_write - Write TP PIO registers
5410 * t4_tp_tm_pio_read - Read TP TM PIO registers
5427 * t4_tp_mib_read - Read TP MIB registers
5444 * t4_read_rss_key - read the global RSS key
5446 * @key: 10-entry array holding the 320-bit RSS key
5449 * Reads the global 320-bit RSS key.
5457 * t4_write_rss_key - program one of the RSS keys
5459 * @key: 10-entry array holding the 320-bit RSS key
5463 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5473 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble), in t4_write_rss_key()
5474 * allows access to key addresses 16-63 by using KeyWrAddrX in t4_write_rss_key()
5477 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && in t4_write_rss_key()
5495 * t4_read_rss_pf_config - read PF RSS Configuration Table
5511 * t4_read_rss_vf_config - read VF RSS Configuration Table
5526 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) { in t4_read_rss_vf_config()
5548 * t4_read_rss_pf_map - read PF RSS Map
5563 * t4_read_rss_pf_mask - read PF RSS Mask
5578 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5590 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1]; in t4_tp_get_tcp_stats()
5592 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A) in t4_tp_get_tcp_stats()
5599 v4->tcp_out_rsts = STAT(OUT_RST); in t4_tp_get_tcp_stats()
5600 v4->tcp_in_segs = STAT64(IN_SEG); in t4_tp_get_tcp_stats()
5601 v4->tcp_out_segs = STAT64(OUT_SEG); in t4_tp_get_tcp_stats()
5602 v4->tcp_retrans_segs = STAT64(RXT_SEG); in t4_tp_get_tcp_stats()
5607 v6->tcp_out_rsts = STAT(OUT_RST); in t4_tp_get_tcp_stats()
5608 v6->tcp_in_segs = STAT64(IN_SEG); in t4_tp_get_tcp_stats()
5609 v6->tcp_out_segs = STAT64(OUT_SEG); in t4_tp_get_tcp_stats()
5610 v6->tcp_retrans_segs = STAT64(RXT_SEG); in t4_tp_get_tcp_stats()
5618 * t4_tp_get_err_stats - read TP's error MIB counters
5628 int nchan = adap->params.arch.nchan; in t4_tp_get_err_stats()
5630 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A, in t4_tp_get_err_stats()
5632 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A, in t4_tp_get_err_stats()
5634 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A, in t4_tp_get_err_stats()
5636 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, in t4_tp_get_err_stats()
5638 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, in t4_tp_get_err_stats()
5640 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A, in t4_tp_get_err_stats()
5642 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, in t4_tp_get_err_stats()
5644 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, in t4_tp_get_err_stats()
5646 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A, in t4_tp_get_err_stats()
5651 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5661 int nchan = adap->params.arch.nchan; in t4_tp_get_cpl_stats()
5663 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok); in t4_tp_get_cpl_stats()
5665 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok); in t4_tp_get_cpl_stats()
5669 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5679 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A, in t4_tp_get_rdma_stats()
5684 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5697 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx, in t4_get_fcoe_stats()
5700 t4_tp_mib_read(adap, &st->frames_drop, 1, in t4_get_fcoe_stats()
5706 st->octets_ddp = ((u64)val[0] << 32) | val[1]; in t4_get_fcoe_stats()
5710 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5715 * Returns the values of TP's counters for non-TCP directly-placed packets.
5723 st->frames = val[0]; in t4_get_usm_stats()
5724 st->drops = val[1]; in t4_get_usm_stats()
5725 st->octets = ((u64)val[2] << 32) | val[3]; in t4_get_usm_stats()
5729 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5732 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5752 * t4_read_cong_tbl - reads the congestion control table
5773 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5790 * init_cong_ctrl - initialize congestion control parameters
5837 * t4_load_mtus - write the MTU and congestion control HW tables
5843 * Write the HW MTU table with the supplied MTUs and the high-speed
5864 log2--; in t4_load_mtus()
5871 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], in t4_load_mtus()
5880 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5891 u64 v = bytes256 * adap->params.vpd.cclk; in chan_rate()
5897 * t4_get_chan_txrate - get the current per channel Tx rates
5912 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5920 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5927 * t4_set_trace_filter - configure one of the tracing filters
5954 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) in t4_set_trace_filter()
5955 return -EINVAL; in t4_set_trace_filter()
5961 if (tp->snap_len > 9600 || idx) in t4_set_trace_filter()
5962 return -EINVAL; in t4_set_trace_filter()
5965 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 || in t4_set_trace_filter()
5966 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M || in t4_set_trace_filter()
5967 tp->min_len > TFMINPKTSIZE_M) in t4_set_trace_filter()
5968 return -EINVAL; in t4_set_trace_filter()
5973 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A); in t4_set_trace_filter()
5978 t4_write_reg(adap, data_reg, tp->data[i]); in t4_set_trace_filter()
5979 t4_write_reg(adap, mask_reg, ~tp->mask[i]); in t4_set_trace_filter()
5982 TFCAPTUREMAX_V(tp->snap_len) | in t4_set_trace_filter()
5983 TFMINPKTSIZE_V(tp->min_len)); in t4_set_trace_filter()
5985 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) | in t4_set_trace_filter()
5986 (is_t4(adap->params.chip) ? in t4_set_trace_filter()
5987 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) : in t4_set_trace_filter()
5988 T5_TFPORT_V(tp->port) | T5_TFEN_F | in t4_set_trace_filter()
5989 T5_TFINVERTMATCH_V(tp->invert))); in t4_set_trace_filter()
5995 * t4_get_trace_filter - query one of the tracing filters
5999 * @enabled: non-zero if the filter is enabled
6013 if (is_t4(adap->params.chip)) { in t4_get_trace_filter()
6015 tp->port = TFPORT_G(ctla); in t4_get_trace_filter()
6016 tp->invert = !!(ctla & TFINVERTMATCH_F); in t4_get_trace_filter()
6019 tp->port = T5_TFPORT_G(ctla); in t4_get_trace_filter()
6020 tp->invert = !!(ctla & T5_TFINVERTMATCH_F); in t4_get_trace_filter()
6022 tp->snap_len = TFCAPTUREMAX_G(ctlb); in t4_get_trace_filter()
6023 tp->min_len = TFMINPKTSIZE_G(ctlb); in t4_get_trace_filter()
6024 tp->skip_ofst = TFOFFSET_G(ctla); in t4_get_trace_filter()
6025 tp->skip_len = TFLENGTH_G(ctla); in t4_get_trace_filter()
6027 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx; in t4_get_trace_filter()
6032 tp->mask[i] = ~t4_read_reg(adap, mask_reg); in t4_get_trace_filter()
6033 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; in t4_get_trace_filter()
6038 * t4_pmtx_get_stats - returns the HW stats from PMTX
6050 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { in t4_pmtx_get_stats()
6053 if (is_t4(adap->params.chip)) { in t4_pmtx_get_stats()
6065 * t4_pmrx_get_stats - returns the HW stats from PMRX
6077 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { in t4_pmrx_get_stats()
6080 if (is_t4(adap->params.chip)) { in t4_pmrx_get_stats()
6092 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6105 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in compute_mps_bg_map()
6125 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n", in compute_mps_bg_map()
6132 * t4_get_mps_bg_map - return the buffer groups associated with a port
6154 mps_bg_map = adapter->params.mps_bg_map; in t4_get_mps_bg_map()
6168 if (adapter->flags & CXGB4_FW_OK) { in t4_get_mps_bg_map()
6174 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf, in t4_get_mps_bg_map()
6198 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6220 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf, in t4_get_tp_e2c_map()
6229 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6239 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_tp_ch_map()
6243 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n", in t4_get_tp_ch_map()
6270 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n", in t4_get_tp_ch_map()
6276 * t4_get_port_type_description - return Port Type string description
6289 "KX", in t4_get_port_type_description()
6313 * t4_get_port_stats_offset - collect port stats relative to a previous
6331 *s -= *o; in t4_get_port_stats_offset()
6335 * t4_get_port_stats - collect port statistics
6349 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ in t4_get_port_stats()
6353 p->tx_octets = GET_STAT(TX_PORT_BYTES); in t4_get_port_stats()
6354 p->tx_frames = GET_STAT(TX_PORT_FRAMES); in t4_get_port_stats()
6355 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); in t4_get_port_stats()
6356 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); in t4_get_port_stats()
6357 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); in t4_get_port_stats()
6358 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); in t4_get_port_stats()
6359 p->tx_frames_64 = GET_STAT(TX_PORT_64B); in t4_get_port_stats()
6360 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); in t4_get_port_stats()
6361 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); in t4_get_port_stats()
6362 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); in t4_get_port_stats()
6363 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); in t4_get_port_stats()
6364 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); in t4_get_port_stats()
6365 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); in t4_get_port_stats()
6366 p->tx_drop = GET_STAT(TX_PORT_DROP); in t4_get_port_stats()
6367 p->tx_pause = GET_STAT(TX_PORT_PAUSE); in t4_get_port_stats()
6368 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); in t4_get_port_stats()
6369 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); in t4_get_port_stats()
6370 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); in t4_get_port_stats()
6371 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); in t4_get_port_stats()
6372 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); in t4_get_port_stats()
6373 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); in t4_get_port_stats()
6374 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); in t4_get_port_stats()
6375 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); in t4_get_port_stats()
6377 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) { in t4_get_port_stats()
6379 p->tx_frames_64 -= p->tx_pause; in t4_get_port_stats()
6381 p->tx_mcast_frames -= p->tx_pause; in t4_get_port_stats()
6383 p->rx_octets = GET_STAT(RX_PORT_BYTES); in t4_get_port_stats()
6384 p->rx_frames = GET_STAT(RX_PORT_FRAMES); in t4_get_port_stats()
6385 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); in t4_get_port_stats()
6386 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); in t4_get_port_stats()
6387 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); in t4_get_port_stats()
6388 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); in t4_get_port_stats()
6389 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); in t4_get_port_stats()
6390 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); in t4_get_port_stats()
6391 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); in t4_get_port_stats()
6392 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); in t4_get_port_stats()
6393 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); in t4_get_port_stats()
6394 p->rx_frames_64 = GET_STAT(RX_PORT_64B); in t4_get_port_stats()
6395 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); in t4_get_port_stats()
6396 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); in t4_get_port_stats()
6397 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); in t4_get_port_stats()
6398 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); in t4_get_port_stats()
6399 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); in t4_get_port_stats()
6400 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); in t4_get_port_stats()
6401 p->rx_pause = GET_STAT(RX_PORT_PAUSE); in t4_get_port_stats()
6402 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); in t4_get_port_stats()
6403 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); in t4_get_port_stats()
6404 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); in t4_get_port_stats()
6405 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); in t4_get_port_stats()
6406 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); in t4_get_port_stats()
6407 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); in t4_get_port_stats()
6408 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); in t4_get_port_stats()
6409 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); in t4_get_port_stats()
6411 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) { in t4_get_port_stats()
6413 p->rx_frames_64 -= p->rx_pause; in t4_get_port_stats()
6415 p->rx_mcast_frames -= p->rx_pause; in t4_get_port_stats()
6418 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6419 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6420 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6421 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6422 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6423 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6424 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6425 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6432 * t4_get_lb_stats - collect loopback port statistics
6445 (is_t4(adap->params.chip) ? \ in t4_get_lb_stats()
6450 p->octets = GET_STAT(BYTES); in t4_get_lb_stats()
6451 p->frames = GET_STAT(FRAMES); in t4_get_lb_stats()
6452 p->bcast_frames = GET_STAT(BCAST); in t4_get_lb_stats()
6453 p->mcast_frames = GET_STAT(MCAST); in t4_get_lb_stats()
6454 p->ucast_frames = GET_STAT(UCAST); in t4_get_lb_stats()
6455 p->error_frames = GET_STAT(ERROR); in t4_get_lb_stats()
6457 p->frames_64 = GET_STAT(64B); in t4_get_lb_stats()
6458 p->frames_65_127 = GET_STAT(65B_127B); in t4_get_lb_stats()
6459 p->frames_128_255 = GET_STAT(128B_255B); in t4_get_lb_stats()
6460 p->frames_256_511 = GET_STAT(256B_511B); in t4_get_lb_stats()
6461 p->frames_512_1023 = GET_STAT(512B_1023B); in t4_get_lb_stats()
6462 p->frames_1024_1518 = GET_STAT(1024B_1518B); in t4_get_lb_stats()
6463 p->frames_1519_max = GET_STAT(1519B_MAX); in t4_get_lb_stats()
6464 p->drop = GET_STAT(DROP_FRAMES); in t4_get_lb_stats()
6466 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6467 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6468 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6469 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6470 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6471 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6472 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6473 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6479 /* t4_mk_filtdelwr - create a delete filter WR
6490 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR)); in t4_mk_filtdelwr()
6491 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16)); in t4_mk_filtdelwr()
6492 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) | in t4_mk_filtdelwr()
6494 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F); in t4_mk_filtdelwr()
6496 wr->rx_chan_rx_rpl_iq = in t4_mk_filtdelwr()
6527 * t4_mdio_rd - read a PHY register through MDIO
6561 * t4_mdio_wr - write a PHY register through MDIO
6592 * t4_sge_decode_idma_state - decode the idma state
6711 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in t4_sge_decode_idma_state()
6733 dev_err(adapter->pdev_dev, in t4_sge_decode_idma_state()
6738 if (is_t4(adapter->params.chip)) { in t4_sge_decode_idma_state()
6757 * t4_sge_ctxt_flush - flush the SGE context cache
6786 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6806 nparams = ndbqtimers - dbqtimerix; in t4_read_sge_dbqtimers()
6815 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, in t4_read_sge_dbqtimers()
6827 * t4_fw_hello - establish communication with FW
6832 * @state: returns the current device state (if non-NULL)
6867 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) in t4_fw_hello()
6889 * Note that we also do this wait if we're a non-Master-capable PF and in t4_fw_hello()
6911 waiting -= 50; in t4_fw_hello()
6922 if (retries-- > 0) in t4_fw_hello()
6925 return -ETIMEDOUT; in t4_fw_hello()
6957 * t4_fw_bye - end communication with FW
6973 * t4_early_init - ask FW to initialize the device
6990 * t4_fw_reset - issue a reset to FW
7008 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7068 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7126 return -ETIMEDOUT; in t4_fw_restart()
7132 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7159 return -EINVAL; in t4_fw_upgrade()
7164 adap->flags &= ~CXGB4_FW_OK; in t4_fw_upgrade()
7179 * portion of the FLASH . The user will need to re-FLASH a new in t4_fw_upgrade()
7193 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); in t4_fw_upgrade()
7203 adap->flags |= CXGB4_FW_OK; in t4_fw_upgrade()
7208 * t4_fl_pkt_align - return the fl packet alignment
7235 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_fl_pkt_align()
7243 if (!is_t4(adap->params.chip)) { in t4_fl_pkt_align()
7261 * t4_fixup_host_params - fix up host-dependent parameters
7263 * @page_size: the host's Base Page Size
7267 * host's Base Page and Cache Line Sizes. This function will fix all of
7273 unsigned int page_shift = fls(page_size) - 1; in t4_fixup_host_params()
7274 unsigned int sge_hps = page_shift - 10; in t4_fixup_host_params()
7277 unsigned int fl_align_log = fls(fl_align) - 1; in t4_fixup_host_params()
7289 if (is_t4(adap->params.chip)) { in t4_fixup_host_params()
7293 INGPADBOUNDARY_V(fl_align_log - in t4_fixup_host_params()
7311 * Line Size, that'll involve a Read-Modify-Write cycle on the in t4_fixup_host_params()
7318 * Boundary to incorporate the PCI-E Maximum Payload Size. We in t4_fixup_host_params()
7323 if (pci_is_pcie(adap->pdev)) { in t4_fixup_host_params()
7331 pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, in t4_fixup_host_params()
7351 unsigned int pack_align_log = fls(pack_align) - 1; in t4_fixup_host_params()
7353 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X; in t4_fixup_host_params()
7362 if (is_t5(adap->params.chip)) in t4_fixup_host_params()
7390 * For the single-MTU buffers in unpacked mode we need to include in t4_fixup_host_params()
7399 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) in t4_fixup_host_params()
7400 & ~(fl_align-1)); in t4_fixup_host_params()
7402 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) in t4_fixup_host_params()
7403 & ~(fl_align-1)); in t4_fixup_host_params()
7405 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); in t4_fixup_host_params()
7411 * t4_fw_initialize - ask FW to initialize the device
7428 * t4_query_params_rw - query FW or device parameters
7451 return -EINVAL; in t4_query_params_rw()
7491 * t4_set_params_timeout - sets FW or device parameters
7513 return -EINVAL; in t4_set_params_timeout()
7522 while (nparams--) { in t4_set_params_timeout()
7531 * t4_set_params - sets FW or device parameters
7552 * t4_cfg_pfvf - configure PF/VF resource limits
7559 * @rxqi: the max number of interrupt-capable ingress queues
7600 * t4_alloc_vi - allocate a virtual interface
7616 * Returns a negative error number or the non-negative VI id.
7631 c.nmac = nmac - 1; in t4_alloc_vi()
7666 * t4_free_vi - free a virtual interface
7693 * t4_set_rxmode - set Rx properties of a virtual interface
7698 * @mtu: the new MTU or -1
7699 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7700 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7701 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7702 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7758 * t4_free_encap_mac_filt - frees MPS entry at given index
7786 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | in t4_free_encap_mac_filt()
7788 eth_zero_addr(p->macaddr); in t4_free_encap_mac_filt()
7789 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_encap_mac_filt()
7794 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7826 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) | in t4_free_raw_mac_filt()
7830 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) | in t4_free_raw_mac_filt()
7833 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) | in t4_free_raw_mac_filt()
7837 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN); in t4_free_raw_mac_filt()
7838 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN); in t4_free_raw_mac_filt()
7840 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_raw_mac_filt()
7844 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7876 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | in t4_alloc_encap_mac_filt()
7878 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_alloc_encap_mac_filt()
7879 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); in t4_alloc_encap_mac_filt()
7881 p->lookup_type_to_vni = in t4_alloc_encap_mac_filt()
7885 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask)); in t4_alloc_encap_mac_filt()
7886 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_encap_mac_filt()
7888 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); in t4_alloc_encap_mac_filt()
7893 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7925 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx)); in t4_alloc_raw_mac_filt()
7928 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) | in t4_alloc_raw_mac_filt()
7931 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) | in t4_alloc_raw_mac_filt()
7935 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN); in t4_alloc_raw_mac_filt()
7936 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN); in t4_alloc_raw_mac_filt()
7938 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_raw_mac_filt()
7940 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd)); in t4_alloc_raw_mac_filt()
7942 ret = -ENOMEM; in t4_alloc_raw_mac_filt()
7949 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7960 * Allocates an exact-match filter for each of the supplied addresses and
7977 unsigned int max_naddr = adap->params.arch.mps_tcam_size; in t4_alloc_mac_filt()
7981 return -EINVAL; in t4_alloc_mac_filt()
8002 p->valid_to_idx = in t4_alloc_mac_filt()
8006 memcpy(p->macaddr, addr[offset + i], in t4_alloc_mac_filt()
8007 sizeof(p->macaddr)); in t4_alloc_mac_filt()
8015 if (ret && ret != -FW_ENOMEM) in t4_alloc_mac_filt()
8020 be16_to_cpu(p->valid_to_idx)); in t4_alloc_mac_filt()
8034 rem -= fw_naddr; in t4_alloc_mac_filt()
8037 if (ret == 0 || ret == -FW_ENOMEM) in t4_alloc_mac_filt()
8043 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8051 * Frees the exact-match filter for each of the supplied addresses
8062 unsigned int max_naddr = is_t4(adap->params.chip) ? in t4_free_mac_filt()
8068 return -EINVAL; in t4_free_mac_filt()
8090 p->valid_to_idx = cpu_to_be16( in t4_free_mac_filt()
8093 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); in t4_free_mac_filt()
8102 be16_to_cpu(p->valid_to_idx)); in t4_free_mac_filt()
8109 rem -= fw_naddr; in t4_free_mac_filt()
8118 * t4_change_mac - modifies the exact-match filter for a MAC address
8122 * @idx: index of existing filter for old value of MAC address, or -1
8127 * Modifies an exact-match filter and sets it to the new MAC address.
8131 * new address value. @idx can be -1 if the address is a new addition.
8142 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size; in t4_change_mac()
8153 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F | in t4_change_mac()
8156 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_change_mac()
8160 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx)); in t4_change_mac()
8162 ret = -ENOMEM; in t4_change_mac()
8164 if (adap->params.viid_smt_extn_support) { in t4_change_mac()
8173 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= in t4_change_mac()
8185 * t4_set_addr_hash - program the MAC inexact-match hash filter
8193 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8212 * t4_enable_vi_params - enable/disable a virtual interface
8240 * t4_enable_vi - enable/disable a virtual interface
8256 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8267 * we notify the OS-specific code of a potential Link Status change
8274 int ret = t4_enable_vi_params(adap, mbox, pi->viid, in t4_enable_pi_params()
8278 t4_os_link_changed(adap, pi->port_id, in t4_enable_pi_params()
8279 rx_en && tx_en && pi->link_cfg.link_ok); in t4_enable_pi_params()
8284 * t4_identify_port - identify a VI's port by blinking its LED
8307 * t4_iq_stop - stop an ingress queue and its FLs
8340 * t4_iq_free - free an ingress queue and its FLs
8371 * t4_eth_eq_free - free an Ethernet egress queue
8396 * t4_ctrl_eq_free - free a control egress queue
8421 * t4_ofld_eq_free - free an offload egress queue
8446 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8456 "Auto-negotiation Failure", in t4_link_down_rc_str()
8486 TEST_SPEED_RETURN(1G, 1000); in fwcap_to_speed()
8495 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8526 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8530 * 32-bit Port Capabilities value.
8537 * 16-bit Port Information message isn't the same as the in lstatus_to_fwcap()
8538 * 16-bit Port Capabilities bitfield used everywhere else ... in lstatus_to_fwcap()
8561 * t4_handle_get_port_info - process a FW reply message
8571 struct link_config *lc = &pi->link_cfg; in t4_handle_get_port_info()
8572 struct adapter *adapter = pi->adapter; in t4_handle_get_port_info()
8580 action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16)); in t4_handle_get_port_info()
8583 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype); in t4_handle_get_port_info()
8589 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap)); in t4_handle_get_port_info()
8590 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap)); in t4_handle_get_port_info()
8591 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap)); in t4_handle_get_port_info()
8599 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32); in t4_handle_get_port_info()
8604 pcaps = be32_to_cpu(cmd->u.info32.pcaps32); in t4_handle_get_port_info()
8605 acaps = be32_to_cpu(cmd->u.info32.acaps32); in t4_handle_get_port_info()
8606 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32); in t4_handle_get_port_info()
8607 linkattr = be32_to_cpu(cmd->u.info32.linkattr32); in t4_handle_get_port_info()
8612 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n", in t4_handle_get_port_info()
8613 be32_to_cpu(cmd->action_to_len16)); in t4_handle_get_port_info()
8623 * whether the OS-dependent layer wants us to redo the current in t4_handle_get_port_info()
8626 lc->new_module = false; in t4_handle_get_port_info()
8627 lc->redo_l1cfg = false; in t4_handle_get_port_info()
8629 if (mod_type != pi->mod_type) { in t4_handle_get_port_info()
8633 * Speeds, Auto-Negotiation, Forward Error Correction, etc. in t4_handle_get_port_info()
8638 lc->pcaps = pcaps; in t4_handle_get_port_info()
8646 * the user explicitly requests these standards-based values. in t4_handle_get_port_info()
8648 lc->def_acaps = acaps; in t4_handle_get_port_info()
8660 pi->port_type = port_type; in t4_handle_get_port_info()
8664 pi->mod_type = mod_type; in t4_handle_get_port_info()
8666 /* Let the OS-dependent layer know if we have a new in t4_handle_get_port_info()
8669 lc->new_module = t4_is_inserted_mod_type(mod_type); in t4_handle_get_port_info()
8671 t4_os_portmod_changed(adapter, pi->port_id); in t4_handle_get_port_info()
8674 if (link_ok != lc->link_ok || speed != lc->speed || in t4_handle_get_port_info()
8675 fc != lc->fc || adv_fc != lc->advertised_fc || in t4_handle_get_port_info()
8676 fec != lc->fec) { in t4_handle_get_port_info()
8678 if (!link_ok && lc->link_ok) { in t4_handle_get_port_info()
8679 lc->link_down_rc = linkdnrc; in t4_handle_get_port_info()
8680 dev_warn_ratelimited(adapter->pdev_dev, in t4_handle_get_port_info()
8682 pi->tx_chan, in t4_handle_get_port_info()
8685 lc->link_ok = link_ok; in t4_handle_get_port_info()
8686 lc->speed = speed; in t4_handle_get_port_info()
8687 lc->advertised_fc = adv_fc; in t4_handle_get_port_info()
8688 lc->fc = fc; in t4_handle_get_port_info()
8689 lc->fec = fec; in t4_handle_get_port_info()
8691 lc->lpacaps = lpacaps; in t4_handle_get_port_info()
8692 lc->acaps = acaps & ADVERT_MASK; in t4_handle_get_port_info()
8694 /* If we're not physically capable of Auto-Negotiation, note in t4_handle_get_port_info()
8695 * this as Auto-Negotiation disabled. Otherwise, we track in t4_handle_get_port_info()
8696 * what Auto-Negotiation settings we have. Note parallel in t4_handle_get_port_info()
8699 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) { in t4_handle_get_port_info()
8700 lc->autoneg = AUTONEG_DISABLE; in t4_handle_get_port_info()
8701 } else if (lc->acaps & FW_PORT_CAP32_ANEG) { in t4_handle_get_port_info()
8702 lc->autoneg = AUTONEG_ENABLE; in t4_handle_get_port_info()
8708 lc->acaps = 0; in t4_handle_get_port_info()
8709 lc->speed_caps = fwcap_to_fwspeed(acaps); in t4_handle_get_port_info()
8710 lc->autoneg = AUTONEG_DISABLE; in t4_handle_get_port_info()
8713 t4_os_link_changed(adapter, pi->port_id, link_ok); in t4_handle_get_port_info()
8716 /* If we have a new Transceiver Module and the OS-dependent code has in t4_handle_get_port_info()
8720 if (lc->new_module && lc->redo_l1cfg) { in t4_handle_get_port_info()
8730 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc); in t4_handle_get_port_info()
8733 dev_warn(adapter->pdev_dev, in t4_handle_get_port_info()
8737 lc->new_module = false; in t4_handle_get_port_info()
8738 lc->redo_l1cfg = false; in t4_handle_get_port_info()
8742 * t4_update_port_info - retrieve and update port information if changed
8751 unsigned int fw_caps = pi->adapter->params.fw_caps_support; in t4_update_port_info()
8758 FW_PORT_CMD_PORTID_V(pi->tx_chan)); in t4_update_port_info()
8764 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox, in t4_update_port_info()
8774 * t4_get_link_params - retrieve basic link parameters for given port
8787 unsigned int fw_caps = pi->adapter->params.fw_caps_support; in t4_get_link_params()
8796 FW_PORT_CMD_PORTID_V(pi->tx_chan)); in t4_get_link_params()
8803 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox, in t4_get_link_params()
8835 * t4_handle_fw_rpl - process a FW reply message
8846 * conditionals ... We can get away with pre-dereferencing in t4_handle_fw_rpl()
8852 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16)); in t4_handle_fw_rpl()
8858 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid)); in t4_handle_fw_rpl()
8863 if (pi->tx_chan == chan) in t4_handle_fw_rpl()
8869 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", in t4_handle_fw_rpl()
8871 return -EINVAL; in t4_handle_fw_rpl()
8880 if (pci_is_pcie(adapter->pdev)) { in get_pci_mode()
8881 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val); in get_pci_mode()
8882 p->speed = val & PCI_EXP_LNKSTA_CLS; in get_pci_mode()
8883 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; in get_pci_mode()
8888 * init_link_config - initialize a link's SW state
8894 * capabilities and default speed/flow-control/autonegotiation settings.
8899 lc->pcaps = pcaps; in init_link_config()
8900 lc->def_acaps = acaps; in init_link_config()
8901 lc->lpacaps = 0; in init_link_config()
8902 lc->speed_caps = 0; in init_link_config()
8903 lc->speed = 0; in init_link_config()
8904 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; in init_link_config()
8909 lc->requested_fec = FEC_AUTO; in init_link_config()
8910 lc->fec = fwcap_to_cc_fec(lc->def_acaps); in init_link_config()
8912 /* If the Port is capable of Auto-Negtotiation, initialize it as in init_link_config()
8915 * Auto-Negotiate disabled and select the highest supported speed in init_link_config()
8919 if (lc->pcaps & FW_PORT_CAP32_ANEG) { in init_link_config()
8920 lc->acaps = lc->pcaps & ADVERT_MASK; in init_link_config()
8921 lc->autoneg = AUTONEG_ENABLE; in init_link_config()
8922 lc->requested_fc |= PAUSE_AUTONEG; in init_link_config()
8924 lc->acaps = 0; in init_link_config()
8925 lc->autoneg = AUTONEG_DISABLE; in init_link_config()
8926 lc->speed_caps = fwcap_to_fwspeed(acaps); in init_link_config()
8942 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO); in t4_wait_dev_ready()
8952 /* Table for non-Numonix supported flash parts. Numonix parts are left in t4_get_flash_params()
8977 /* Check to see if it's one of our non-standard supported Flash parts. in t4_get_flash_params()
8981 adap->params.sf_size = supported_flash[part].size_mb; in t4_get_flash_params()
8982 adap->params.sf_nsec = in t4_get_flash_params()
8983 adap->params.sf_size / SF_SEC_SIZE; in t4_get_flash_params()
8998 /* This Density -> Size decoding table is taken from Micron in t4_get_flash_params()
9033 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */ in t4_get_flash_params()
9034 /* This Density -> Size decoding table is taken from ISSI in t4_get_flash_params()
9049 /* This Density -> Size decoding table is taken from Macronix in t4_get_flash_params()
9064 /* This Density -> Size decoding table is taken from Winbond in t4_get_flash_params()
9087 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n", in t4_get_flash_params()
9093 adap->params.sf_size = size; in t4_get_flash_params()
9094 adap->params.sf_nsec = size / SF_SEC_SIZE; in t4_get_flash_params()
9097 if (adap->params.sf_size < FLASH_MIN_SIZE) in t4_get_flash_params()
9098 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n", in t4_get_flash_params()
9099 flashid, adap->params.sf_size, FLASH_MIN_SIZE); in t4_get_flash_params()
9104 * t4_prep_adapter - prepare SW and HW for operation
9117 get_pci_mode(adapter, &adapter->params.pci); in t4_prep_adapter()
9122 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret); in t4_prep_adapter()
9128 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id); in t4_prep_adapter()
9130 adapter->params.chip = 0; in t4_prep_adapter()
9133 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); in t4_prep_adapter()
9134 adapter->params.arch.sge_fl_db = DBPRIO_F; in t4_prep_adapter()
9135 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
9137 adapter->params.arch.mps_rplc_size = 128; in t4_prep_adapter()
9138 adapter->params.arch.nchan = NCHAN; in t4_prep_adapter()
9139 adapter->params.arch.pm_stats_cnt = PM_NSTATS; in t4_prep_adapter()
9140 adapter->params.arch.vfcount = 128; in t4_prep_adapter()
9144 adapter->params.arch.cng_ch_bits_log = 2; in t4_prep_adapter()
9147 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); in t4_prep_adapter()
9148 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F; in t4_prep_adapter()
9149 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
9151 adapter->params.arch.mps_rplc_size = 128; in t4_prep_adapter()
9152 adapter->params.arch.nchan = NCHAN; in t4_prep_adapter()
9153 adapter->params.arch.pm_stats_cnt = PM_NSTATS; in t4_prep_adapter()
9154 adapter->params.arch.vfcount = 128; in t4_prep_adapter()
9155 adapter->params.arch.cng_ch_bits_log = 2; in t4_prep_adapter()
9158 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); in t4_prep_adapter()
9159 adapter->params.arch.sge_fl_db = 0; in t4_prep_adapter()
9160 adapter->params.arch.mps_tcam_size = in t4_prep_adapter()
9162 adapter->params.arch.mps_rplc_size = 256; in t4_prep_adapter()
9163 adapter->params.arch.nchan = 2; in t4_prep_adapter()
9164 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS; in t4_prep_adapter()
9165 adapter->params.arch.vfcount = 256; in t4_prep_adapter()
9169 adapter->params.arch.cng_ch_bits_log = 3; in t4_prep_adapter()
9172 dev_err(adapter->pdev_dev, "Device %d is not supported\n", in t4_prep_adapter()
9174 return -EINVAL; in t4_prep_adapter()
9177 adapter->params.cim_la_size = CIMLA_SIZE; in t4_prep_adapter()
9178 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t4_prep_adapter()
9183 adapter->params.nports = 1; in t4_prep_adapter()
9184 adapter->params.portvec = 1; in t4_prep_adapter()
9185 adapter->params.vpd.cclk = 50000; in t4_prep_adapter()
9188 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2, in t4_prep_adapter()
9194 * t4_shutdown_adapter - shut down adapter, host & wire
9202 * the port Link Status to go down -- if register writes work --
9212 u32 a_port_cfg = is_t4(adapter->params.chip) ? in t4_shutdown_adapter()
9226 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9263 if (!user && is_t4(adapter->params.chip)) in t4_bar2_sge_qregs()
9264 return -EINVAL; in t4_bar2_sge_qregs()
9268 page_shift = adapter->params.sge.hps + 10; in t4_bar2_sge_qregs()
9274 ? adapter->params.sge.eq_qpp in t4_bar2_sge_qregs()
9275 : adapter->params.sge.iq_qpp); in t4_bar2_sge_qregs()
9276 qpp_mask = (1 << qpp_shift) - 1; in t4_bar2_sge_qregs()
9298 * from the writes to the registers -- the Write Combined Doorbell in t4_bar2_sge_qregs()
9316 * t4_init_devlog_params - initialize adapter->params.devlog
9324 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_params()
9339 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams); in t4_init_devlog_params()
9340 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4; in t4_init_devlog_params()
9344 dparams->size = nentries * sizeof(struct fw_devlog_e); in t4_init_devlog_params()
9355 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), in t4_init_devlog_params()
9362 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo); in t4_init_devlog_params()
9363 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4; in t4_init_devlog_params()
9364 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); in t4_init_devlog_params()
9370 * t4_init_sge_params - initialize adap->params.sge
9377 struct sge_params *sge_params = &adapter->params.sge; in t4_init_sge_params()
9385 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf); in t4_init_sge_params()
9386 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M); in t4_init_sge_params()
9391 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf); in t4_init_sge_params()
9393 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); in t4_init_sge_params()
9395 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M); in t4_init_sge_params()
9401 * t4_init_tp_params - initialize adap->params.tp
9414 adap->params.tp.tre = TIMERRESOLUTION_G(v); in t4_init_tp_params()
9415 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); in t4_init_tp_params()
9417 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ in t4_init_tp_params()
9419 adap->params.tp.tx_modq[chan] = chan; in t4_init_tp_params()
9429 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, in t4_init_tp_params()
9432 dev_info(adap->pdev_dev, in t4_init_tp_params()
9436 adap->params.tp.vlan_pri_map = in t4_init_tp_params()
9438 adap->params.tp.filter_mask = in t4_init_tp_params()
9441 dev_info(adap->pdev_dev, in t4_init_tp_params()
9442 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n"); in t4_init_tp_params()
9444 /* Incase of older-fw (which doesn't expose the api in t4_init_tp_params()
9445 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses in t4_init_tp_params()
9446 * the fw api) combination, fall-back to older method of reading in t4_init_tp_params()
9447 * the filter mode from indirect-register in t4_init_tp_params()
9449 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
9452 /* With the older-fw and newer-driver combination we might run in t4_init_tp_params()
9459 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map; in t4_init_tp_params()
9462 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
9468 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { in t4_init_tp_params()
9470 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0; in t4_init_tp_params()
9477 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F); in t4_init_tp_params()
9478 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); in t4_init_tp_params()
9479 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); in t4_init_tp_params()
9480 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); in t4_init_tp_params()
9481 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F); in t4_init_tp_params()
9482 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9484 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9486 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9488 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9490 adap->params.tp.frag_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
9496 if ((adap->params.tp.ingress_config & VNIC_F) == 0) in t4_init_tp_params()
9497 adap->params.tp.vnic_shift = -1; in t4_init_tp_params()
9500 adap->params.tp.hash_filter_mask = v; in t4_init_tp_params()
9502 adap->params.tp.hash_filter_mask |= ((u64)v << 32); in t4_init_tp_params()
9507 * t4_filter_field_shift - calculate filter field shift
9517 unsigned int filter_mode = adap->params.tp.vlan_pri_map; in t4_filter_field_shift()
9522 return -1; in t4_filter_field_shift()
9574 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid)); in t4_init_rss_mode()
9579 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen); in t4_init_rss_mode()
9585 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9601 struct adapter *adapter = pi->adapter; in t4_init_portinfo()
9602 unsigned int fw_caps = adapter->params.fw_caps_support; in t4_init_portinfo()
9612 * which knows the new 32-bit Port Capabilities, it's time to find in t4_init_portinfo()
9614 * Updates using the new 32-bit Port Capabilities version of the in t4_init_portinfo()
9625 adapter->params.fw_caps_support = fw_caps; in t4_init_portinfo()
9637 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd); in t4_init_portinfo()
9649 : -1); in t4_init_portinfo()
9658 : -1); in t4_init_portinfo()
9663 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size, in t4_init_portinfo()
9668 pi->viid = ret; in t4_init_portinfo()
9669 pi->tx_chan = port; in t4_init_portinfo()
9670 pi->lport = port; in t4_init_portinfo()
9671 pi->rss_size = rss_size; in t4_init_portinfo()
9672 pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port); in t4_init_portinfo()
9677 if (adapter->params.viid_smt_extn_support) { in t4_init_portinfo()
9678 pi->vivld = vivld; in t4_init_portinfo()
9679 pi->vin = vin; in t4_init_portinfo()
9682 pi->vivld = FW_VIID_VIVLD_G(pi->viid); in t4_init_portinfo()
9683 pi->vin = FW_VIID_VIN_G(pi->viid); in t4_init_portinfo()
9686 pi->port_type = port_type; in t4_init_portinfo()
9687 pi->mdio_addr = mdio_addr; in t4_init_portinfo()
9688 pi->mod_type = FW_PORT_MOD_TYPE_NA; in t4_init_portinfo()
9690 init_link_config(&pi->link_cfg, pcaps, acaps); in t4_init_portinfo()
9702 while ((adap->params.portvec & (1 << j)) == 0) in t4_port_init()
9709 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); in t4_port_init()
9720 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL, in t4_init_port_mirror()
9732 * t4_read_cimq_cfg - read CIM queue configuration
9734 * @base: holds the queue base addresses in bytes
9741 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) in t4_read_cimq_cfg() argument
9744 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cimq_cfg()
9751 /* value is in 256-byte units */ in t4_read_cimq_cfg()
9752 *base++ = CIMQBASE_G(v) * 256; in t4_read_cimq_cfg()
9754 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */ in t4_read_cimq_cfg()
9760 /* value is in 256-byte units */ in t4_read_cimq_cfg()
9761 *base++ = CIMQBASE_G(v) * 256; in t4_read_cimq_cfg()
9767 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9771 * @n: capacity of @data in 32-bit words
9775 * error and the number of 32-bit words actually read on success.
9784 return -EINVAL; in t4_read_cim_ibq()
9790 /* It might take 3-10ms before the IBQ debug read access is allowed. in t4_read_cim_ibq()
9809 * t4_read_cim_obq - read the contents of a CIM outbound queue
9813 * @n: capacity of @data in 32-bit words
9817 * error and the number of 32-bit words actually read on success.
9823 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cim_obq()
9826 if ((qid > (cim_num_obq - 1)) || (n & 3)) in t4_read_cim_obq()
9827 return -EINVAL; in t4_read_cim_obq()
9833 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */ in t4_read_cim_obq()
9852 * t4_cim_read - read a block from CIM internal address space
9858 * Reads a block of 4-byte words from the CIM intenal address space.
9866 return -EBUSY; in t4_cim_read()
9868 for ( ; !ret && n--; addr += 4) { in t4_cim_read()
9879 * t4_cim_write - write a block into CIM internal address space
9885 * Writes a block of 4-byte words into the CIM intenal address space.
9893 return -EBUSY; in t4_cim_write()
9895 for ( ; !ret && n--; addr += 4) { in t4_cim_write()
9911 * t4_cim_read_la - read CIM LA capture buffer
9943 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
9952 ret = -ETIMEDOUT; in t4_cim_read_la()
9959 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to in t4_cim_read_la()
9960 * identify the 32-bit portion of the full 312-bit data in t4_cim_read_la()
9962 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9) in t4_cim_read_la()
9980 * t4_tp_read_la - read TP LA capture buffer
9997 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); in t4_tp_read_la()
10009 val |= adap->params.tp.la_mask; in t4_tp_read_la()
10019 la_buf[TPLA_SIZE - 1] = ~0ULL; in t4_tp_read_la()
10023 cfg | adap->params.tp.la_mask); in t4_tp_read_la()
10037 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10058 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ in t4_idma_monitor_init()
10059 idma->idma_stalled[0] = 0; in t4_idma_monitor_init()
10060 idma->idma_stalled[1] = 0; in t4_idma_monitor_init()
10064 * t4_idma_monitor - monitor SGE Ingress DMA state
10096 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { in t4_idma_monitor()
10097 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz) in t4_idma_monitor()
10098 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, " in t4_idma_monitor()
10100 i, idma->idma_qid[i], in t4_idma_monitor()
10101 idma->idma_stalled[i] / hz); in t4_idma_monitor()
10102 idma->idma_stalled[i] = 0; in t4_idma_monitor()
10115 if (idma->idma_stalled[i] == 0) { in t4_idma_monitor()
10116 idma->idma_stalled[i] = hz; in t4_idma_monitor()
10117 idma->idma_warn[i] = 0; in t4_idma_monitor()
10119 idma->idma_stalled[i] += ticks; in t4_idma_monitor()
10120 idma->idma_warn[i] -= ticks; in t4_idma_monitor()
10123 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz) in t4_idma_monitor()
10128 if (idma->idma_warn[i] > 0) in t4_idma_monitor()
10130 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz; in t4_idma_monitor()
10138 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; in t4_idma_monitor()
10142 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; in t4_idma_monitor()
10144 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in " in t4_idma_monitor()
10146 i, idma->idma_qid[i], idma->idma_state[i], in t4_idma_monitor()
10147 idma->idma_stalled[i] / hz, in t4_idma_monitor()
10149 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); in t4_idma_monitor()
10154 * t4_load_cfg - download config file
10166 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_cfg()
10176 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n", in t4_load_cfg()
10178 return -EFBIG; in t4_load_cfg()
10184 flash_cfg_start_sec + i - 1); in t4_load_cfg()
10186 * with the on-adapter Firmware Configuration File. in t4_load_cfg()
10193 if ((size - i) < SF_PAGE_SIZE) in t4_load_cfg()
10194 n = size - i; in t4_load_cfg()
10207 dev_err(adap->pdev_dev, "config file %s failed %d\n", in t4_load_cfg()
10213 * t4_set_vf_mac_acl - Set MAC address for the specified VF
10228 FW_ACL_MAC_CMD_PFN_V(adapter->pf) | in t4_set_vf_mac_acl()
10235 switch (adapter->pf) { in t4_set_vf_mac_acl()
10250 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); in t4_set_vf_mac_acl()
10254 * t4_read_pace_tbl - read the pace table
10272 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10287 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2; in t4_get_tx_sched()
10296 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ in t4_get_tx_sched()
10301 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2; in t4_get_tx_sched()
10310 /* t4_sge_ctxt_rd - read an SGE context through FW
10350 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10399 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params()
10404 * t4_i2c_rd - read I2C data from adapter
10407 * @port: Port number if per-port device; <0 if not
10408 * @devid: per-port device ID or absolute device ID
10424 return -EINVAL; in t4_i2c_rd()
10428 return -EINVAL; in t4_i2c_rd()
10454 len -= i2c_len; in t4_i2c_rd()
10461 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10479 FW_ACL_VLAN_CMD_PFN_V(adap->pf) | in t4_set_vlan_acl()
10491 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); in t4_set_vlan_acl()
10495 * modify_device_id - Modifies the device ID of the Boot BIOS image
10511 pcir_offset = le16_to_cpu(header->pcir_offset); in modify_device_id()
10520 * 0x04-0xFF: Do not modify in modify_device_id()
10522 if (pcir_header->code_type == CXGB4_HDR_CODE1) { in modify_device_id()
10529 pcir_header->device_id = cpu_to_le16(device_id); in modify_device_id()
10535 header->cksum = 0x0; in modify_device_id()
10540 for (i = 0; i < (header->size512 * 512); i++) in modify_device_id()
10547 cur_header[7] = -csum; in modify_device_id()
10549 } else if (pcir_header->code_type == CXGB4_HDR_CODE2) { in modify_device_id()
10553 pcir_header->device_id = cpu_to_le16(device_id); in modify_device_id()
10559 cur_header += header->size512 * 512; in modify_device_id()
10560 } while (!(pcir_header->indicator & CXGB4_HDR_INDI)); in modify_device_id()
10564 * t4_load_boot - download boot flash
10571 * The boot image has the following sections: a 28-byte header and the
10577 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_boot()
10590 dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n"); in t4_load_boot()
10591 return -EFBIG; in t4_load_boot()
10596 pcir_offset = le16_to_cpu(header->pcir_offset); in t4_load_boot()
10606 dev_err(adap->pdev_dev, "boot image too small/large\n"); in t4_load_boot()
10607 return -EFBIG; in t4_load_boot()
10610 if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) { in t4_load_boot()
10611 dev_err(adap->pdev_dev, "Boot image missing signature\n"); in t4_load_boot()
10612 return -EINVAL; in t4_load_boot()
10616 if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) { in t4_load_boot()
10617 dev_err(adap->pdev_dev, "PCI header missing signature\n"); in t4_load_boot()
10618 return -EINVAL; in t4_load_boot()
10622 if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) { in t4_load_boot()
10623 dev_err(adap->pdev_dev, "Vendor ID missing signature\n"); in t4_load_boot()
10624 return -EINVAL; in t4_load_boot()
10628 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, in t4_load_boot()
10634 (boot_sector >> 16) + i - 1); in t4_load_boot()
10638 * with the on-adapter option ROM file in t4_load_boot()
10643 pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id); in t4_load_boot()
10648 if (le16_to_cpu(pcir_header->device_id) != device_id) { in t4_load_boot()
10663 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in t4_load_boot()
10677 dev_err(adap->pdev_dev, "boot image load failed, error %d\n", in t4_load_boot()
10683 * t4_flash_bootcfg_addr - return the address of the flash
10697 if (adapter->params.sf_size < in t4_flash_bootcfg_addr()
10699 return -ENOSPC; in t4_flash_bootcfg_addr()
10706 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_bootcfg()
10720 dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n", in t4_load_bootcfg()
10722 return -EFBIG; in t4_load_bootcfg()
10726 if (le16_to_cpu(header->signature) != BOOT_CFG_SIG) { in t4_load_bootcfg()
10727 dev_err(adap->pdev_dev, "Wrong bootcfg signature\n"); in t4_load_bootcfg()
10728 ret = -EINVAL; in t4_load_bootcfg()
10735 flash_cfg_start_sec + i - 1); in t4_load_bootcfg()
10739 * with the on-adapter OptionROM Configuration File. in t4_load_bootcfg()
10746 n = min_t(u32, size - i, SF_PAGE_SIZE); in t4_load_bootcfg()
10756 npad = ((size + 4 - 1) & ~3) - size; in t4_load_bootcfg()
10768 dev_err(adap->pdev_dev, "boot config data %s failed %d\n", in t4_load_bootcfg()