50  *	@adapter: the adapter performing the operation
61 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,  in t1_wait_op_done()  argument
65 		u32 val = readl(adapter->regs + reg) & mask;  in t1_wait_op_done()
81 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)  in __t1_tpi_write()  argument
85 	writel(addr, adapter->regs + A_TPI_ADDR);  in __t1_tpi_write()
86 	writel(value, adapter->regs + A_TPI_WR_DATA);  in __t1_tpi_write()
87 	writel(F_TPIWR, adapter->regs + A_TPI_CSR);  in __t1_tpi_write()
89 	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,  in __t1_tpi_write()
93 			 adapter->name, addr);  in __t1_tpi_write()
97 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)  in t1_tpi_write()  argument
101 	spin_lock(&adapter->tpi_lock);  in t1_tpi_write()
102 	ret = __t1_tpi_write(adapter, addr, value);  in t1_tpi_write()
103 	spin_unlock(&adapter->tpi_lock);  in t1_tpi_write()
110 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)  in __t1_tpi_read()  argument
114 	writel(addr, adapter->regs + A_TPI_ADDR);  in __t1_tpi_read()
115 	writel(0, adapter->regs + A_TPI_CSR);  in __t1_tpi_read()
117 	tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,  in __t1_tpi_read()
121 			 adapter->name, addr);  in __t1_tpi_read()
123 		*valp = readl(adapter->regs + A_TPI_RD_DATA);  in __t1_tpi_read()
127 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)  in t1_tpi_read()  argument
131 	spin_lock(&adapter->tpi_lock);  in t1_tpi_read()
132 	ret = __t1_tpi_read(adapter, addr, valp);  in t1_tpi_read()
133 	spin_unlock(&adapter->tpi_lock);  in t1_tpi_read()
140 static void t1_tpi_par(adapter_t *adapter, u32 value)  in t1_tpi_par()  argument
142 	writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);  in t1_tpi_par()
150 void t1_link_changed(adapter_t *adapter, int port_id)  in t1_link_changed()  argument
153 	struct cphy *phy = adapter->port[port_id].phy;  in t1_link_changed()
154 	struct link_config *lc = &adapter->port[port_id].link_config;  in t1_link_changed()
165 		struct cmac *mac = adapter->port[port_id].mac;  in t1_link_changed()
170 	t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);  in t1_link_changed()
173 static bool t1_pci_intr_handler(adapter_t *adapter)  in t1_pci_intr_handler()  argument
177 	pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);  in t1_pci_intr_handler()
180 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,  in t1_pci_intr_handler()
183 		t1_interrupts_disable(adapter);  in t1_pci_intr_handler()
184 		adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR;  in t1_pci_intr_handler()
185 		pr_alert("%s: PCI error encountered.\n", adapter->name);  in t1_pci_intr_handler()
197 static int fpga_phy_intr_handler(adapter_t *adapter)  in fpga_phy_intr_handler()  argument
200 	u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);  in fpga_phy_intr_handler()
202 	for_each_port(adapter, p)  in fpga_phy_intr_handler()
204 			struct cphy *phy = adapter->port[p].phy;  in fpga_phy_intr_handler()
208 				t1_link_changed(adapter, p);  in fpga_phy_intr_handler()
210 	writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);  in fpga_phy_intr_handler()
217 static irqreturn_t fpga_slow_intr(adapter_t *adapter)  in fpga_slow_intr()  argument
219 	u32 cause = readl(adapter->regs + A_PL_CAUSE);  in fpga_slow_intr()
224 		if (t1_sge_intr_error_handler(adapter->sge))  in fpga_slow_intr()
229 		fpga_phy_intr_handler(adapter);  in fpga_slow_intr()
236 		u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);  in fpga_slow_intr()
239 		writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);  in fpga_slow_intr()
242 		if (t1_pci_intr_handler(adapter))  in fpga_slow_intr()
248 		writel(cause, adapter->regs + A_PL_CAUSE);  in fpga_slow_intr()
260 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)  in mi1_wait_until_ready()  argument
267 		__t1_tpi_read(adapter, mi1_reg, &val);  in mi1_wait_until_ready()
273 		pr_alert("%s: MDIO operation timed out\n", adapter->name);  in mi1_wait_until_ready()
280 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)  in mi1_mdio_init()  argument
288 	t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);  in mi1_mdio_init()
298 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_read()  local
302 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_read()
303 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_read()
304 	__t1_tpi_write(adapter,  in mi1_mdio_read()
306 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_read()
307 	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);  in mi1_mdio_read()
308 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_read()
315 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_write()  local
318 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_write()
319 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_write()
320 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);  in mi1_mdio_write()
321 	__t1_tpi_write(adapter,  in mi1_mdio_write()
323 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_write()
324 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_write()
340 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_ext_read()  local
344 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_ext_read()
347 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_ext_read()
348 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);  in mi1_mdio_ext_read()
349 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,  in mi1_mdio_ext_read()
351 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_read()
354 	__t1_tpi_write(adapter,  in mi1_mdio_ext_read()
356 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_read()
359 	__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);  in mi1_mdio_ext_read()
360 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_ext_read()
367 	struct adapter *adapter = dev->ml_priv;  in mi1_mdio_ext_write()  local
370 	spin_lock(&adapter->tpi_lock);  in mi1_mdio_ext_write()
373 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);  in mi1_mdio_ext_write()
374 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);  in mi1_mdio_ext_write()
375 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,  in mi1_mdio_ext_write()
377 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_write()
380 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);  in mi1_mdio_ext_write()
381 	__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);  in mi1_mdio_ext_write()
382 	mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);  in mi1_mdio_ext_write()
383 	spin_unlock(&adapter->tpi_lock);  in mi1_mdio_ext_write()
574 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)  in t1_seeprom_read()  argument
583 	pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);  in t1_seeprom_read()
586 		pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);  in t1_seeprom_read()
591 		       adapter->name, addr);  in t1_seeprom_read()
594 	pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);  in t1_seeprom_read()
599 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)  in t1_eeprom_vpd_get()  argument
604 		ret = t1_seeprom_read(adapter, addr,  in t1_eeprom_vpd_get()
613 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])  in vpd_macaddress_get()  argument
617 	if (t1_eeprom_vpd_get(adapter, &vpd))  in vpd_macaddress_get()
643 				   (mac->adapter->params.nports < 2)))  in t1_link_start()
679 int t1_elmer0_ext_intr_handler(adapter_t *adapter)  in t1_elmer0_ext_intr_handler()  argument
685 	t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);  in t1_elmer0_ext_intr_handler()
687 	switch (board_info(adapter)->board) {  in t1_elmer0_ext_intr_handler()
694 		for_each_port(adapter, i) {  in t1_elmer0_ext_intr_handler()
699 			phy = adapter->port[i].phy;  in t1_elmer0_ext_intr_handler()
702 				t1_link_changed(adapter, i);  in t1_elmer0_ext_intr_handler()
708 			phy = adapter->port[0].phy;  in t1_elmer0_ext_intr_handler()
711 				t1_link_changed(adapter, 0);  in t1_elmer0_ext_intr_handler()
722 		for_each_port(adapter, p) {  in t1_elmer0_ext_intr_handler()
723 			phy = adapter->port[p].phy;  in t1_elmer0_ext_intr_handler()
726 			    t1_link_changed(adapter, p);  in t1_elmer0_ext_intr_handler()
735 			phy = adapter->port[0].phy;  in t1_elmer0_ext_intr_handler()
738 				t1_link_changed(adapter, 0);  in t1_elmer0_ext_intr_handler()
743 		if (netif_msg_intr(adapter))  in t1_elmer0_ext_intr_handler()
744 			dev_dbg(&adapter->pdev->dev,  in t1_elmer0_ext_intr_handler()
747 			struct cmac *mac = adapter->port[0].mac;  in t1_elmer0_ext_intr_handler()
754 			t1_tpi_read(adapter,  in t1_elmer0_ext_intr_handler()
756 			if (netif_msg_link(adapter))  in t1_elmer0_ext_intr_handler()
757 				dev_info(&adapter->pdev->dev, "XPAK %s\n",  in t1_elmer0_ext_intr_handler()
762 	t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);  in t1_elmer0_ext_intr_handler()
767 void t1_interrupts_enable(adapter_t *adapter)  in t1_interrupts_enable()  argument
771 	adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;  in t1_interrupts_enable()
773 	t1_sge_intr_enable(adapter->sge);  in t1_interrupts_enable()
774 	t1_tp_intr_enable(adapter->tp);  in t1_interrupts_enable()
775 	if (adapter->espi) {  in t1_interrupts_enable()
776 		adapter->slow_intr_mask |= F_PL_INTR_ESPI;  in t1_interrupts_enable()
777 		t1_espi_intr_enable(adapter->espi);  in t1_interrupts_enable()
781 	for_each_port(adapter, i) {  in t1_interrupts_enable()
782 		adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);  in t1_interrupts_enable()
783 		adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);  in t1_interrupts_enable()
787 	if (t1_is_asic(adapter)) {  in t1_interrupts_enable()
788 		u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);  in t1_interrupts_enable()
791 		pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,  in t1_interrupts_enable()
794 		adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;  in t1_interrupts_enable()
796 		writel(pl_intr, adapter->regs + A_PL_ENABLE);  in t1_interrupts_enable()
801 void t1_interrupts_disable(adapter_t* adapter)  in t1_interrupts_disable()  argument
805 	t1_sge_intr_disable(adapter->sge);  in t1_interrupts_disable()
806 	t1_tp_intr_disable(adapter->tp);  in t1_interrupts_disable()
807 	if (adapter->espi)  in t1_interrupts_disable()
808 		t1_espi_intr_disable(adapter->espi);  in t1_interrupts_disable()
811 	for_each_port(adapter, i) {  in t1_interrupts_disable()
812 		adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);  in t1_interrupts_disable()
813 		adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);  in t1_interrupts_disable()
817 	if (t1_is_asic(adapter))  in t1_interrupts_disable()
818 		writel(0, adapter->regs + A_PL_ENABLE);  in t1_interrupts_disable()
821 	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);  in t1_interrupts_disable()
823 	adapter->slow_intr_mask = 0;  in t1_interrupts_disable()
827 void t1_interrupts_clear(adapter_t* adapter)  in t1_interrupts_clear()  argument
831 	t1_sge_intr_clear(adapter->sge);  in t1_interrupts_clear()
832 	t1_tp_intr_clear(adapter->tp);  in t1_interrupts_clear()
833 	if (adapter->espi)  in t1_interrupts_clear()
834 		t1_espi_intr_clear(adapter->espi);  in t1_interrupts_clear()
837 	for_each_port(adapter, i) {  in t1_interrupts_clear()
838 		adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);  in t1_interrupts_clear()
839 		adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);  in t1_interrupts_clear()
843 	if (t1_is_asic(adapter)) {  in t1_interrupts_clear()
844 		u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);  in t1_interrupts_clear()
847 		       adapter->regs + A_PL_CAUSE);  in t1_interrupts_clear()
851 	pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);  in t1_interrupts_clear()
857 static irqreturn_t asic_slow_intr(adapter_t *adapter)  in asic_slow_intr()  argument
859 	u32 cause = readl(adapter->regs + A_PL_CAUSE);  in asic_slow_intr()
862 	cause &= adapter->slow_intr_mask;  in asic_slow_intr()
866 		if (t1_sge_intr_error_handler(adapter->sge))  in asic_slow_intr()
870 		t1_tp_intr_handler(adapter->tp);  in asic_slow_intr()
872 		t1_espi_intr_handler(adapter->espi);  in asic_slow_intr()
874 		if (t1_pci_intr_handler(adapter))  in asic_slow_intr()
882 		adapter->pending_thread_intr |= F_PL_INTR_EXT;  in asic_slow_intr()
883 		adapter->slow_intr_mask &= ~F_PL_INTR_EXT;  in asic_slow_intr()
884 		writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,  in asic_slow_intr()
885 		       adapter->regs + A_PL_ENABLE);  in asic_slow_intr()
890 	writel(cause, adapter->regs + A_PL_CAUSE);  in asic_slow_intr()
891 	readl(adapter->regs + A_PL_CAUSE); /* flush writes */  in asic_slow_intr()
895 irqreturn_t t1_slow_intr_handler(adapter_t *adapter)  in t1_slow_intr_handler()  argument
898 	if (!t1_is_asic(adapter))  in t1_slow_intr_handler()
899 		return fpga_slow_intr(adapter);  in t1_slow_intr_handler()
901 	return asic_slow_intr(adapter);  in t1_slow_intr_handler()
905 static void power_sequence_xpak(adapter_t* adapter)  in power_sequence_xpak()  argument
911 	t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);  in power_sequence_xpak()
914 		t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);  in power_sequence_xpak()
916 		t1_tpi_write(adapter, A_ELMER0_GPO, gpo);  in power_sequence_xpak()
920 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,  in t1_get_board_rev()  argument
928 		u32 val = readl(adapter->regs + A_TP_PC_CONFIG);  in t1_get_board_rev()
946 static int board_init(adapter_t *adapter, const struct board_info *bi)  in board_init()  argument
953 		t1_tpi_par(adapter, 0xf);  in board_init()
954 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);  in board_init()
957 		t1_tpi_par(adapter, 0xf);  in board_init()
958 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);  in board_init()
963 		power_sequence_xpak(adapter);  in board_init()
971 		t1_tpi_par(adapter, 0xf);  in board_init()
972 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);  in board_init()
976 		t1_tpi_par(adapter, 0xf);  in board_init()
977 		t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);  in board_init()
988 int t1_init_hw_modules(adapter_t *adapter)  in t1_init_hw_modules()  argument
991 	const struct board_info *bi = board_info(adapter);  in t1_init_hw_modules()
994 		u32 val = readl(adapter->regs + A_MC4_CFG);  in t1_init_hw_modules()
996 		writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);  in t1_init_hw_modules()
998 		       adapter->regs + A_MC5_CONFIG);  in t1_init_hw_modules()
1001 	if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,  in t1_init_hw_modules()
1005 	if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))  in t1_init_hw_modules()
1008 	err = t1_sge_configure(adapter->sge, &adapter->params.sge);  in t1_init_hw_modules()
1020 static void get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)  in get_pci_mode()  argument
1025 	pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);  in get_pci_mode()
1034 void t1_free_sw_modules(adapter_t *adapter)  in t1_free_sw_modules()  argument
1038 	for_each_port(adapter, i) {  in t1_free_sw_modules()
1039 		struct cmac *mac = adapter->port[i].mac;  in t1_free_sw_modules()
1040 		struct cphy *phy = adapter->port[i].phy;  in t1_free_sw_modules()
1048 	if (adapter->sge)  in t1_free_sw_modules()
1049 		t1_sge_destroy(adapter->sge);  in t1_free_sw_modules()
1050 	if (adapter->tp)  in t1_free_sw_modules()
1051 		t1_tp_destroy(adapter->tp);  in t1_free_sw_modules()
1052 	if (adapter->espi)  in t1_free_sw_modules()
1053 		t1_espi_destroy(adapter->espi);  in t1_free_sw_modules()
1077 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi)  in t1_init_sw_modules()  argument
1081 	adapter->params.brd_info = bi;  in t1_init_sw_modules()
1082 	adapter->params.nports = bi->port_number;  in t1_init_sw_modules()
1083 	adapter->params.stats_update_period = bi->gmac->stats_update_period;  in t1_init_sw_modules()
1085 	adapter->sge = t1_sge_create(adapter, &adapter->params.sge);  in t1_init_sw_modules()
1086 	if (!adapter->sge) {  in t1_init_sw_modules()
1088 		       adapter->name);  in t1_init_sw_modules()
1092 	if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {  in t1_init_sw_modules()
1094 		       adapter->name);  in t1_init_sw_modules()
1098 	adapter->tp = t1_tp_create(adapter, &adapter->params.tp);  in t1_init_sw_modules()
1099 	if (!adapter->tp) {  in t1_init_sw_modules()
1101 		       adapter->name);  in t1_init_sw_modules()
1105 	board_init(adapter, bi);  in t1_init_sw_modules()
1106 	bi->mdio_ops->init(adapter, bi);  in t1_init_sw_modules()
1108 		bi->gphy->reset(adapter);  in t1_init_sw_modules()
1110 		bi->gmac->reset(adapter);  in t1_init_sw_modules()
1112 	for_each_port(adapter, i) {  in t1_init_sw_modules()
1117 		adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,  in t1_init_sw_modules()
1119 		if (!adapter->port[i].phy) {  in t1_init_sw_modules()
1121 			       adapter->name, i);  in t1_init_sw_modules()
1125 		adapter->port[i].mac = mac = bi->gmac->create(adapter, i);  in t1_init_sw_modules()
1128 			       adapter->name, i);  in t1_init_sw_modules()
1136 		if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)  in t1_init_sw_modules()
1138 		else if (vpd_macaddress_get(adapter, i, hw_addr)) {  in t1_init_sw_modules()
1140 			       adapter->port[i].dev->name);  in t1_init_sw_modules()
1143 		memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);  in t1_init_sw_modules()
1144 		init_link_config(&adapter->port[i].link_config, bi);  in t1_init_sw_modules()
1147 	get_pci_mode(adapter, &adapter->params.pci);  in t1_init_sw_modules()
1148 	t1_interrupts_clear(adapter);  in t1_init_sw_modules()
1152 	t1_free_sw_modules(adapter);  in t1_init_sw_modules()