Lines Matching +full:max +full:- +full:bits +full:- +full:per +full:- +full:word
1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
23 #include "realtek-smi-core.h"
79 /* bits 0..7 = port 0, bits 8..15 = port 1 */
81 /* bits 0..7 = port 2, bits 8..15 = port 3 */
83 /* bits 0..7 = port 4, bits 8..15 = port 5 */
100 /* bits 0..7 = port 0, bits 8..15 = port 1 */
102 /* bits 0..7 = port 2, bits 8..15 = port 3 */
104 /* bits 0..7 = port 4, bits 8..15 = port 5 */
115 #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
116 #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
117 #define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
248 /* First configuration word per member config, VID and prio */
252 /* Second configuration word per member config, member and untagged */
256 /* Third config word per member config, STAG currently unused */
303 /* bits 0..5 enable force when cleared */
315 * struct rtl8366rb - RTL8366RB-specific data
316 * @max_mtu: per-port max MTU setting
369 mib->offset; in rtl8366rb_get_mib_counter()
372 * then ASIC will prepare 64bits counter wait for being retrived in rtl8366rb_get_mib_counter()
374 ret = regmap_write(smi->map, addr, 0); /* Write whatever */ in rtl8366rb_get_mib_counter()
379 ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val); in rtl8366rb_get_mib_counter()
381 return -EIO; in rtl8366rb_get_mib_counter()
384 return -EBUSY; in rtl8366rb_get_mib_counter()
387 return -EIO; in rtl8366rb_get_mib_counter()
389 /* Read each individual MIB 16 bits at the time */ in rtl8366rb_get_mib_counter()
391 for (i = mib->length; i > 0; i--) { in rtl8366rb_get_mib_counter()
392 ret = regmap_read(smi->map, addr + (i - 1), &val); in rtl8366rb_get_mib_counter()
405 /* For line interrupts we combine link down in bits in rtl8366rb_get_irqmask()
406 * 6..11 with link up in bits 0..5 into one interrupt. in rtl8366rb_get_irqmask()
420 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG, in rtl8366rb_mask_irq()
423 dev_err(smi->dev, "could not mask IRQ\n"); in rtl8366rb_mask_irq()
431 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG, in rtl8366rb_unmask_irq()
435 dev_err(smi->dev, "could not unmask IRQ\n"); in rtl8366rb_unmask_irq()
445 ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG, in rtl8366rb_irq()
448 dev_err(smi->dev, "can't read interrupt status\n"); in rtl8366rb_irq()
459 /* For line interrupts we combine link down in bits in rtl8366rb_irq()
460 * 6..11 with link up in bits 0..5 into one interrupt. in rtl8366rb_irq()
463 line -= 5; in rtl8366rb_irq()
464 child_irq = irq_find_mapping(smi->irqdomain, line); in rtl8366rb_irq()
479 irq_set_chip_data(irq, domain->host_data); in rtl8366rb_irq_map()
509 intc = of_get_child_by_name(smi->dev->of_node, "interrupt-controller"); in rtl8366rb_setup_cascaded_irq()
511 dev_err(smi->dev, "missing child interrupt-controller node\n"); in rtl8366rb_setup_cascaded_irq()
512 return -EINVAL; in rtl8366rb_setup_cascaded_irq()
517 dev_err(smi->dev, "failed to get parent IRQ\n"); in rtl8366rb_setup_cascaded_irq()
518 ret = irq ? irq : -EINVAL; in rtl8366rb_setup_cascaded_irq()
523 ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG, in rtl8366rb_setup_cascaded_irq()
526 dev_err(smi->dev, "can't read interrupt status\n"); in rtl8366rb_setup_cascaded_irq()
535 dev_info(smi->dev, "active high/rising IRQ\n"); in rtl8366rb_setup_cascaded_irq()
540 dev_info(smi->dev, "active low/falling IRQ\n"); in rtl8366rb_setup_cascaded_irq()
544 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_CONTROL_REG, in rtl8366rb_setup_cascaded_irq()
548 dev_err(smi->dev, "could not configure IRQ polarity\n"); in rtl8366rb_setup_cascaded_irq()
552 ret = devm_request_threaded_irq(smi->dev, irq, NULL, in rtl8366rb_setup_cascaded_irq()
556 dev_err(smi->dev, "unable to request irq: %d\n", ret); in rtl8366rb_setup_cascaded_irq()
559 smi->irqdomain = irq_domain_add_linear(intc, in rtl8366rb_setup_cascaded_irq()
563 if (!smi->irqdomain) { in rtl8366rb_setup_cascaded_irq()
564 dev_err(smi->dev, "failed to create IRQ domain\n"); in rtl8366rb_setup_cascaded_irq()
565 ret = -EINVAL; in rtl8366rb_setup_cascaded_irq()
568 for (i = 0; i < smi->num_ports; i++) in rtl8366rb_setup_cascaded_irq()
569 irq_set_parent(irq_create_mapping(smi->irqdomain, i), irq); in rtl8366rb_setup_cascaded_irq()
584 dev_info(smi->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", in rtl8366rb_set_addr()
587 ret = regmap_write(smi->map, RTL8366RB_SMAR0, val); in rtl8366rb_set_addr()
591 ret = regmap_write(smi->map, RTL8366RB_SMAR1, val); in rtl8366rb_set_addr()
595 ret = regmap_write(smi->map, RTL8366RB_SMAR2, val); in rtl8366rb_set_addr()
643 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
658 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
694 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
736 ret = regmap_read(smi->map, in rtl8366rb_jam_table()
742 ret = regmap_write(smi->map, in rtl8366rb_jam_table()
750 dev_dbg(smi->dev, "jam %04x into register %04x\n", in rtl8366rb_jam_table()
753 ret = regmap_write(smi->map, in rtl8366rb_jam_table()
764 struct realtek_smi *smi = ds->priv; in rtl8366rb_setup()
774 rb = smi->chip_data; in rtl8366rb_setup()
776 ret = regmap_read(smi->map, RTL8366RB_CHIP_ID_REG, &chip_id); in rtl8366rb_setup()
778 dev_err(smi->dev, "unable to read chip id\n"); in rtl8366rb_setup()
786 dev_err(smi->dev, "unknown chip id (%04x)\n", chip_id); in rtl8366rb_setup()
787 return -ENODEV; in rtl8366rb_setup()
790 ret = regmap_read(smi->map, RTL8366RB_CHIP_VERSION_CTRL_REG, in rtl8366rb_setup()
793 dev_err(smi->dev, "unable to read chip version\n"); in rtl8366rb_setup()
797 dev_info(smi->dev, "RTL%04x ver %u chip found\n", in rtl8366rb_setup()
822 * without them, using just the off-the-shelf tables. in rtl8366rb_setup()
824 if (of_machine_is_compatible("belkin,f5d8235-v1")) { in rtl8366rb_setup()
844 ret = regmap_write(smi->map, in rtl8366rb_setup()
851 ret = regmap_write(smi->map, 0x0c, 0x240); in rtl8366rb_setup()
854 ret = regmap_write(smi->map, 0x0d, 0x240); in rtl8366rb_setup()
868 ret = regmap_update_bits(smi->map, RTL8368RB_CPU_CTRL_REG, in rtl8366rb_setup()
870 BIT(smi->cpu_port)); in rtl8366rb_setup()
874 /* Make sure we default-enable the fixed CPU port */ in rtl8366rb_setup()
875 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, in rtl8366rb_setup()
876 BIT(smi->cpu_port), in rtl8366rb_setup()
882 ret = regmap_update_bits(smi->map, RTL8366RB_SGCR, in rtl8366rb_setup()
889 rb->max_mtu[i] = 1532; in rtl8366rb_setup()
892 ret = regmap_write(smi->map, RTL8366RB_SSCR0, 0); in rtl8366rb_setup()
897 ret = regmap_write(smi->map, RTL8366RB_SSCR1, 0); in rtl8366rb_setup()
908 ret = regmap_update_bits(smi->map, RTL8366RB_PMC0, in rtl8366rb_setup()
917 ret = regmap_write(smi->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, in rtl8366rb_setup()
923 ret = regmap_update_bits(smi->map, RTL8366RB_SSCR2, in rtl8366rb_setup()
929 ret = regmap_update_bits(smi->map, RTL8366RB_LED_BLINKRATE_REG, in rtl8366rb_setup()
940 if (smi->leds_disabled) { in rtl8366rb_setup()
942 regmap_update_bits(smi->map, in rtl8366rb_setup()
945 regmap_update_bits(smi->map, in rtl8366rb_setup()
948 regmap_update_bits(smi->map, in rtl8366rb_setup()
954 /* TODO: make this configurable per LED */ in rtl8366rb_setup()
958 ret = regmap_update_bits(smi->map, in rtl8366rb_setup()
972 dev_info(smi->dev, "no interrupt support\n"); in rtl8366rb_setup()
976 dev_info(smi->dev, "could not set up MDIO bus\n"); in rtl8366rb_setup()
977 return -ENODEV; in rtl8366rb_setup()
980 ds->configure_vlan_while_not_filtering = false; in rtl8366rb_setup()
998 struct realtek_smi *smi = ds->priv; in rtl8366rb_mac_link_up()
1001 if (port != smi->cpu_port) in rtl8366rb_mac_link_up()
1004 dev_dbg(smi->dev, "MAC link up on CPU port (%d)\n", port); in rtl8366rb_mac_link_up()
1007 ret = regmap_update_bits(smi->map, RTL8366RB_MAC_FORCE_CTRL_REG, in rtl8366rb_mac_link_up()
1010 dev_err(smi->dev, "failed to force 1Gbit on CPU port\n"); in rtl8366rb_mac_link_up()
1014 ret = regmap_update_bits(smi->map, RTL8366RB_PAACR2, in rtl8366rb_mac_link_up()
1018 dev_err(smi->dev, "failed to set PAACR on CPU port\n"); in rtl8366rb_mac_link_up()
1023 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), in rtl8366rb_mac_link_up()
1026 dev_err(smi->dev, "failed to enable the CPU port\n"); in rtl8366rb_mac_link_up()
1035 struct realtek_smi *smi = ds->priv; in rtl8366rb_mac_link_down()
1038 if (port != smi->cpu_port) in rtl8366rb_mac_link_down()
1041 dev_dbg(smi->dev, "MAC link down on CPU port (%d)\n", port); in rtl8366rb_mac_link_down()
1044 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), in rtl8366rb_mac_link_down()
1047 dev_err(smi->dev, "failed to disable the CPU port\n"); in rtl8366rb_mac_link_down()
1058 if (smi->leds_disabled) in rb8366rb_set_port_led()
1063 ret = regmap_update_bits(smi->map, in rb8366rb_set_port_led()
1068 ret = regmap_update_bits(smi->map, in rb8366rb_set_port_led()
1074 ret = regmap_update_bits(smi->map, in rb8366rb_set_port_led()
1079 ret = regmap_update_bits(smi->map, in rb8366rb_set_port_led()
1085 ret = regmap_update_bits(smi->map, in rb8366rb_set_port_led()
1091 dev_err(smi->dev, "no LED for port %d\n", port); in rb8366rb_set_port_led()
1095 dev_err(smi->dev, "error updating LED on port %d\n", port); in rb8366rb_set_port_led()
1102 struct realtek_smi *smi = ds->priv; in rtl8366rb_port_enable()
1105 dev_dbg(smi->dev, "enable port %d\n", port); in rtl8366rb_port_enable()
1106 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), in rtl8366rb_port_enable()
1118 struct realtek_smi *smi = ds->priv; in rtl8366rb_port_disable()
1121 dev_dbg(smi->dev, "disable port %d\n", port); in rtl8366rb_port_disable()
1122 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port), in rtl8366rb_port_disable()
1132 struct realtek_smi *smi = ds->priv; in rtl8366rb_change_mtu()
1138 /* Cache the per-port MTU setting */ in rtl8366rb_change_mtu()
1139 rb = smi->chip_data; in rtl8366rb_change_mtu()
1140 rb->max_mtu[port] = new_mtu; in rtl8366rb_change_mtu()
1146 * The first setting, 1522 bytes, is max IP packet 1500 bytes, in rtl8366rb_change_mtu()
1155 if (rb->max_mtu[i] > max_mtu) in rtl8366rb_change_mtu()
1156 max_mtu = rb->max_mtu[i]; in rtl8366rb_change_mtu()
1167 return regmap_update_bits(smi->map, RTL8366RB_SGCR, in rtl8366rb_change_mtu()
1174 /* The max MTU is 16000 bytes, so we subtract the CPU tag in rtl8366rb_max_mtu()
1175 * and the max presented to the system is 15996 bytes. in rtl8366rb_max_mtu()
1190 return -EINVAL; in rtl8366rb_get_vlan_4k()
1193 ret = regmap_write(smi->map, RTL8366RB_VLAN_TABLE_WRITE_BASE, in rtl8366rb_get_vlan_4k()
1198 /* write table access control word */ in rtl8366rb_get_vlan_4k()
1199 ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, in rtl8366rb_get_vlan_4k()
1205 ret = regmap_read(smi->map, in rtl8366rb_get_vlan_4k()
1212 vlan4k->vid = vid; in rtl8366rb_get_vlan_4k()
1213 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & in rtl8366rb_get_vlan_4k()
1215 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; in rtl8366rb_get_vlan_4k()
1216 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK; in rtl8366rb_get_vlan_4k()
1228 if (vlan4k->vid >= RTL8366RB_NUM_VIDS || in rtl8366rb_set_vlan_4k()
1229 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK || in rtl8366rb_set_vlan_4k()
1230 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK || in rtl8366rb_set_vlan_4k()
1231 vlan4k->fid > RTL8366RB_FIDMAX) in rtl8366rb_set_vlan_4k()
1232 return -EINVAL; in rtl8366rb_set_vlan_4k()
1234 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK; in rtl8366rb_set_vlan_4k()
1235 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) | in rtl8366rb_set_vlan_4k()
1236 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) << in rtl8366rb_set_vlan_4k()
1238 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK; in rtl8366rb_set_vlan_4k()
1241 ret = regmap_write(smi->map, in rtl8366rb_set_vlan_4k()
1248 /* write table access control word */ in rtl8366rb_set_vlan_4k()
1249 ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, in rtl8366rb_set_vlan_4k()
1265 return -EINVAL; in rtl8366rb_get_vlan_mc()
1268 ret = regmap_read(smi->map, in rtl8366rb_get_vlan_mc()
1275 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK; in rtl8366rb_get_vlan_mc()
1276 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) & in rtl8366rb_get_vlan_mc()
1278 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & in rtl8366rb_get_vlan_mc()
1280 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; in rtl8366rb_get_vlan_mc()
1281 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK; in rtl8366rb_get_vlan_mc()
1294 vlanmc->vid >= RTL8366RB_NUM_VIDS || in rtl8366rb_set_vlan_mc()
1295 vlanmc->priority > RTL8366RB_PRIORITYMAX || in rtl8366rb_set_vlan_mc()
1296 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK || in rtl8366rb_set_vlan_mc()
1297 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK || in rtl8366rb_set_vlan_mc()
1298 vlanmc->fid > RTL8366RB_FIDMAX) in rtl8366rb_set_vlan_mc()
1299 return -EINVAL; in rtl8366rb_set_vlan_mc()
1301 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) | in rtl8366rb_set_vlan_mc()
1302 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) << in rtl8366rb_set_vlan_mc()
1304 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) | in rtl8366rb_set_vlan_mc()
1305 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) << in rtl8366rb_set_vlan_mc()
1307 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK; in rtl8366rb_set_vlan_mc()
1310 ret = regmap_write(smi->map, in rtl8366rb_set_vlan_mc()
1325 if (port >= smi->num_ports) in rtl8366rb_get_mc_index()
1326 return -EINVAL; in rtl8366rb_get_mc_index()
1328 ret = regmap_read(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), in rtl8366rb_get_mc_index()
1341 if (port >= smi->num_ports || index >= RTL8366RB_NUM_VLANS) in rtl8366rb_set_mc_index()
1342 return -EINVAL; in rtl8366rb_set_mc_index()
1344 return regmap_update_bits(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), in rtl8366rb_set_mc_index()
1353 unsigned int max = RTL8366RB_NUM_VLANS; in rtl8366rb_is_vlan_valid() local
1355 if (smi->vlan4k_enabled) in rtl8366rb_is_vlan_valid()
1356 max = RTL8366RB_NUM_VIDS - 1; in rtl8366rb_is_vlan_valid()
1358 if (vlan == 0 || vlan > max) in rtl8366rb_is_vlan_valid()
1366 dev_dbg(smi->dev, "%s VLAN\n", enable ? "enable" : "disable"); in rtl8366rb_enable_vlan()
1367 return regmap_update_bits(smi->map, in rtl8366rb_enable_vlan()
1374 dev_dbg(smi->dev, "%s VLAN 4k\n", enable ? "enable" : "disable"); in rtl8366rb_enable_vlan4k()
1375 return regmap_update_bits(smi->map, RTL8366RB_SGCR, in rtl8366rb_enable_vlan4k()
1387 return -EINVAL; in rtl8366rb_phy_read()
1389 ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG, in rtl8366rb_phy_read()
1396 ret = regmap_write(smi->map, reg, 0); in rtl8366rb_phy_read()
1398 dev_err(smi->dev, in rtl8366rb_phy_read()
1404 ret = regmap_read(smi->map, RTL8366RB_PHY_ACCESS_DATA_REG, &val); in rtl8366rb_phy_read()
1408 dev_dbg(smi->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n", in rtl8366rb_phy_read()
1421 return -EINVAL; in rtl8366rb_phy_write()
1423 ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG, in rtl8366rb_phy_write()
1430 dev_dbg(smi->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n", in rtl8366rb_phy_write()
1433 ret = regmap_write(smi->map, reg, val); in rtl8366rb_phy_write()
1450 ret = regmap_read(smi->map, RTL8366RB_RESET_CTRL_REG, &val); in rtl8366rb_reset_chip()
1456 } while (--timeout); in rtl8366rb_reset_chip()
1459 dev_err(smi->dev, "timeout waiting for the switch to reset\n"); in rtl8366rb_reset_chip()
1460 return -EIO; in rtl8366rb_reset_chip()
1468 struct device *dev = smi->dev; in rtl8366rb_detect()
1473 ret = regmap_read(smi->map, 0x5c, &val); in rtl8366rb_detect()
1483 return -ENODEV; in rtl8366rb_detect()
1486 smi->cpu_port = RTL8366RB_PORT_NUM_CPU; in rtl8366rb_detect()
1487 smi->num_ports = RTL8366RB_NUM_PORTS; in rtl8366rb_detect()
1488 smi->num_vlan_mc = RTL8366RB_NUM_VLANS; in rtl8366rb_detect()
1489 smi->mib_counters = rtl8366rb_mib_counters; in rtl8366rb_detect()
1490 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters); in rtl8366rb_detect()