Lines Matching +full:rx +full:- +full:internal +full:- +full:delay +full:- +full:ps
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
97 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read32()
100 ret = bus->read(bus, phy_id, regnum + 1); in qca8k_mii_read32()
105 dev_err_ratelimited(&bus->dev, in qca8k_mii_read32()
123 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_mii_write32()
125 ret = bus->write(bus, phy_id, regnum + 1, hi); in qca8k_mii_write32()
127 dev_err_ratelimited(&bus->dev, in qca8k_mii_write32()
139 ret = bus->write(bus, 0x18, 0, page); in qca8k_set_page()
141 dev_err_ratelimited(&bus->dev, in qca8k_set_page()
154 struct mii_bus *bus = priv->bus; in qca8k_read()
160 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_read()
169 mutex_unlock(&bus->mdio_lock); in qca8k_read()
176 struct mii_bus *bus = priv->bus; in qca8k_write()
182 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_write()
191 mutex_unlock(&bus->mdio_lock); in qca8k_write()
198 struct mii_bus *bus = priv->bus; in qca8k_rmw()
205 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_rmw()
220 mutex_unlock(&bus->mdio_lock); in qca8k_rmw()
262 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
263 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
264 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
265 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
266 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
267 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
268 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
281 .max_register = 0x16ac, /* end MIB - Port6 range */
298 * before returning -ETIMEDOUT in qca8k_busy_wait()
321 /* vid - 83:72 */ in qca8k_fdb_read()
322 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M; in qca8k_fdb_read()
323 /* aging - 67:64 */ in qca8k_fdb_read()
324 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M; in qca8k_fdb_read()
325 /* portmask - 54:48 */ in qca8k_fdb_read()
326 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M; in qca8k_fdb_read()
327 /* mac - 47:0 */ in qca8k_fdb_read()
328 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff; in qca8k_fdb_read()
329 fdb->mac[1] = reg[1] & 0xff; in qca8k_fdb_read()
330 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff; in qca8k_fdb_read()
331 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff; in qca8k_fdb_read()
332 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff; in qca8k_fdb_read()
333 fdb->mac[5] = reg[0] & 0xff; in qca8k_fdb_read()
345 /* vid - 83:72 */ in qca8k_fdb_write()
347 /* aging - 67:64 */ in qca8k_fdb_write()
349 /* portmask - 54:48 */ in qca8k_fdb_write()
351 /* mac - 47:0 */ in qca8k_fdb_write()
394 return -1; in qca8k_fdb_access()
405 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); in qca8k_fdb_next()
419 mutex_lock(&priv->reg_mutex); in qca8k_fdb_add()
421 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); in qca8k_fdb_add()
422 mutex_unlock(&priv->reg_mutex); in qca8k_fdb_add()
432 mutex_lock(&priv->reg_mutex); in qca8k_fdb_del()
434 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); in qca8k_fdb_del()
435 mutex_unlock(&priv->reg_mutex); in qca8k_fdb_del()
443 mutex_lock(&priv->reg_mutex); in qca8k_fdb_flush()
444 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1); in qca8k_fdb_flush()
445 mutex_unlock(&priv->reg_mutex); in qca8k_fdb_flush()
475 return -ENOMEM; in qca8k_vlan_access()
494 mutex_lock(&priv->reg_mutex); in qca8k_vlan_add()
517 mutex_unlock(&priv->reg_mutex); in qca8k_vlan_add()
529 mutex_lock(&priv->reg_mutex); in qca8k_vlan_del()
563 mutex_unlock(&priv->reg_mutex); in qca8k_vlan_del()
573 mutex_lock(&priv->reg_mutex); in qca8k_mib_init()
589 mutex_unlock(&priv->reg_mutex); in qca8k_mib_init()
598 /* Port 0 and 6 have no internal PHY */ in qca8k_port_set_status()
612 * Port 0 has no internal phy. in qca8k_port_to_phy()
613 * Port 1 has an internal PHY at MDIO address 0. in qca8k_port_to_phy()
614 * Port 2 has an internal PHY at MDIO address 1. in qca8k_port_to_phy()
616 * Port 5 has an internal PHY at MDIO address 4. in qca8k_port_to_phy()
617 * Port 6 has no internal PHY. in qca8k_port_to_phy()
620 return port - 1; in qca8k_port_to_phy()
637 * before returnting -ETIMEDOUT in qca8k_mdio_busy_wait()
653 return -EINVAL; in qca8k_mdio_write()
662 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_mdio_write()
677 mutex_unlock(&bus->mdio_lock); in qca8k_mdio_write()
690 return -EINVAL; in qca8k_mdio_read()
698 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_mdio_read()
717 mutex_unlock(&bus->mdio_lock); in qca8k_mdio_read()
728 struct qca8k_priv *priv = slave_bus->priv; in qca8k_internal_mdio_write()
729 struct mii_bus *bus = priv->bus; in qca8k_internal_mdio_write()
737 struct qca8k_priv *priv = slave_bus->priv; in qca8k_internal_mdio_read()
738 struct mii_bus *bus = priv->bus; in qca8k_internal_mdio_read()
746 struct qca8k_priv *priv = ds->priv; in qca8k_phy_write()
752 if (priv->legacy_phy_port_mapping) in qca8k_phy_write()
755 return qca8k_mdio_write(priv->bus, port, regnum, data); in qca8k_phy_write()
761 struct qca8k_priv *priv = ds->priv; in qca8k_phy_read()
768 if (priv->legacy_phy_port_mapping) in qca8k_phy_read()
771 ret = qca8k_mdio_read(priv->bus, port, regnum); in qca8k_phy_read()
782 struct dsa_switch *ds = priv->ds; in qca8k_mdio_register()
785 bus = devm_mdiobus_alloc(ds->dev); in qca8k_mdio_register()
788 return -ENOMEM; in qca8k_mdio_register()
790 bus->priv = (void *)priv; in qca8k_mdio_register()
791 bus->name = "qca8k slave mii"; in qca8k_mdio_register()
792 bus->read = qca8k_internal_mdio_read; in qca8k_mdio_register()
793 bus->write = qca8k_internal_mdio_write; in qca8k_mdio_register()
794 snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d", in qca8k_mdio_register()
795 ds->index); in qca8k_mdio_register()
797 bus->parent = ds->dev; in qca8k_mdio_register()
798 bus->phy_mask = ~ds->phys_mii_mask; in qca8k_mdio_register()
800 ds->slave_mii_bus = bus; in qca8k_mdio_register()
802 return devm_of_mdiobus_register(priv->dev, bus, mdio); in qca8k_mdio_register()
813 ports = of_get_child_by_name(priv->dev->of_node, "ports"); in qca8k_setup_mdio_bus()
815 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports"); in qca8k_setup_mdio_bus()
818 return -EINVAL; in qca8k_setup_mdio_bus()
828 if (!dsa_is_user_port(priv->ds, reg)) in qca8k_setup_mdio_bus()
833 if (of_property_read_bool(port, "phy-handle") && in qca8k_setup_mdio_bus()
842 dev_err(priv->dev, "no PHYs are defined.\n"); in qca8k_setup_mdio_bus()
843 return -EINVAL; in qca8k_setup_mdio_bus()
848 * passthrough to the internal PHYs. It's not possible to use both in qca8k_setup_mdio_bus()
852 * If the external mdio-bus driver is capable magically disabling in qca8k_setup_mdio_bus()
853 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's in qca8k_setup_mdio_bus()
858 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n"); in qca8k_setup_mdio_bus()
859 return -EINVAL; in qca8k_setup_mdio_bus()
863 /* Make sure to disable the internal mdio bus in cases in qca8k_setup_mdio_bus()
864 * a dt-overlay and driver reload changed the configuration in qca8k_setup_mdio_bus()
872 mdio = of_get_child_by_name(priv->dev->of_node, "mdio"); in qca8k_setup_mdio_bus()
884 priv->legacy_phy_port_mapping = true; in qca8k_setup_mdio_bus()
885 priv->ops.phy_read = qca8k_phy_read; in qca8k_setup_mdio_bus()
886 priv->ops.phy_write = qca8k_phy_write; in qca8k_setup_mdio_bus()
900 dp = dsa_to_port(priv->ds, 0); in qca8k_setup_of_rgmii_delay()
902 port_dn = dp->dn; in qca8k_setup_of_rgmii_delay()
915 if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val)) in qca8k_setup_of_rgmii_delay()
918 /* Switch regs accept value in ns, convert ps to ns */ in qca8k_setup_of_rgmii_delay()
922 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); in qca8k_setup_of_rgmii_delay()
926 priv->rgmii_rx_delay = val; in qca8k_setup_of_rgmii_delay()
927 /* Stop here if we need to check only for rx delay */ in qca8k_setup_of_rgmii_delay()
933 if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val)) in qca8k_setup_of_rgmii_delay()
936 /* Switch regs accept value in ns, convert ps to ns */ in qca8k_setup_of_rgmii_delay()
940 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); in qca8k_setup_of_rgmii_delay()
944 priv->rgmii_tx_delay = val; in qca8k_setup_of_rgmii_delay()
956 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_setup()
962 dev_err(priv->dev, "port 0 is not the CPU port"); in qca8k_setup()
963 return -EINVAL; in qca8k_setup()
966 mutex_init(&priv->reg_mutex); in qca8k_setup()
969 priv->regmap = devm_regmap_init(ds->dev, NULL, priv, in qca8k_setup()
971 if (IS_ERR(priv->regmap)) in qca8k_setup()
972 dev_warn(priv->dev, "regmap initialization failed"); in qca8k_setup()
986 dev_err(priv->dev, "failed enabling CPU port"); in qca8k_setup()
993 dev_warn(priv->dev, "mib init failed"); in qca8k_setup()
1000 dev_err(priv->dev, "failed enabling QCA header mode"); in qca8k_setup()
1045 /* Enable ARP Auto-learning by default */ in qca8k_setup()
1074 if (priv->switch_id == QCA8K_ID_QCA8337) { in qca8k_setup()
1114 if (priv->switch_id == QCA8K_ID_QCA8327) { in qca8k_setup()
1125 priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; in qca8k_setup()
1128 dev_warn(priv->dev, "failed setting MTU settings"); in qca8k_setup()
1134 ds->pcs_poll = true; in qca8k_setup()
1143 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_config()
1149 if (state->interface != PHY_INTERFACE_MODE_RGMII && in qca8k_phylink_mac_config()
1150 state->interface != PHY_INTERFACE_MODE_RGMII_ID && in qca8k_phylink_mac_config()
1151 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && in qca8k_phylink_mac_config()
1152 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && in qca8k_phylink_mac_config()
1153 state->interface != PHY_INTERFACE_MODE_SGMII) in qca8k_phylink_mac_config()
1163 /* Internal PHY, nothing to do */ in qca8k_phylink_mac_config()
1166 if (state->interface != PHY_INTERFACE_MODE_RGMII && in qca8k_phylink_mac_config()
1167 state->interface != PHY_INTERFACE_MODE_RGMII_ID && in qca8k_phylink_mac_config()
1168 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && in qca8k_phylink_mac_config()
1169 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && in qca8k_phylink_mac_config()
1170 state->interface != PHY_INTERFACE_MODE_SGMII && in qca8k_phylink_mac_config()
1171 state->interface != PHY_INTERFACE_MODE_1000BASEX) in qca8k_phylink_mac_config()
1177 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); in qca8k_phylink_mac_config()
1182 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", in qca8k_phylink_mac_config()
1187 switch (state->interface) { in qca8k_phylink_mac_config()
1189 /* RGMII mode means no delay so don't enable the delay */ in qca8k_phylink_mac_config()
1195 /* RGMII_ID needs internal delay. This is enabled through in qca8k_phylink_mac_config()
1201 QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) | in qca8k_phylink_mac_config()
1202 QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) | in qca8k_phylink_mac_config()
1205 /* QCA8337 requires to set rgmii rx delay */ in qca8k_phylink_mac_config()
1206 if (priv->switch_id == QCA8K_ID_QCA8337) in qca8k_phylink_mac_config()
1215 /* Enable/disable SerDes auto-negotiation as necessary */ in qca8k_phylink_mac_config()
1237 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { in qca8k_phylink_mac_config()
1240 } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) { in qca8k_phylink_mac_config()
1248 dev_err(ds->dev, "xMII mode %s not supported for port %d\n", in qca8k_phylink_mac_config()
1249 phy_modes(state->interface), port); in qca8k_phylink_mac_config()
1263 if (state->interface != PHY_INTERFACE_MODE_NA && in qca8k_phylink_validate()
1264 state->interface != PHY_INTERFACE_MODE_RGMII && in qca8k_phylink_validate()
1265 state->interface != PHY_INTERFACE_MODE_RGMII_ID && in qca8k_phylink_validate()
1266 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && in qca8k_phylink_validate()
1267 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && in qca8k_phylink_validate()
1268 state->interface != PHY_INTERFACE_MODE_SGMII) in qca8k_phylink_validate()
1276 /* Internal PHY */ in qca8k_phylink_validate()
1277 if (state->interface != PHY_INTERFACE_MODE_NA && in qca8k_phylink_validate()
1278 state->interface != PHY_INTERFACE_MODE_GMII && in qca8k_phylink_validate()
1279 state->interface != PHY_INTERFACE_MODE_INTERNAL) in qca8k_phylink_validate()
1283 if (state->interface != PHY_INTERFACE_MODE_NA && in qca8k_phylink_validate()
1284 state->interface != PHY_INTERFACE_MODE_RGMII && in qca8k_phylink_validate()
1285 state->interface != PHY_INTERFACE_MODE_RGMII_ID && in qca8k_phylink_validate()
1286 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && in qca8k_phylink_validate()
1287 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && in qca8k_phylink_validate()
1288 state->interface != PHY_INTERFACE_MODE_SGMII && in qca8k_phylink_validate()
1289 state->interface != PHY_INTERFACE_MODE_1000BASEX) in qca8k_phylink_validate()
1307 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) in qca8k_phylink_validate()
1314 linkmode_and(state->advertising, state->advertising, mask); in qca8k_phylink_validate()
1321 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_link_state()
1329 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); in qca8k_phylink_mac_link_state()
1330 state->an_complete = state->link; in qca8k_phylink_mac_link_state()
1331 state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO); in qca8k_phylink_mac_link_state()
1332 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL : in qca8k_phylink_mac_link_state()
1337 state->speed = SPEED_10; in qca8k_phylink_mac_link_state()
1340 state->speed = SPEED_100; in qca8k_phylink_mac_link_state()
1343 state->speed = SPEED_1000; in qca8k_phylink_mac_link_state()
1346 state->speed = SPEED_UNKNOWN; in qca8k_phylink_mac_link_state()
1350 state->pause = MLO_PAUSE_NONE; in qca8k_phylink_mac_link_state()
1352 state->pause |= MLO_PAUSE_RX; in qca8k_phylink_mac_link_state()
1354 state->pause |= MLO_PAUSE_TX; in qca8k_phylink_mac_link_state()
1363 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_link_down()
1373 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_link_up()
1426 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_get_ethtool_stats()
1434 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; in qca8k_get_ethtool_stats()
1440 if (mib->size == 2) { in qca8k_get_ethtool_stats()
1447 if (mib->size == 2) in qca8k_get_ethtool_stats()
1464 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_set_mac_eee()
1469 mutex_lock(&priv->reg_mutex); in qca8k_set_mac_eee()
1474 if (eee->eee_enabled) in qca8k_set_mac_eee()
1481 mutex_unlock(&priv->reg_mutex); in qca8k_set_mac_eee()
1495 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_port_stp_state_set()
1524 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_port_bridge_join()
1529 if (dsa_to_port(ds, i)->bridge_dev != br) in qca8k_port_bridge_join()
1553 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_port_bridge_leave()
1557 if (dsa_to_port(ds, i)->bridge_dev != br) in qca8k_port_bridge_leave()
1578 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_port_enable()
1581 priv->port_sts[port].enabled = 1; in qca8k_port_enable()
1592 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_port_disable()
1595 priv->port_sts[port].enabled = 0; in qca8k_port_disable()
1601 struct qca8k_priv *priv = ds->priv; in qca8k_port_change_mtu()
1604 priv->port_mtu[port] = new_mtu; in qca8k_port_change_mtu()
1607 if (priv->port_mtu[i] > mtu) in qca8k_port_change_mtu()
1608 mtu = priv->port_mtu[i]; in qca8k_port_change_mtu()
1636 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_port_fdb_add()
1646 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_port_fdb_del()
1659 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; in qca8k_port_fdb_dump()
1665 mutex_lock(&priv->reg_mutex); in qca8k_port_fdb_dump()
1666 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) { in qca8k_port_fdb_dump()
1674 mutex_unlock(&priv->reg_mutex); in qca8k_port_fdb_dump()
1683 struct qca8k_priv *priv = ds->priv; in qca8k_port_vlan_filtering()
1704 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in qca8k_port_vlan_add()
1705 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in qca8k_port_vlan_add()
1706 struct qca8k_priv *priv = ds->priv; in qca8k_port_vlan_add()
1709 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged); in qca8k_port_vlan_add()
1711 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret); in qca8k_port_vlan_add()
1719 0xfff << shift, vlan->vid << shift); in qca8k_port_vlan_add()
1724 QCA8K_PORT_VLAN_CVID(vlan->vid) | in qca8k_port_vlan_add()
1725 QCA8K_PORT_VLAN_SVID(vlan->vid)); in qca8k_port_vlan_add()
1735 struct qca8k_priv *priv = ds->priv; in qca8k_port_vlan_del()
1738 ret = qca8k_vlan_del(priv, port, vlan->vid); in qca8k_port_vlan_del()
1740 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret); in qca8k_port_vlan_del()
1747 struct qca8k_priv *priv = ds->priv; in qca8k_get_phy_flags()
1749 /* Communicate to the phy internal driver the switch revision. in qca8k_get_phy_flags()
1756 return priv->switch_revision; in qca8k_get_phy_flags()
1805 data = of_device_get_match_data(priv->dev); in qca8k_read_switch_id()
1807 return -ENODEV; in qca8k_read_switch_id()
1811 return -ENODEV; in qca8k_read_switch_id()
1814 if (id != data->id) { in qca8k_read_switch_id()
1815 dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id); in qca8k_read_switch_id()
1816 return -ENODEV; in qca8k_read_switch_id()
1819 priv->switch_id = id; in qca8k_read_switch_id()
1821 /* Save revision to communicate to the internal PHY driver */ in qca8k_read_switch_id()
1822 priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK); in qca8k_read_switch_id()
1836 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); in qca8k_sw_probe()
1838 return -ENOMEM; in qca8k_sw_probe()
1840 priv->bus = mdiodev->bus; in qca8k_sw_probe()
1841 priv->dev = &mdiodev->dev; in qca8k_sw_probe()
1843 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset", in qca8k_sw_probe()
1845 if (IS_ERR(priv->reset_gpio)) in qca8k_sw_probe()
1846 return PTR_ERR(priv->reset_gpio); in qca8k_sw_probe()
1848 if (priv->reset_gpio) { in qca8k_sw_probe()
1849 gpiod_set_value_cansleep(priv->reset_gpio, 1); in qca8k_sw_probe()
1854 gpiod_set_value_cansleep(priv->reset_gpio, 0); in qca8k_sw_probe()
1862 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); in qca8k_sw_probe()
1863 if (!priv->ds) in qca8k_sw_probe()
1864 return -ENOMEM; in qca8k_sw_probe()
1866 priv->ds->dev = &mdiodev->dev; in qca8k_sw_probe()
1867 priv->ds->num_ports = QCA8K_NUM_PORTS; in qca8k_sw_probe()
1868 priv->ds->priv = priv; in qca8k_sw_probe()
1869 priv->ops = qca8k_switch_ops; in qca8k_sw_probe()
1870 priv->ds->ops = &priv->ops; in qca8k_sw_probe()
1871 mutex_init(&priv->reg_mutex); in qca8k_sw_probe()
1872 dev_set_drvdata(&mdiodev->dev, priv); in qca8k_sw_probe()
1874 return dsa_register_switch(priv->ds); in qca8k_sw_probe()
1880 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); in qca8k_sw_remove()
1889 dsa_unregister_switch(priv->ds); in qca8k_sw_remove()
1891 dev_set_drvdata(&mdiodev->dev, NULL); in qca8k_sw_remove()
1896 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); in qca8k_sw_shutdown()
1901 dsa_switch_shutdown(priv->ds); in qca8k_sw_shutdown()
1903 dev_set_drvdata(&mdiodev->dev, NULL); in qca8k_sw_shutdown()
1913 if (!priv->port_sts[i].enabled) in qca8k_set_pm()
1926 return dsa_switch_suspend(priv->ds); in qca8k_suspend()
1935 return dsa_switch_resume(priv->ds); in qca8k_resume()