Lines Matching +full:0 +full:x5000
16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS 0x00
18 #define MV88E6352_G1_STS_PPU_STATE 0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
34 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
36 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
37 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
38 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
40 #define MV88E6XXX_G1_MAC_01 0x01
41 #define MV88E6XXX_G1_MAC_23 0x02
42 #define MV88E6XXX_G1_MAC_45 0x03
44 /* Offset 0x01: ATU FID Register */
45 #define MV88E6352_G1_ATU_FID 0x01
47 /* Offset 0x02: VTU FID Register */
48 #define MV88E6352_G1_VTU_FID 0x02
49 #define MV88E6352_G1_VTU_FID_MASK 0x0fff
51 /* Offset 0x03: VTU SID Register */
52 #define MV88E6352_G1_VTU_SID 0x03
53 #define MV88E6352_G1_VTU_SID_MASK 0x3f
55 /* Offset 0x04: Switch Global Control Register */
56 #define MV88E6XXX_G1_CTL1 0x04
57 #define MV88E6XXX_G1_CTL1_SW_RESET 0x8000
58 #define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000
59 #define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
60 #define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
61 #define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
62 #define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
63 #define MV88E6393X_G1_CTL1_DEVICE2_EN 0x0200
64 #define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
65 #define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
66 #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020
67 #define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010
68 #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008
69 #define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004
70 #define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002
71 #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001
73 /* Offset 0x05: VTU Operation Register */
74 #define MV88E6XXX_G1_VTU_OP 0x05
75 #define MV88E6XXX_G1_VTU_OP_BUSY 0x8000
76 #define MV88E6XXX_G1_VTU_OP_MASK 0x7000
77 #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
78 #define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
79 #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000
80 #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000
81 #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000
82 #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000
83 #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000
86 #define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf
88 /* Offset 0x06: VTU VID Register */
89 #define MV88E6XXX_G1_VTU_VID 0x06
90 #define MV88E6XXX_G1_VTU_VID_MASK 0x0fff
91 #define MV88E6390_G1_VTU_VID_PAGE 0x2000
92 #define MV88E6XXX_G1_VTU_VID_VALID 0x1000
94 /* Offset 0x07: VTU/STU Data Register 1
95 * Offset 0x08: VTU/STU Data Register 2
96 * Offset 0x09: VTU/STU Data Register 3
98 #define MV88E6XXX_G1_VTU_DATA1 0x07
99 #define MV88E6XXX_G1_VTU_DATA2 0x08
100 #define MV88E6XXX_G1_VTU_DATA3 0x09
101 #define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003
102 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000
103 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001
104 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002
105 #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003
106 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000
107 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001
108 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002
109 #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003
111 /* Offset 0x0A: ATU Control Register */
112 #define MV88E6XXX_G1_ATU_CTL 0x0a
113 #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008
114 #define MV88E6161_G1_ATU_CTL_HASH_MASK 0x0003
116 /* Offset 0x0B: ATU Operation Register */
117 #define MV88E6XXX_G1_ATU_OP 0x0b
118 #define MV88E6XXX_G1_ATU_OP_BUSY 0x8000
119 #define MV88E6XXX_G1_ATU_OP_MASK 0x7000
120 #define MV88E6XXX_G1_ATU_OP_NOOP 0x0000
121 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000
122 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000
123 #define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000
124 #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000
125 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000
126 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000
127 #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000
133 /* Offset 0x0C: ATU Data Register */
134 #define MV88E6XXX_G1_ATU_DATA 0x0c
135 #define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000
136 #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0
137 #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
138 #define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f
139 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED 0x0000
140 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST 0x0001
141 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2 0x0002
142 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3 0x0003
143 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4 0x0004
144 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5 0x0005
145 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6 0x0006
146 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST 0x0007
147 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY 0x0008
148 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO 0x0009
149 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL 0x000a
150 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO 0x000b
151 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT 0x000c
152 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO 0x000d
153 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e
154 #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO 0x000f
155 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED 0x0000
156 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY 0x0004
157 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL 0x0005
158 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT 0x0006
159 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007
160 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO 0x000c
161 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO 0x000d
162 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO 0x000e
163 #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO 0x000f
165 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
166 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
167 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
169 #define MV88E6XXX_G1_ATU_MAC01 0x0d
170 #define MV88E6XXX_G1_ATU_MAC23 0x0e
171 #define MV88E6XXX_G1_ATU_MAC45 0x0f
173 /* Offset 0x10: IP-PRI Mapping Register 0
174 * Offset 0x11: IP-PRI Mapping Register 1
175 * Offset 0x12: IP-PRI Mapping Register 2
176 * Offset 0x13: IP-PRI Mapping Register 3
177 * Offset 0x14: IP-PRI Mapping Register 4
178 * Offset 0x15: IP-PRI Mapping Register 5
179 * Offset 0x16: IP-PRI Mapping Register 6
180 * Offset 0x17: IP-PRI Mapping Register 7
182 #define MV88E6XXX_G1_IP_PRI_0 0x10
183 #define MV88E6XXX_G1_IP_PRI_1 0x11
184 #define MV88E6XXX_G1_IP_PRI_2 0x12
185 #define MV88E6XXX_G1_IP_PRI_3 0x13
186 #define MV88E6XXX_G1_IP_PRI_4 0x14
187 #define MV88E6XXX_G1_IP_PRI_5 0x15
188 #define MV88E6XXX_G1_IP_PRI_6 0x16
189 #define MV88E6XXX_G1_IP_PRI_7 0x17
191 /* Offset 0x18: IEEE-PRI Register */
192 #define MV88E6XXX_G1_IEEE_PRI 0x18
194 /* Offset 0x19: Core Tag Type */
195 #define MV88E6185_G1_CORE_TAG_TYPE 0x19
197 /* Offset 0x1A: Monitor Control */
198 #define MV88E6185_G1_MONITOR_CTL 0x1a
199 #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000
200 #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00
201 #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0
202 #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0
203 #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f
205 /* Offset 0x1A: Monitor & MGMT Control Register */
206 #define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a
207 #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000
208 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00
209 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO 0x0000
210 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI 0x0100
211 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO 0x0200
212 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI 0x0300
213 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
214 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
215 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
216 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI 0x00e0
217 #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
219 /* Offset 0x1C: Global Control 2 */
220 #define MV88E6XXX_G1_CTL2 0x1c
221 #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
222 #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
223 #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
224 #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000
225 #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000
226 #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000
227 #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000
228 #define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000
229 #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000
230 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000
231 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000
232 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000
233 #define MV88E6085_G1_CTL2_DA_CHECK 0x4000
234 #define MV88E6085_G1_CTL2_P10RM 0x2000
235 #define MV88E6085_G1_CTL2_RM_ENABLE 0x1000
236 #define MV88E6352_G1_CTL2_DA_CHECK 0x0800
237 #define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700
238 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000
239 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100
240 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200
241 #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300
242 #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600
243 #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700
244 #define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0
245 #define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040
246 #define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080
247 #define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060
248 #define MV88E6390_G1_CTL2_CTR_MODE 0x0020
249 #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
251 /* Offset 0x1D: Stats Operation Register */
252 #define MV88E6XXX_G1_STATS_OP 0x1d
253 #define MV88E6XXX_G1_STATS_OP_BUSY 0x8000
254 #define MV88E6XXX_G1_STATS_OP_NOP 0x0000
255 #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000
256 #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000
257 #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000
258 #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000
259 #define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400
260 #define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800
261 #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00
262 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200
263 #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400
265 /* Offset 0x1E: Stats Counter Register Bytes 3 & 2
266 * Offset 0x1F: Stats Counter Register Bytes 1 & 0
268 #define MV88E6XXX_G1_STATS_COUNTER_32 0x1e
269 #define MV88E6XXX_G1_STATS_COUNTER_01 0x1f