133 	chip->g1_irq.masked |= (1 << n);  in mv88e6xxx_g1_irq_mask()
141 	chip->g1_irq.masked &= ~(1 << n);  in mv88e6xxx_g1_irq_unmask()
161 		for (n = 0; n < chip->g1_irq.nirqs; ++n) {  in mv88e6xxx_g1_irq_thread_work()
163 				sub_irq = irq_find_mapping(chip->g1_irq.domain,  in mv88e6xxx_g1_irq_thread_work()
179 		ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);  in mv88e6xxx_g1_irq_thread_work()
203 	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);  in mv88e6xxx_g1_irq_bus_sync_unlock()
212 	reg |= (~chip->g1_irq.masked & mask);  in mv88e6xxx_g1_irq_bus_sync_unlock()
237 	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);  in mv88e6xxx_g1_irq_domain_map()
255 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);  in mv88e6xxx_g1_irq_free_common()
258 	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {  in mv88e6xxx_g1_irq_free_common()
259 		virq = irq_find_mapping(chip->g1_irq.domain, irq);  in mv88e6xxx_g1_irq_free_common()
263 	irq_domain_remove(chip->g1_irq.domain);  in mv88e6xxx_g1_irq_free_common()
284 	chip->g1_irq.nirqs = chip->info->g1_irqs;  in mv88e6xxx_g1_irq_setup_common()
285 	chip->g1_irq.domain = irq_domain_add_simple(  in mv88e6xxx_g1_irq_setup_common()
286 		NULL, chip->g1_irq.nirqs, 0,  in mv88e6xxx_g1_irq_setup_common()
288 	if (!chip->g1_irq.domain)  in mv88e6xxx_g1_irq_setup_common()
291 	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)  in mv88e6xxx_g1_irq_setup_common()
292 		irq_create_mapping(chip->g1_irq.domain, irq);  in mv88e6xxx_g1_irq_setup_common()
294 	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;  in mv88e6xxx_g1_irq_setup_common()
295 	chip->g1_irq.masked = ~0;  in mv88e6xxx_g1_irq_setup_common()
301 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);  in mv88e6xxx_g1_irq_setup_common()
315 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);  in mv88e6xxx_g1_irq_setup_common()
320 		virq = irq_find_mapping(chip->g1_irq.domain, irq);  in mv88e6xxx_g1_irq_setup_common()
324 	irq_domain_remove(chip->g1_irq.domain);  in mv88e6xxx_g1_irq_setup_common()