Lines Matching +full:0 +full:x409
13 #define MT7530_ALL_MEMBERS 0xff
19 ID_MT7530 = 0,
26 #define TRGMII_BASE(x) (0x10000 + (x))
29 #define ETHSYS_CLKCFG0 0x2c
32 #define SYSC_REG_RSTCTRL 0x34
36 #define MT7530_MFC 0x10
37 #define BC_FFP(x) (((x) & 0xff) << 24)
38 #define BC_FFP_MASK BC_FFP(~0)
39 #define UNM_FFP(x) (((x) & 0xff) << 16)
40 #define UNM_FFP_MASK UNM_FFP(~0)
41 #define UNU_FFP(x) (((x) & 0xff) << 8)
42 #define UNU_FFP_MASK UNU_FFP(~0)
45 #define CPU_MASK (0xf << 4)
47 #define MIRROR_PORT(x) ((x) & 0x7)
48 #define MIRROR_MASK 0x7
51 #define MT7531_CFC 0x4
56 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
66 #define MT753X_BPC 0x24
67 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
78 #define MT7530_ATA1 0x74
79 #define STATIC_EMP 0
81 #define MT7530_ATA2 0x78
83 #define ATA2_FID(x) (((x) & 0x7) << 12)
86 #define MT7530_ATWD 0x7c
89 #define MT7530_ATC 0x80
90 #define ATC_HASH (((x) & 0xfff) << 16)
95 #define ATC_MAT(x) (((x) & 0xf) << 8)
96 #define ATC_MAT_MACTAB ATC_MAT(0)
99 MT7530_FDB_READ = 0,
107 #define MT7530_TSRA1 0x84
111 #define MAC_BYTE_3 0
112 #define MAC_BYTE_MASK 0xff
114 #define MT7530_TSRA2 0x88
117 #define CVID 0
118 #define CVID_MASK 0xfff
120 #define MT7530_ATRD 0x8C
122 #define AGE_TIMER_MASK 0xff
124 #define PORT_MAP_MASK 0xff
126 #define ENT_STATUS_MASK 0x3
129 #define MT7530_VTCR 0x90
132 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
133 #define VTCR_VID ((x) & 0xfff)
139 MT7530_VTCR_RD_VID = 0,
144 #define MT7530_VAWD1 0x94
153 #define PORT_MEM(x) (((x) & 0xff) << 16)
155 #define FID(x) (((x) & 0x7) << 1)
157 #define VLAN_VALID BIT(0)
159 #define PORT_MEM_MASK 0xff
162 FID_STANDALONE = 0,
166 #define MT7530_VAWD2 0x98
168 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
172 MT7530_VLAN_EGRESS_UNTAG = 0,
178 #define MT7530_AAC 0xa0
183 #define AGE_CNT_MAX 0xff
186 #define AGE_UNIT_MASK GENMASK(11, 0)
187 #define AGE_UNIT_MAX 0xfff
191 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
192 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
193 #define FID_PST_MASK(fid) FID_PST(fid, 0x3)
196 MT7530_STP_DISABLED = 0,
204 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
207 #define PORT_VLAN(x) ((x) & 0x3)
211 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
225 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
226 #define PORT_PRI(x) (((x) & 0x7) << 24)
227 #define EG_TAG(x) (((x) & 0x3) << 28)
228 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
229 #define PCR_MATRIX_CLR PCR_MATRIX(0)
233 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
237 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
239 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
241 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
243 #define ACC_FRM_MASK GENMASK(1, 0)
246 MT7530_VLAN_EG_DISABLED = 0,
251 MT7530_VLAN_USER = 0,
256 MT7530_VLAN_ACC_ALL = 0,
261 #define STAG_VPID (((x) & 0xffff) << 16)
264 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
265 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
266 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
267 #define G0_PORT_VID_DEF G0_PORT_VID(0)
270 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
271 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
286 #define PMCR_FORCE_LNK BIT(0)
315 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
316 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
317 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
322 #define LPI_MODE_EN BIT(0)
324 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
331 #define PMSR_SPEED_10 0x00
334 #define PMSR_LINK BIT(0)
337 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
340 #define MT7530_GMACCR 0x30e0
343 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
344 #define MAX_RX_PKT_LEN_1522 0x0
345 #define MAX_RX_PKT_LEN_1536 0x1
346 #define MAX_RX_PKT_LEN_1552 0x2
347 #define MAX_RX_PKT_LEN_JUMBO 0x3
350 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
351 #define MT7530_MIB_CCR 0x4fe0
368 #define MT7531_SGMII_REG_BASE 0x5000
370 ((p) - 5) * 0x1000 + (r))
373 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
379 #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
380 #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
381 #define MT7531_SGMII_TX_CONFIG BIT(0)
384 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
391 #define MT7531_SGMII_FORCE_SPEED_10 0
395 MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
396 MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
400 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
404 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
406 #define MT7531_RG_TPHY_SPEED_1_25G 0x0
410 #define MT7530_SYS_CTRL 0x7000
413 #define SYS_CTRL_REG_RST BIT(0)
416 #define MT7530_SYS_INT_EN 0x7008
419 #define MT7530_SYS_INT_STS 0x700c
422 #define MT7531_PHY_IAC 0x701C
424 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
425 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
426 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
427 #define MT7531_MDIO_ST_MASK (0x3 << 16)
428 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
429 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
430 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
431 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
432 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
433 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
436 MT7531_MDIO_ADDR = 0,
444 MT7531_MDIO_ST_CL45 = 0,
460 #define MT7531_CLKGEN_CTRL 0x7500
461 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
463 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
467 #define GP_MODE(x) (((x) & 0x3) << 1)
469 #define GP_CLK_EN BIT(0)
472 MT7531_GP_MODE_RGMII = 0,
478 MT7531_CLK_SKEW_NO_CHG = 0,
485 #define MT7530_HWTRAP 0x7800
491 #define MT7531_HWTRAP 0x7800
494 #define HWTRAP_XTAL_FSEL_40MHZ 0
502 #define MT7530_MHWTRAP 0x7804
512 #define MT7530_TOP_SIG_CTRL 0x7808
515 #define MT7531_TOP_SIG_SR 0x780c
517 #define PAD_MCM_SMI_EN BIT(0)
519 #define MT7530_IO_DRV_CR 0x7810
520 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
521 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
523 #define MT7531_CHIP_REV 0x781C
525 #define MT7531_PLLGP_EN 0x7820
528 #define SW_PLLGP BIT(0)
530 #define MT7530_P6ECR 0x7830
531 #define P6_INTF_MODE_MASK 0x3
532 #define P6_INTF_MODE(x) ((x) & 0x3)
534 #define MT7531_PLLGP_CR0 0x78a8
537 #define RG_COREPLL_POSDIV_M 0x3800000
539 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
540 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
543 #define MT7531_ANA_PLLGP_CR2 0x78b0
544 #define MT7531_ANA_PLLGP_CR5 0x78bc
547 #define MT7530_TRGMII_RCK_CTRL 0x7a00
550 #define DQSI1_TAP_MASK (0x7f << 8)
551 #define DQSI0_TAP_MASK 0x7f
552 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
553 #define DQSI0_TAP(x) ((x) & 0x7f)
555 #define MT7530_TRGMII_RCK_RTT 0x7a04
559 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
562 #define RD_TAP_MASK 0x7f
563 #define RD_TAP(x) ((x) & 0x7f)
565 #define MT7530_TRGMII_TXCTRL 0x7a40
570 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
571 #define TD_DM_DRVP(x) ((x) & 0xf)
572 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
574 #define MT7530_TRGMII_TCK_CTRL 0x7a78
575 #define TCK_TAP(x) (((x) & 0xf) << 8)
577 #define MT7530_P5RGMIIRXCR 0x7b00
579 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
581 #define MT7530_P5RGMIITXCR 0x7b04
582 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
585 #define MT7531_GPIO_MODE0 0x7c0c
586 #define MT7531_GPIO0_MASK GENMASK(3, 0)
589 #define MT7531_GPIO_MODE1 0x7c10
597 * [ 2: 0] port 0
604 /* LED enable, 0: Disable, 1: Enable (Default) */
605 #define MT7530_LED_EN 0x7d00
606 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
607 #define MT7530_LED_IO_MODE 0x7d04
608 /* GPIO direction, 0: Input, 1: Output */
609 #define MT7530_LED_GPIO_DIR 0x7d10
610 /* GPIO output enable, 0: Disable, 1: Enable */
611 #define MT7530_LED_GPIO_OE 0x7d14
612 /* GPIO value, 0: Low, 1: High */
613 #define MT7530_LED_GPIO_DATA 0x7d18
615 #define MT7530_CREV 0x7ffc
617 #define MT7530_ID 0x7530
619 #define MT7531_CREV 0x781C
620 #define CHIP_REV_M 0x0f
621 #define MT7531_ID 0x7531
624 #define CORE_PLL_GROUP2 0x401
628 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
630 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
631 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
633 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
635 #define CORE_PLL_GROUP4 0x403
642 #define MT753X_CTRL_PHY_ADDR 0
644 #define CORE_PLL_GROUP5 0x404
645 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
647 #define CORE_PLL_GROUP6 0x405
648 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
650 #define CORE_PLL_GROUP7 0x406
653 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
656 #define CORE_PLL_GROUP10 0x409
657 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
659 #define CORE_PLL_GROUP11 0x40a
660 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
662 #define CORE_GSWPLL_GRP1 0x40d
663 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
664 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
669 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
671 #define CORE_GSWPLL_GRP2 0x40e
672 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
673 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
675 #define CORE_TRGMII_GSW_CLK_CG 0x410
676 #define REG_GSWCK_EN BIT(0)
717 P5_DISABLED = 0,