Lines Matching refs:mt7530_write

233 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)  in mt7530_write()  function
312 mt7530_write(priv, MT7530_ATC, val); in mt7530_fdb_cmd()
388 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); in mt7530_fdb_write()
444 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), in mt7530_pad_clk_setup()
525 mt7530_write(priv, MT7531_PLLGP_EN, val); in mt7531_pad_setup()
530 mt7530_write(priv, MT7531_PLLGP_EN, val); in mt7531_pad_setup()
534 mt7530_write(priv, MT7531_PLLGP_CR0, val); in mt7531_pad_setup()
539 mt7530_write(priv, MT7531_PLLGP_EN, val); in mt7531_pad_setup()
545 mt7530_write(priv, MT7531_PLLGP_CR0, val); in mt7531_pad_setup()
553 mt7530_write(priv, MT7531_PLLGP_CR0, val); in mt7531_pad_setup()
559 mt7530_write(priv, MT7531_PLLGP_CR0, val); in mt7531_pad_setup()
566 mt7530_write(priv, MT7531_PLLGP_CR0, val); in mt7531_pad_setup()
573 mt7530_write(priv, MT7531_PLLGP_CR0, val); in mt7531_pad_setup()
576 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); in mt7531_pad_setup()
579 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); in mt7531_pad_setup()
584 mt7530_write(priv, MT7531_PLLGP_CR0, val); in mt7531_pad_setup()
588 mt7530_write(priv, MT7531_PLLGP_EN, val); in mt7531_pad_setup()
599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); in mt7530_mib_reset()
600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); in mt7530_mib_reset()
918 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); in mt7530_set_ageing_time()
946 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); in mt7530_setup_port5()
966 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); in mt7530_setup_port5()
975 mt7530_write(priv, MT7530_P5RGMIITXCR, in mt7530_setup_port5()
979 mt7530_write(priv, MT7530_IO_DRV_CR, in mt7530_setup_port5()
983 mt7530_write(priv, MT7530_MHWTRAP, val); in mt7530_setup_port5()
1008 mt7530_write(priv, MT7530_PVC_P(port), in mt753x_cpu_port_enable()
1022 mt7530_write(priv, MT7530_PCR_P(port), in mt753x_cpu_port_enable()
1265 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), in mt7530_port_set_vlan_unaware()
1267 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG in mt7530_port_set_vlan_unaware()
1470 mt7530_write(priv, MT7530_VTCR, val); in mt7530_vlan_cmd()
1523 mt7530_write(priv, MT7530_VAWD1, val); in mt7530_hw_vlan_add()
1568 mt7530_write(priv, MT7530_VAWD1, val); in mt7530_hw_vlan_del()
1570 mt7530_write(priv, MT7530_VAWD1, 0); in mt7530_hw_vlan_del()
1571 mt7530_write(priv, MT7530_VAWD2, 0); in mt7530_hw_vlan_del()
1606 mt7530_write(priv, MT7530_VAWD1, val); in mt7530_setup_vlan0()
1725 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1735 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_add()
1754 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_del()
1759 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
1855 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); in mt7530_setup_gpio()
1856 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); in mt7530_setup_gpio()
1857 mt7530_write(priv, MT7530_LED_IO_MODE, 0); in mt7530_setup_gpio()
2147 mt7530_write(priv, MT7530_SYS_CTRL, in mt7530_setup()
2155 mt7530_write(priv, MT7530_MHWTRAP, val); in mt7530_setup()
2290 mt7530_write(priv, MT7530_SYS_CTRL, in mt7531_setup()
2518 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); in mt7531_rgmii_setup()
2577 mt7530_write(priv, MT7531_SGMII_MODE(port), val); in mt7531_sgmii_link_up_force()
2603 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); in mt7531_sgmii_setup_mode_force()
2614 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); in mt7531_sgmii_setup_mode_force()
2642 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); in mt7531_sgmii_setup_mode_an()
2656 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); in mt7531_sgmii_restart_an()
2767 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); in mt753x_phylink_mac_config()
2891 mt7530_write(priv, MT7530_PMCR_P(port), in mt7531_cpu_port_config()