Lines Matching +full:mt7621 +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/gpio/consumer.h>
22 #include <linux/gpio/driver.h>
80 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
84 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
89 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
94 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
99 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
103 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
112 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
116 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
121 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
126 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_write_mmd_indirect()
131 ret = bus->write(bus, 0, MII_MMD_DATA, data); in core_write_mmd_indirect()
134 dev_err(&bus->dev, in core_write_mmd_indirect()
142 struct mii_bus *bus = priv->bus; in core_write()
144 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in core_write()
148 mutex_unlock(&bus->mdio_lock); in core_write()
154 struct mii_bus *bus = priv->bus; in core_rmw()
157 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in core_rmw()
164 mutex_unlock(&bus->mdio_lock); in core_rmw()
182 struct mii_bus *bus = priv->bus; in mt7530_mii_write()
192 ret = bus->write(bus, 0x1f, 0x1f, page); in mt7530_mii_write()
196 ret = bus->write(bus, 0x1f, r, lo); in mt7530_mii_write()
200 ret = bus->write(bus, 0x1f, 0x10, hi); in mt7530_mii_write()
203 dev_err(&bus->dev, in mt7530_mii_write()
211 struct mii_bus *bus = priv->bus; in mt7530_mii_read()
219 ret = bus->write(bus, 0x1f, 0x1f, page); in mt7530_mii_read()
221 dev_err(&bus->dev, in mt7530_mii_read()
226 lo = bus->read(bus, 0x1f, r); in mt7530_mii_read()
227 hi = bus->read(bus, 0x1f, 0x10); in mt7530_mii_read()
235 struct mii_bus *bus = priv->bus; in mt7530_write()
237 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_write()
241 mutex_unlock(&bus->mdio_lock); in mt7530_write()
247 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
253 struct mii_bus *bus = p->priv->bus; in _mt7530_read()
256 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in _mt7530_read()
258 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
260 mutex_unlock(&bus->mdio_lock); in _mt7530_read()
278 struct mii_bus *bus = priv->bus; in mt7530_rmw()
281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_rmw()
288 mutex_unlock(&bus->mdio_lock); in mt7530_rmw()
318 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
327 return -EINVAL; in mt7530_fdb_cmd()
345 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
349 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
350 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
351 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
352 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
353 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
354 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
355 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
356 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
357 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
358 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
395 struct mt7530_priv *priv = ds->priv; in mt7530_pad_clk_setup()
401 dev_err(priv->dev, in mt7530_pad_clk_setup()
404 return -EINVAL; in mt7530_pad_clk_setup()
415 if (priv->id == ID_MT7621) { in mt7530_pad_clk_setup()
429 dev_err(priv->dev, "xMII interface %d not supported\n", in mt7530_pad_clk_setup()
431 return -EINVAL; in mt7530_pad_clk_setup()
504 struct mt7530_priv *priv = ds->priv; in mt7531_pad_setup()
597 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
605 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read()
611 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write()
618 struct mii_bus *bus = priv->bus; in mt7531_ind_c45_phy_read()
625 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c45_phy_read()
630 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
641 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
652 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
658 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c45_phy_read()
667 struct mii_bus *bus = priv->bus; in mt7531_ind_c45_phy_write()
674 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c45_phy_write()
679 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
690 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
701 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
706 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c45_phy_write()
714 struct mii_bus *bus = priv->bus; in mt7531_ind_c22_phy_read()
721 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c22_phy_read()
726 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
738 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
744 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c22_phy_read()
753 struct mii_bus *bus = priv->bus; in mt7531_ind_c22_phy_write()
760 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c22_phy_write()
765 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
777 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
782 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c22_phy_write()
826 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read()
828 return priv->info->phy_read(priv, port, regnum); in mt753x_phy_read()
834 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write()
836 return priv->info->phy_write(priv, port, regnum, val); in mt753x_phy_write()
857 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
864 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; in mt7530_get_ethtool_stats()
867 if (mib->size == 2) { in mt7530_get_ethtool_stats()
886 struct mt7530_priv *priv = ds->priv; in mt7530_set_ageing_time()
889 unsigned int error = -1; in mt7530_set_ageing_time()
895 return -ERANGE; in mt7530_set_ageing_time()
899 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; in mt7530_set_ageing_time()
902 unsigned int tmp_error = secs - in mt7530_set_ageing_time()
925 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
929 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
936 switch (priv->p5_intf_sel) { in mt7530_setup_port5()
938 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ in mt7530_setup_port5()
942 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ in mt7530_setup_port5()
949 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ in mt7530_setup_port5()
956 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", in mt7530_setup_port5()
957 priv->p5_intf_sel); in mt7530_setup_port5()
969 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
985 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", in mt7530_setup_port5()
986 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); in mt7530_setup_port5()
988 priv->p5_interface = interface; in mt7530_setup_port5()
991 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
997 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
1001 if (priv->info->cpu_port_config) { in mt753x_cpu_port_enable()
1002 ret = priv->info->cpu_port_config(ds, port); in mt753x_cpu_port_enable()
1016 if (priv->id == ID_MT7621) in mt753x_cpu_port_enable()
1023 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
1036 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
1038 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
1044 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); in mt7530_port_enable()
1045 priv->ports[port].enable = true; in mt7530_port_enable()
1047 priv->ports[port].pm); in mt7530_port_enable()
1050 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1058 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1060 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1065 priv->ports[port].enable = false; in mt7530_port_disable()
1070 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1076 struct mt7530_priv *priv = ds->priv; in mt7530_port_change_mtu()
1077 struct mii_bus *bus = priv->bus; in mt7530_port_change_mtu()
1088 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_port_change_mtu()
1109 mutex_unlock(&bus->mdio_lock); in mt7530_port_change_mtu()
1123 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1156 return -EINVAL; in mt7530_port_pre_bridge_flags()
1166 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_flags()
1191 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1195 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1203 if (dsa_to_port(ds, i)->bridge_dev != bridge) in mt7530_port_bridge_join()
1205 if (priv->ports[i].enable) in mt7530_port_bridge_join()
1208 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); in mt7530_port_bridge_join()
1215 if (priv->ports[port].enable) in mt7530_port_bridge_join()
1218 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); in mt7530_port_bridge_join()
1224 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1232 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1236 /* This is called after .port_bridge_leave when leaving a VLAN-aware in mt7530_port_set_vlan_unaware()
1239 if (dsa_to_port(ds, port)->bridge_dev) in mt7530_port_set_vlan_unaware()
1266 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1275 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1284 G0_PORT_VID(priv->ports[port].pvid)); in mt7530_port_set_vlan_aware()
1287 if (!priv->ports[port].pvid) in mt7530_port_set_vlan_aware()
1304 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1307 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1315 if (dsa_to_port(ds, i)->bridge_dev != bridge) in mt7530_port_bridge_leave()
1317 if (priv->ports[i].enable) in mt7530_port_bridge_leave()
1320 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); in mt7530_port_bridge_leave()
1327 if (priv->ports[port].enable) in mt7530_port_bridge_leave()
1330 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); in mt7530_port_bridge_leave()
1333 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_bridge_leave()
1339 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1346 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1350 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1351 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1353 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1362 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1366 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1367 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1369 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1378 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1384 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1400 } while (--cnt && in mt7530_port_fdb_dump()
1404 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1413 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_add()
1414 const u8 *addr = mdb->addr; in mt7530_port_mdb_add()
1415 u16 vid = mdb->vid; in mt7530_port_mdb_add()
1419 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_add()
1427 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_mdb_add()
1430 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_add()
1439 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_del()
1440 const u8 *addr = mdb->addr; in mt7530_port_mdb_del()
1441 u16 vid = mdb->vid; in mt7530_port_mdb_del()
1445 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_del()
1453 mt7530_fdb_write(priv, vid, port_mask, addr, -1, in mt7530_port_mdb_del()
1457 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_del()
1476 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1482 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1483 return -EINVAL; in mt7530_vlan_cmd()
1494 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1497 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1515 new_members = entry->old_members | BIT(entry->port) | in mt7530_hw_vlan_add()
1528 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : in mt7530_hw_vlan_add()
1531 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1532 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1552 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1556 dev_err(priv->dev, in mt7530_hw_vlan_del()
1587 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1616 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1617 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1619 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1621 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1624 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); in mt7530_port_vlan_add()
1627 priv->ports[port].pvid = vlan->vid; in mt7530_port_vlan_add()
1637 G0_PORT_VID(vlan->vid)); in mt7530_port_vlan_add()
1638 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_add()
1640 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_add()
1642 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_add()
1651 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1661 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1663 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1666 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, in mt7530_port_vlan_del()
1672 if (priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_del()
1673 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_del()
1675 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_del()
1685 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
1706 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
1711 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
1712 return -EEXIST; in mt753x_port_mirror_add()
1714 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
1717 monitor_port = mt753x_mirror_port_get(priv->id, val); in mt753x_port_mirror_add()
1718 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
1719 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
1720 return -EEXIST; in mt753x_port_mirror_add()
1722 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
1723 val &= ~MT753X_MIRROR_MASK(priv->id); in mt753x_port_mirror_add()
1724 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
1725 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1730 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
1733 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
1743 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
1747 if (mirror->ingress) { in mt753x_port_mirror_del()
1749 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
1752 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
1756 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
1757 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
1758 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
1759 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
1774 /* Map GPIO offset to register bit in mt7530_gpio_to_bit()
1775 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 in mt7530_gpio_to_bit()
1776 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 in mt7530_gpio_to_bit()
1777 * [10: 8] port 2 LED 0..2 as GPIO 6..8 in mt7530_gpio_to_bit()
1778 * [14:12] port 3 LED 0..2 as GPIO 9..11 in mt7530_gpio_to_bit()
1779 * [18:16] port 4 LED 0..2 as GPIO 12..14 in mt7530_gpio_to_bit()
1848 struct device *dev = priv->dev; in mt7530_setup_gpio()
1853 return -ENOMEM; in mt7530_setup_gpio()
1859 gc->label = "mt7530"; in mt7530_setup_gpio()
1860 gc->parent = dev; in mt7530_setup_gpio()
1861 gc->owner = THIS_MODULE; in mt7530_setup_gpio()
1862 gc->get_direction = mt7530_gpio_get_direction; in mt7530_setup_gpio()
1863 gc->direction_input = mt7530_gpio_direction_input; in mt7530_setup_gpio()
1864 gc->direction_output = mt7530_gpio_direction_output; in mt7530_setup_gpio()
1865 gc->get = mt7530_gpio_get; in mt7530_setup_gpio()
1866 gc->set = mt7530_gpio_set; in mt7530_setup_gpio()
1867 gc->base = -1; in mt7530_setup_gpio()
1868 gc->ngpio = 15; in mt7530_setup_gpio()
1869 gc->can_sleep = true; in mt7530_setup_gpio()
1883 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_irq_thread_fn()
1886 mutex_unlock(&priv->bus->mdio_lock); in mt7530_irq_thread_fn()
1892 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_irq_thread_fn()
1906 priv->irq_enable &= ~BIT(d->hwirq); in mt7530_irq_mask()
1914 priv->irq_enable |= BIT(d->hwirq); in mt7530_irq_unmask()
1922 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_irq_bus_lock()
1930 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7530_irq_bus_sync_unlock()
1931 mutex_unlock(&priv->bus->mdio_lock); in mt7530_irq_bus_sync_unlock()
1946 irq_set_chip_data(irq, domain->host_data); in mt7530_irq_map()
1962 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio_irq()
1966 if (BIT(p) & ds->phys_mii_mask) { in mt7530_setup_mdio_irq()
1969 irq = irq_create_mapping(priv->irq_domain, p); in mt7530_setup_mdio_irq()
1970 ds->slave_mii_bus->irq[p] = irq; in mt7530_setup_mdio_irq()
1978 struct device *dev = priv->dev; in mt7530_setup_irq()
1979 struct device_node *np = dev->of_node; in mt7530_setup_irq()
1982 if (!of_property_read_bool(np, "interrupt-controller")) { in mt7530_setup_irq()
1987 priv->irq = of_irq_get(np, 0); in mt7530_setup_irq()
1988 if (priv->irq <= 0) { in mt7530_setup_irq()
1989 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); in mt7530_setup_irq()
1990 return priv->irq ? : -EINVAL; in mt7530_setup_irq()
1993 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
1995 if (!priv->irq_domain) { in mt7530_setup_irq()
1997 return -ENOMEM; in mt7530_setup_irq()
2001 if (priv->id != ID_MT7531) in mt7530_setup_irq()
2004 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, in mt7530_setup_irq()
2007 irq_domain_remove(priv->irq_domain); in mt7530_setup_irq()
2021 if (BIT(p) & priv->ds->phys_mii_mask) { in mt7530_free_mdio_irq()
2024 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_free_mdio_irq()
2033 free_irq(priv->irq, priv); in mt7530_free_irq_common()
2034 irq_domain_remove(priv->irq_domain); in mt7530_free_irq_common()
2047 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio()
2048 struct device *dev = priv->dev; in mt7530_setup_mdio()
2055 return -ENOMEM; in mt7530_setup_mdio()
2057 ds->slave_mii_bus = bus; in mt7530_setup_mdio()
2058 bus->priv = priv; in mt7530_setup_mdio()
2059 bus->name = KBUILD_MODNAME "-mii"; in mt7530_setup_mdio()
2060 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); in mt7530_setup_mdio()
2061 bus->read = mt753x_phy_read; in mt7530_setup_mdio()
2062 bus->write = mt753x_phy_write; in mt7530_setup_mdio()
2063 bus->parent = dev; in mt7530_setup_mdio()
2064 bus->phy_mask = ~ds->phys_mii_mask; in mt7530_setup_mdio()
2066 if (priv->irq) in mt7530_setup_mdio()
2072 if (priv->irq) in mt7530_setup_mdio()
2082 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
2095 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; in mt7530_setup()
2096 ds->assisted_learning_on_cpu_port = true; in mt7530_setup()
2097 ds->mtu_enforcement_ingress = true; in mt7530_setup()
2099 if (priv->id == ID_MT7530) { in mt7530_setup()
2100 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
2101 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
2103 dev_err(priv->dev, in mt7530_setup()
2108 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
2109 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
2111 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
2117 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
2120 if (priv->mcm) { in mt7530_setup()
2121 reset_control_assert(priv->rstc); in mt7530_setup()
2123 reset_control_deassert(priv->rstc); in mt7530_setup()
2125 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
2127 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
2135 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
2142 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
2143 return -ENODEV; in mt7530_setup()
2157 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7530_setup()
2186 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7530_setup()
2192 priv->p5_intf_sel = P5_DISABLED; in mt7530_setup()
2196 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7530_setup()
2197 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); in mt7530_setup()
2198 if (ret && ret != -ENODEV) in mt7530_setup()
2204 "mediatek,eth-mac")) in mt7530_setup()
2211 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
2215 if (phy_node->parent == priv->dev->of_node->parent) { in mt7530_setup()
2217 if (ret && ret != -ENODEV) { in mt7530_setup()
2221 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
2223 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; in mt7530_setup()
2225 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; in mt7530_setup()
2234 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { in mt7530_setup()
2254 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
2259 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
2262 if (priv->mcm) { in mt7531_setup()
2263 reset_control_assert(priv->rstc); in mt7531_setup()
2265 reset_control_deassert(priv->rstc); in mt7531_setup()
2267 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
2269 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
2277 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
2285 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
2286 return -ENODEV; in mt7531_setup()
2295 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; in mt7531_setup()
2297 /* Let ds->slave_mii_bus be able to access external phy. */ in mt7531_setup()
2303 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7531_setup()
2305 dev_dbg(ds->dev, "P5 support %s interface\n", in mt7531_setup()
2306 p5_intf_modes(priv->p5_intf_sel)); in mt7531_setup()
2312 priv->p5_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
2313 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
2363 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7531_setup()
2368 ds->assisted_learning_on_cpu_port = true; in mt7531_setup()
2369 ds->mtu_enforcement_ingress = true; in mt7531_setup()
2383 struct mt7530_priv *priv = ds->priv; in mt7530_phy_mode_supported()
2387 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt7530_phy_mode_supported()
2391 if (!phy_interface_mode_is_rgmii(state->interface) && in mt7530_phy_mode_supported()
2392 state->interface != PHY_INTERFACE_MODE_MII && in mt7530_phy_mode_supported()
2393 state->interface != PHY_INTERFACE_MODE_GMII) in mt7530_phy_mode_supported()
2397 if (state->interface != PHY_INTERFACE_MODE_RGMII && in mt7530_phy_mode_supported()
2398 state->interface != PHY_INTERFACE_MODE_TRGMII) in mt7530_phy_mode_supported()
2402 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, in mt7530_phy_mode_supported()
2412 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); in mt7531_is_rgmii_port()
2419 struct mt7530_priv *priv = ds->priv; in mt7531_phy_mode_supported()
2423 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt7531_phy_mode_supported()
2428 return phy_interface_mode_is_rgmii(state->interface); in mt7531_phy_mode_supported()
2431 if (state->interface != PHY_INTERFACE_MODE_SGMII && in mt7531_phy_mode_supported()
2432 !phy_interface_mode_is_8023z(state->interface)) in mt7531_phy_mode_supported()
2436 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, in mt7531_phy_mode_supported()
2448 struct mt7530_priv *priv = ds->priv; in mt753x_phy_mode_supported()
2450 return priv->info->phy_mode_supported(ds, port, state); in mt753x_phy_mode_supported()
2456 struct mt7530_priv *priv = ds->priv; in mt753x_pad_setup()
2458 return priv->info->pad_setup(ds, state->interface); in mt753x_pad_setup()
2465 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
2471 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
2483 dev_err(priv->dev, "RGMII mode is not available for port %d\n", in mt7531_rgmii_setup()
2485 return -EINVAL; in mt7531_rgmii_setup()
2515 return -EINVAL; in mt7531_rgmii_setup()
2546 struct mt7530_priv *priv = ds->priv; in mt7531_sgmii_link_up_force()
2591 return -EINVAL; in mt7531_sgmii_setup_mode_force()
2623 return -EINVAL; in mt7531_sgmii_setup_mode_an()
2649 struct mt7530_priv *priv = ds->priv; in mt7531_sgmii_restart_an()
2664 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2669 dev_err(priv->dev, "port %d is not a MAC port\n", port); in mt7531_mac_config()
2670 return -EINVAL; in mt7531_mac_config()
2679 phydev = dp->slave->phydev; in mt7531_mac_config()
2687 return -EINVAL; in mt7531_mac_config()
2691 return -EINVAL; in mt7531_mac_config()
2694 return -EINVAL; in mt7531_mac_config()
2701 struct mt7530_priv *priv = ds->priv; in mt753x_mac_config()
2703 return priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_mac_config()
2710 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_config()
2718 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt753x_phylink_mac_config()
2722 if (priv->p5_interface == state->interface) in mt753x_phylink_mac_config()
2728 if (priv->p5_intf_sel != P5_DISABLED) in mt753x_phylink_mac_config()
2729 priv->p5_interface = state->interface; in mt753x_phylink_mac_config()
2732 if (priv->p6_interface == state->interface) in mt753x_phylink_mac_config()
2740 priv->p6_interface = state->interface; in mt753x_phylink_mac_config()
2744 dev_err(ds->dev, "%s: unsupported %s port: %i\n", in mt753x_phylink_mac_config()
2745 __func__, phy_modes(state->interface), port); in mt753x_phylink_mac_config()
2750 state->interface != PHY_INTERFACE_MODE_SGMII) { in mt753x_phylink_mac_config()
2751 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", in mt753x_phylink_mac_config()
2760 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); in mt753x_phylink_mac_config()
2773 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_an_restart()
2775 if (!priv->info->mac_pcs_an_restart) in mt753x_phylink_mac_an_restart()
2778 priv->info->mac_pcs_an_restart(ds, port); in mt753x_phylink_mac_an_restart()
2785 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_down()
2794 struct mt7530_priv *priv = ds->priv; in mt753x_mac_pcs_link_up()
2796 if (!priv->info->mac_pcs_link_up) in mt753x_mac_pcs_link_up()
2799 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); in mt753x_mac_pcs_link_up()
2809 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_up()
2816 /* MT753x MAC works in 1G full duplex mode for all up-clocked in mt753x_phylink_mac_link_up()
2858 struct mt7530_priv *priv = ds->priv; in mt7531_cpu_port_config()
2870 priv->p5_interface = interface; in mt7531_cpu_port_config()
2877 priv->p6_interface = interface; in mt7531_cpu_port_config()
2880 return -EINVAL; in mt7531_cpu_port_config()
2892 PMCR_CPU_PORT_SETTING(priv->id)); in mt7531_cpu_port_config()
2910 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_validate()
2921 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_validate()
2923 if (state->interface != PHY_INTERFACE_MODE_NA && in mt753x_phylink_validate()
2931 if (state->interface != PHY_INTERFACE_MODE_TRGMII || in mt753x_phylink_validate()
2932 !phy_interface_mode_is_8023z(state->interface)) { in mt753x_phylink_validate()
2940 /* This switch only supports 1G full-duplex. */ in mt753x_phylink_validate()
2941 if (state->interface != PHY_INTERFACE_MODE_MII) in mt753x_phylink_validate()
2944 priv->info->mac_port_validate(ds, port, mask); in mt753x_phylink_validate()
2950 linkmode_and(state->advertising, state->advertising, mask); in mt753x_phylink_validate()
2962 struct mt7530_priv *priv = ds->priv; in mt7530_phylink_mac_link_state()
2966 return -EINVAL; in mt7530_phylink_mac_link_state()
2970 state->link = (pmsr & PMSR_LINK); in mt7530_phylink_mac_link_state()
2971 state->an_complete = state->link; in mt7530_phylink_mac_link_state()
2972 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_phylink_mac_link_state()
2976 state->speed = SPEED_10; in mt7530_phylink_mac_link_state()
2979 state->speed = SPEED_100; in mt7530_phylink_mac_link_state()
2982 state->speed = SPEED_1000; in mt7530_phylink_mac_link_state()
2985 state->speed = SPEED_UNKNOWN; in mt7530_phylink_mac_link_state()
2989 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_phylink_mac_link_state()
2991 state->pause |= MLO_PAUSE_RX; in mt7530_phylink_mac_link_state()
2993 state->pause |= MLO_PAUSE_TX; in mt7530_phylink_mac_link_state()
3006 state->link = !!(status & MT7531_SGMII_LINK_STATUS); in mt7531_sgmii_pcs_get_state_an()
3007 if (state->interface == PHY_INTERFACE_MODE_SGMII && in mt7531_sgmii_pcs_get_state_an()
3014 state->speed = SPEED_1000; in mt7531_sgmii_pcs_get_state_an()
3017 state->speed = SPEED_100; in mt7531_sgmii_pcs_get_state_an()
3020 state->speed = SPEED_10; in mt7531_sgmii_pcs_get_state_an()
3023 dev_err(priv->dev, "invalid sgmii PHY speed\n"); in mt7531_sgmii_pcs_get_state_an()
3024 state->link = false; in mt7531_sgmii_pcs_get_state_an()
3025 return -EINVAL; in mt7531_sgmii_pcs_get_state_an()
3029 state->duplex = DUPLEX_FULL; in mt7531_sgmii_pcs_get_state_an()
3031 state->duplex = DUPLEX_HALF; in mt7531_sgmii_pcs_get_state_an()
3041 struct mt7530_priv *priv = ds->priv; in mt7531_phylink_mac_link_state()
3043 if (state->interface == PHY_INTERFACE_MODE_SGMII) in mt7531_phylink_mac_link_state()
3046 return -EOPNOTSUPP; in mt7531_phylink_mac_link_state()
3053 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_state()
3055 return priv->info->mac_port_get_state(ds, port, state); in mt753x_phylink_mac_link_state()
3061 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
3062 int ret = priv->info->sw_setup(ds); in mt753x_setup()
3072 if (ret && priv->irq) in mt753x_setup()
3081 struct mt7530_priv *priv = ds->priv; in mt753x_get_mac_eee()
3084 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); in mt753x_get_mac_eee()
3085 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); in mt753x_get_mac_eee()
3093 struct mt7530_priv *priv = ds->priv; in mt753x_set_mac_eee()
3096 if (e->tx_lpi_timer > 0xFFF) in mt753x_set_mac_eee()
3097 return -EINVAL; in mt753x_set_mac_eee()
3099 set = SET_LPI_THRESH(e->tx_lpi_timer); in mt753x_set_mac_eee()
3100 if (!e->tx_lpi_enabled) in mt753x_set_mac_eee()
3184 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
3197 dn = mdiodev->dev.of_node; in mt7530_probe()
3199 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); in mt7530_probe()
3201 return -ENOMEM; in mt7530_probe()
3203 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe()
3204 if (!priv->ds) in mt7530_probe()
3205 return -ENOMEM; in mt7530_probe()
3207 priv->ds->dev = &mdiodev->dev; in mt7530_probe()
3208 priv->ds->num_ports = MT7530_NUM_PORTS; in mt7530_probe()
3211 * casues a little bit differences on power-on sequence. in mt7530_probe()
3213 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); in mt7530_probe()
3214 if (priv->mcm) { in mt7530_probe()
3215 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); in mt7530_probe()
3217 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); in mt7530_probe()
3218 if (IS_ERR(priv->rstc)) { in mt7530_probe()
3219 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); in mt7530_probe()
3220 return PTR_ERR(priv->rstc); in mt7530_probe()
3227 priv->info = of_device_get_match_data(&mdiodev->dev); in mt7530_probe()
3228 if (!priv->info) in mt7530_probe()
3229 return -EINVAL; in mt7530_probe()
3234 if (!priv->info->sw_setup || !priv->info->pad_setup || in mt7530_probe()
3235 !priv->info->phy_read || !priv->info->phy_write || in mt7530_probe()
3236 !priv->info->phy_mode_supported || in mt7530_probe()
3237 !priv->info->mac_port_validate || in mt7530_probe()
3238 !priv->info->mac_port_get_state || !priv->info->mac_port_config) in mt7530_probe()
3239 return -EINVAL; in mt7530_probe()
3241 priv->id = priv->info->id; in mt7530_probe()
3243 if (priv->id == ID_MT7530) { in mt7530_probe()
3244 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); in mt7530_probe()
3245 if (IS_ERR(priv->core_pwr)) in mt7530_probe()
3246 return PTR_ERR(priv->core_pwr); in mt7530_probe()
3248 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); in mt7530_probe()
3249 if (IS_ERR(priv->io_pwr)) in mt7530_probe()
3250 return PTR_ERR(priv->io_pwr); in mt7530_probe()
3254 * integrated circuit so the GPIO pin would be used to complete in mt7530_probe()
3255 * the reset, otherwise memory-mapped register accessing used in mt7530_probe()
3258 if (!priv->mcm) { in mt7530_probe()
3259 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", in mt7530_probe()
3261 if (IS_ERR(priv->reset)) { in mt7530_probe()
3262 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); in mt7530_probe()
3263 return PTR_ERR(priv->reset); in mt7530_probe()
3267 priv->bus = mdiodev->bus; in mt7530_probe()
3268 priv->dev = &mdiodev->dev; in mt7530_probe()
3269 priv->ds->priv = priv; in mt7530_probe()
3270 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe()
3271 mutex_init(&priv->reg_mutex); in mt7530_probe()
3272 dev_set_drvdata(&mdiodev->dev, priv); in mt7530_probe()
3274 return dsa_register_switch(priv->ds); in mt7530_probe()
3280 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); in mt7530_remove()
3286 ret = regulator_disable(priv->core_pwr); in mt7530_remove()
3288 dev_err(priv->dev, in mt7530_remove()
3291 ret = regulator_disable(priv->io_pwr); in mt7530_remove()
3293 dev_err(priv->dev, "Failed to disable io pwr: %d\n", in mt7530_remove()
3296 if (priv->irq) in mt7530_remove()
3299 dsa_unregister_switch(priv->ds); in mt7530_remove()
3300 mutex_destroy(&priv->reg_mutex); in mt7530_remove()
3302 dev_set_drvdata(&mdiodev->dev, NULL); in mt7530_remove()
3307 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); in mt7530_shutdown()
3312 dsa_switch_shutdown(priv->ds); in mt7530_shutdown()
3314 dev_set_drvdata(&mdiodev->dev, NULL); in mt7530_shutdown()