Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #define KS_PRIO_S 2
36 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
37 #define KSZ8863_PCS_RESET BIT(0)
41 #define SW_NEW_BACKOFF BIT(7)
42 #define SW_GLOBAL_RESET BIT(6)
43 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
44 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
45 #define SW_LINK_AUTO_AGING BIT(0)
49 #define SW_HUGE_PACKET BIT(6)
50 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
51 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
52 #define SW_CHECK_LENGTH BIT(3)
53 #define SW_AGING_ENABLE BIT(2)
54 #define SW_FAST_AGING BIT(1)
55 #define SW_AGGR_BACKOFF BIT(0)
59 #define UNICAST_VLAN_BOUNDARY BIT(7)
60 #define MULTICAST_STORM_DISABLE BIT(6)
61 #define SW_BACK_PRESSURE BIT(5)
62 #define FAIR_FLOW_CTRL BIT(4)
63 #define NO_EXC_COLLISION_DROP BIT(3)
64 #define SW_LEGAL_PACKET_DISABLE BIT(1)
67 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3)
69 #define SW_VLAN_ENABLE BIT(7)
70 #define SW_IGMP_SNOOP BIT(6)
71 #define SW_MIRROR_RX_TX BIT(0)
75 #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7)
76 #define SW_HALF_DUPLEX BIT(6)
77 #define SW_FLOW_CTRL BIT(5)
78 #define SW_10_MBIT BIT(4)
79 #define SW_REPLACE_VID BIT(3)
89 #define SW_MIB_COUNTER_FLUSH BIT(7)
90 #define SW_MIB_COUNTER_FREEZE BIT(6)
103 #define SW_LED_LINK_ACT_DUPLEX 2
108 #define SW_PASS_PAUSE BIT(0)
114 #define SW_PLL_POWER_DOWN BIT(5)
119 #define SW_SOFTWARE_POWER_DOWN 2
129 #define PORT_BROADCAST_STORM BIT(7)
130 #define PORT_DIFFSERV_ENABLE BIT(6)
131 #define PORT_802_1P_ENABLE BIT(5)
136 #define PORT_BASED_PRIO_2 2
138 #define PORT_INSERT_TAG BIT(2)
139 #define PORT_REMOVE_TAG BIT(1)
140 #define PORT_QUEUE_SPLIT_L BIT(0)
148 #define PORT_MIRROR_SNIFFER BIT(7)
149 #define PORT_MIRROR_RX BIT(6)
150 #define PORT_MIRROR_TX BIT(5)
159 #define PORT_INGRESS_FILTER BIT(6)
160 #define PORT_DISCARD_NON_VID BIT(5)
161 #define PORT_FORCE_FLOW_CTRL BIT(4)
162 #define PORT_BACK_PRESSURE BIT(3)
163 #define PORT_TX_ENABLE BIT(2)
164 #define PORT_RX_ENABLE BIT(1)
165 #define PORT_LEARN_DISABLE BIT(0)
186 #define PORT_ACL_ENABLE BIT(2)
190 #define PORT_AUTHEN_TRAP 2
194 #define PORT_MII_INTERNAL_CLOCK BIT(7)
195 #define PORT_GMII_1GPS_MODE BIT(6)
196 #define PORT_RGMII_ID_IN_ENABLE BIT(4)
197 #define PORT_RGMII_ID_OUT_ENABLE BIT(3)
198 #define PORT_GMII_MAC_MODE BIT(2)
202 #define PORT_INTERFACE_GMII 2
210 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5)
211 #define PORT_AUTO_NEG_SYM_PAUSE BIT(4)
212 #define PORT_AUTO_NEG_100BTX_FD BIT(3)
213 #define PORT_AUTO_NEG_100BTX BIT(2)
214 #define PORT_AUTO_NEG_10BT_FD BIT(1)
215 #define PORT_AUTO_NEG_10BT BIT(0)
223 #define PORT_FIBER_MODE BIT(7)
225 #define PORT_REMOTE_ASYM_PAUSE BIT(5)
226 #define PORT_REMOTE_SYM_PAUSE BIT(4)
227 #define PORT_REMOTE_100BTX_FD BIT(3)
228 #define PORT_REMOTE_100BTX BIT(2)
229 #define PORT_REMOTE_10BT_FD BIT(1)
230 #define PORT_REMOTE_10BT BIT(0)
237 #define PORT_HP_MDIX BIT(7)
238 #define PORT_REVERSED_POLARITY BIT(5)
239 #define PORT_TX_FLOW_CTRL BIT(4)
240 #define PORT_RX_FLOW_CTRL BIT(3)
241 #define PORT_STAT_SPEED_100MBIT BIT(2)
242 #define PORT_STAT_FULL_DUPLEX BIT(1)
244 #define PORT_REMOTE_FAULT BIT(0)
251 #define PORT_CABLE_10M_SHORT BIT(7)
256 #define PORT_CABLE_STAT_SHORT 2
258 #define PORT_START_CABLE_DIAG BIT(4)
259 #define PORT_FORCE_LINK BIT(3)
260 #define PORT_POWER_SAVING BIT(2)
261 #define PORT_PHY_REMOTE_LOOPBACK BIT(1)
277 #define PORT_AUTO_NEG_ENABLE BIT(7)
278 #define PORT_AUTO_NEG_DISABLE BIT(7)
279 #define PORT_FORCE_100_MBIT BIT(6)
280 #define PORT_FORCE_FULL_DUPLEX BIT(5)
287 #define PORT_LED_OFF BIT(7)
288 #define PORT_TX_DISABLE BIT(6)
289 #define PORT_AUTO_NEG_RESTART BIT(5)
290 #define PORT_POWER_DOWN BIT(3)
291 #define PORT_AUTO_MDIX_DISABLE BIT(2)
292 #define PORT_FORCE_MDIX BIT(1)
293 #define PORT_MAC_LOOPBACK BIT(0)
300 #define PORT_MDIX_STATUS BIT(7)
301 #define PORT_AUTO_NEG_COMPLETE BIT(6)
302 #define PORT_STAT_LINK_GOOD BIT(5)
309 #define PORT_PHY_LOOPBACK BIT(7)
310 #define PORT_PHY_ISOLATE BIT(5)
311 #define PORT_PHY_SOFT_RESET BIT(4)
312 #define PORT_PHY_FORCE_LINK BIT(3)
315 #define PHY_MODE_10BT_HALF 2
354 (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))
365 #define TABLE_ACL_V 2
372 #define TABLE_READ BIT(4)
373 #define TABLE_SELECT_S 2
376 #define TABLE_DYNAMIC_MAC_V 2
398 #define INT_PME BIT(4)
403 #define INT_PORT_5 BIT(4)
404 #define INT_PORT_4 BIT(3)
405 #define INT_PORT_3 BIT(2)
406 #define INT_PORT_2 BIT(1)
407 #define INT_PORT_1 BIT(0)
417 #define SWITCH_802_1P_SHIFT 2
427 #define SW_PRIO_MAP_2_HI 2
435 #define SW_SELF_ADDR_FILTER_ENABLE BIT(6)
442 #define SW_UNK_FWD_ENABLE BIT(5)
451 #define SW_IN_RATE_LIMIT_256_MS 2
452 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
453 #define SW_INS_TAG_ENABLE BIT(2)
481 #define SW_DRIVE_STRENGTH_8MA 2
491 #define SW_IPV6_MLD_OPTION BIT(3)
492 #define SW_IPV6_MLD_SNOOP BIT(2)
500 #define PORT_PASS_ALL BIT(6)
502 #define PORT_INS_TAG_FOR_PORT_5 BIT(3)
503 #define PORT_INS_TAG_FOR_PORT_4 BIT(2)
504 #define PORT_INS_TAG_FOR_PORT_3 BIT(1)
505 #define PORT_INS_TAG_FOR_PORT_2 BIT(0)
513 #define PORT_QUEUE_SPLIT_H BIT(1)
516 #define PORT_QUEUE_SPLIT_4 2
517 #define PORT_DROP_TAG BIT(0)
561 #define RATE_CTRL_ENABLE BIT(7)
562 #define RATE_RATIO_M (BIT(7) - 1)
564 #define PORT_OUT_RATE_ENABLE BIT(7)
576 #define PORT_IN_LIMIT_MODE_S 2
579 #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S)
580 #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S)
581 #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S)
584 #define PORT_IN_MULTICAST 2
586 #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S)
587 #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S)
610 #define PORT_IN_RATE_ENABLE BIT(7)
611 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
640 #define SW_PME_OUTPUT_ENABLE BIT(1)
641 #define SW_PME_ACTIVE_HIGH BIT(0)
643 #define PORT_MAGIC_PACKET_DETECT BIT(2)
644 #define PORT_LINK_UP_DETECT BIT(1)
645 #define PORT_ENERGY_DETECT BIT(0)
655 #define ACL_MODE_LAYER_3 2
658 #define ACL_ENABLE_S 2
661 #define ACL_ENABLE_2_MAC 2
664 #define ACL_ENABLE_3_SRC_DST_COMP 2
667 #define ACL_ENABLE_4_UDP_PORT_COMP 2
669 #define ACL_SRC BIT(1)
670 #define ACL_EQUAL BIT(0)
683 #define ACL_PORT_MODE_IN_RANGE 2
686 #define ACL_TCP_FLAG_ENABLE BIT(0)
698 #define ACL_PRIO_MODE_LOWER 2
702 #define ACL_VLAN_PRIO_REPLACE BIT(2)
712 #define ACL_MAP_MODE_AND 2
716 #define ACL_CNT_M (BIT(11) - 1)
718 #define ACL_MSEC_UNIT BIT(4)
719 #define ACL_INTR_MODE BIT(3)
728 #define ACL_ACTION_LEN 2
731 #define ACL_RULESET_LEN 2
742 #define PORT_ACL_WRITE_DONE BIT(6)
743 #define PORT_ACL_READ_DONE BIT(5)
744 #define PORT_ACL_WRITE BIT(4)
749 #define PORT_ACL_FORCE_DLR_MISS BIT(0)
759 #define PHY_START_CABLE_DIAG BIT(15)
766 #define PHY_CABLE_10M_SHORT BIT(12)
773 #define PHY_STAT_REVERSED_POLARITY BIT(5)
774 #define PHY_STAT_MDIX BIT(4)
775 #define PHY_FORCE_LINK BIT(3)
776 #define PHY_POWER_SAVING_ENABLE BIT(2)
777 #define PHY_REMOTE_LOOPBACK BIT(1)
822 * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
823 * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF
824 * MIB_PACKET_DROPPED 00-00000000-0000FFFF
825 * MIB_COUNTER_VALID 00-00000020-00000000
826 * MIB_COUNTER_OVERFLOW 00-00000040-00000000
843 #define TAIL_TAG_OVERRIDE BIT(6)
844 #define TAIL_TAG_LOOKUP BIT(7)