Lines Matching +full:2 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 or MIT) */
6 * Copyright (C) 2019-2021 Linutronix GmbH
20 #include <linux/platform_data/hirschmann-hellcreek.h>
27 * - 0: CPU
28 * - 1: Tunnel
29 * - 2: TSN front port 1
30 * - 3: TSN front port 2
31 * - ...
42 #define HR_MODID_C (0 * 2)
43 #define HR_REL_L_C (1 * 2)
44 #define HR_REL_H_C (2 * 2)
45 #define HR_BLD_L_C (3 * 2)
46 #define HR_BLD_H_C (4 * 2)
47 #define HR_CTRL_C (5 * 2)
48 #define HR_CTRL_C_READY BIT(14)
49 #define HR_CTRL_C_TRANSITION BIT(13)
50 #define HR_CTRL_C_ENABLE BIT(0)
52 #define HR_PSEL (0xa6 * 2)
56 #define HR_PSEL_PRTCWSEL_MASK GENMASK(2, 0)
58 #define HR_PTCFG (0xa7 * 2)
59 #define HR_PTCFG_MLIMIT_EN BIT(13)
60 #define HR_PTCFG_UMC_FLT BIT(10)
61 #define HR_PTCFG_UUC_FLT BIT(9)
62 #define HR_PTCFG_UNTRUST BIT(8)
63 #define HR_PTCFG_TAG_REQUIRED BIT(7)
66 #define HR_PTCFG_INGRESSFLT BIT(3)
67 #define HR_PTCFG_BLOCKED BIT(2)
68 #define HR_PTCFG_LEARNING_EN BIT(1)
69 #define HR_PTCFG_ADMIN_EN BIT(0)
71 #define HR_PRTCCFG (0xa8 * 2)
73 #define HR_PRTCCFG_PCP_TC_MAP_MASK GENMASK(2, 0)
75 #define HR_CSEL (0x8d * 2)
78 #define HR_CRDL (0x8e * 2)
79 #define HR_CRDH (0x8f * 2)
81 #define HR_SWTRC_CFG (0x90 * 2)
82 #define HR_SWTRC0 (0x91 * 2)
83 #define HR_SWTRC1 (0x92 * 2)
84 #define HR_PFREE (0x93 * 2)
85 #define HR_MFREE (0x94 * 2)
87 #define HR_FDBAGE (0x97 * 2)
88 #define HR_FDBMAX (0x98 * 2)
89 #define HR_FDBRDL (0x99 * 2)
90 #define HR_FDBRDM (0x9a * 2)
91 #define HR_FDBRDH (0x9b * 2)
93 #define HR_FDBMDRD (0x9c * 2)
98 #define HR_FDBMDRD_OBT BIT(8)
99 #define HR_FDBMDRD_PASS_BLOCKED BIT(9)
100 #define HR_FDBMDRD_STATIC BIT(11)
103 #define HR_FDBMDRD_REPRIO_EN BIT(15)
105 #define HR_FDBWDL (0x9d * 2)
106 #define HR_FDBWDM (0x9e * 2)
107 #define HR_FDBWDH (0x9f * 2)
108 #define HR_FDBWRM0 (0xa0 * 2)
111 #define HR_FDBWRM0_OBT BIT(8)
112 #define HR_FDBWRM0_PASS_BLOCKED BIT(9)
115 #define HR_FDBWRM0_REPRIO_EN BIT(15)
116 #define HR_FDBWRM1 (0xa1 * 2)
118 #define HR_FDBWRCMD (0xa2 * 2)
119 #define HR_FDBWRCMD_FDBDEL BIT(9)
121 #define HR_SWCFG (0xa3 * 2)
122 #define HR_SWCFG_GM_STATEMD BIT(15)
128 #define HR_SWCFG_CT_EN BIT(11)
129 #define HR_SWCFG_VLAN_UNAWARE BIT(10)
130 #define HR_SWCFG_ALWAYS_OBT BIT(9)
131 #define HR_SWCFG_FDBAGE_EN BIT(5)
132 #define HR_SWCFG_FDBLRN_EN BIT(4)
134 #define HR_SWSTAT (0xa4 * 2)
135 #define HR_SWSTAT_FAIL BIT(4)
136 #define HR_SWSTAT_BUSY BIT(0)
138 #define HR_SWCMD (0xa5 * 2)
139 #define HW_SWCMD_FLUSH BIT(0)
141 #define HR_VIDCFG (0xaa * 2)
144 #define HR_VIDCFG_PVID BIT(12)
146 #define HR_VIDMBRCFG (0xab * 2)
149 #define HR_VIDMBRCFG_P1MBR_SHIFT 2
150 #define HR_VIDMBRCFG_P1MBR_MASK GENMASK(3, 2)
156 #define HR_FEABITS0 (0xac * 2)
164 #define TR_QTRACK (0xb1 * 2)
165 #define TR_TGDVER (0xb3 * 2)
170 #define TR_TGDSEL (0xb4 * 2)
173 #define TR_TGDCTRL (0xb5 * 2)
174 #define TR_TGDCTRL_GATE_EN BIT(0)
175 #define TR_TGDCTRL_CYC_SNAP BIT(4)
176 #define TR_TGDCTRL_SNAP_EST BIT(5)
179 #define TR_TGDSTAT0 (0xb6 * 2)
180 #define TR_TGDSTAT1 (0xb7 * 2)
181 #define TR_ESTWRL (0xb8 * 2)
182 #define TR_ESTWRH (0xb9 * 2)
183 #define TR_ESTCMD (0xba * 2)
184 #define TR_ESTCMD_ESTSEC_MASK GENMASK(2, 0)
186 #define TR_ESTCMD_ESTARM BIT(4)
187 #define TR_ESTCMD_ESTSWCFG BIT(5)
188 #define TR_EETWRL (0xbb * 2)
189 #define TR_EETWRH (0xbc * 2)
190 #define TR_EETCMD (0xbd * 2)
191 #define TR_EETCMD_EETSEC_MASK GEMASK(2, 0)
193 #define TR_EETCMD_EETARM BIT(4)
194 #define TR_CTWRL (0xbe * 2)
195 #define TR_CTWRH (0xbf * 2)
196 #define TR_LCNSL (0xc1 * 2)
197 #define TR_LCNSH (0xc2 * 2)
198 #define TR_LCS (0xc3 * 2)
199 #define TR_GCLDAT (0xc4 * 2)
202 #define TR_GCLDAT_GCLWRLAST BIT(8)
203 #define TR_GCLDAT_GCLOVRI BIT(9)
204 #define TR_GCLTIL (0xc5 * 2)
205 #define TR_GCLTIH (0xc6 * 2)
206 #define TR_GCLCMD (0xc7 * 2)
248 /* Per-port timestamping resources */
251 /* Per-port Qbv schedule information */
296 * cannot be armed directly to $base_time - 8 + X, because for large deltas the
299 #define HELLCREEK_SCHEDULE_PERIOD (2 * HZ)