Lines Matching +full:0 +full:x1ff
13 REG_SWITCH_CNTRL = 0,
32 #define MDIO_MASTER_SEL (1 << 0)
35 #define SF2_REV_MASK 0xffff
37 #define SWITCH_TOP_REV_MASK 0xffff
40 #define PHY_REVISION_MASK 0xffff
43 #define IDDQ_BIAS (1 << 0)
50 #define PHY_PHYAD_MASK 0x1F
53 #define CROSSBAR_BCM4908_INT_P7 0
55 #define CROSSBAR_BCM4908_EXT_SERDES 0
60 #define RGMII_MODE_EN (1 << 0)
63 #define INT_EPHY (0 << PORT_MODE_SHIFT)
68 #define PORT_MODE_MASK 0x7
74 #define LPI_COUNT_MASK 0x3F
81 #define INTRL2_CPU_STATUS 0x00
82 #define INTRL2_CPU_SET 0x04
83 #define INTRL2_CPU_CLEAR 0x08
84 #define INTRL2_CPU_MASK_STATUS 0x0c
85 #define INTRL2_CPU_MASK_SET 0x10
86 #define INTRL2_CPU_MASK_CLEAR 0x14
89 #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
102 #define P0_IRQ_OFF 0
118 #define P7_IRQ_OFF 0
122 #define ACB_CONTROL 0x00
123 #define ACB_EN (1 << 0)
126 #define ACB_FLUSH_MASK 0x3
128 #define ACB_QUEUE_0_CFG 0x08
129 #define XOFF_THRESHOLD_MASK 0x7ff
132 #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff
136 #define PKTLEN_MASK 0x3f
137 #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4))
140 #define CORE_G_PCTL_PORT0 0x00000
141 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
142 #define CORE_IMP_CTL 0x00020
143 #define RX_DIS (1 << 0)
149 #define CORE_SWMODE 0x0002c
150 #define SW_FWDG_MODE (1 << 0)
154 #define CORE_STS_OVERRIDE_IMP 0x00038
159 #define CORE_STS_OVERRIDE_IMP2 0x39040
161 #define CORE_NEW_CTRL 0x00084
162 #define IP_MC (1 << 0)
171 #define CORE_SWITCH_CTRL 0x00088
174 #define CORE_DIS_LEARN 0x000f0
176 #define CORE_SFT_LRN_CTRL 0x000f8
179 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
180 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
181 #define LINK_STS (1 << 0)
184 #define SPEED_MASK 0x3
189 #define CORE_WATCHDOG_CTRL 0x001e4
194 #define CORE_FAST_AGE_CTRL 0x00220
195 #define EN_FAST_AGE_STATIC (1 << 0)
203 #define CORE_FAST_AGE_PORT 0x00224
204 #define AGE_PORT_MASK 0xf
206 #define CORE_FAST_AGE_VID 0x00228
207 #define AGE_VID_MASK 0x3fff
209 #define CORE_LNKSTS 0x00400
210 #define LNK_STS_MASK 0x1ff
212 #define CORE_SPDSTS 0x00410
213 #define SPDSTS_10 0
217 #define SPDSTS_MASK 0x3
219 #define CORE_DUPSTS 0x00420
220 #define CORE_DUPSTS_MASK 0x1ff
222 #define CORE_PAUSESTS 0x00428
225 #define CORE_GMNCFGCFG 0x0800
226 #define RST_MIB_CNT (1 << 0)
229 #define CORE_IMP0_PRT_ID 0x0804
231 #define CORE_RST_MIB_CNT_EN 0x0950
233 #define CORE_ARLA_VTBL_RWCTRL 0x1600
234 #define ARLA_VTBL_CMD_WRITE 0
239 #define CORE_ARLA_VTBL_ADDR 0x1604
240 #define VTBL_ADDR_INDEX_MASK 0xfff
242 #define CORE_ARLA_VTBL_ENTRY 0x160c
243 #define FWD_MAP_MASK 0x1ff
244 #define UNTAG_MAP_MASK 0x1ff
246 #define MSTP_INDEX_MASK 0x7
250 #define CORE_MEM_PSM_VDD_CTRL 0x2380
252 #define P_TXQ_PSM_VDD_MASK 0x3
256 #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10))
257 #define PRT_TO_QID_MASK 0x3
260 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
261 #define PORT_VLAN_CTRL_MASK 0x1ff
263 #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80
264 #define TXQ_PAUSE_THD_MASK 0x7ff
266 (x) * 0x8)
268 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
271 #define PRI_MASK 0x7
273 #define CORE_JOIN_ALL_VLAN_EN 0xd140
275 #define CORE_CFP_ACC 0x28000
276 #define OP_STR_DONE (1 << 0)
290 #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT)
293 #define XCESS_ADDR_MASK 0xff
301 #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010
303 #define CORE_CFP_DATA_PORT_0 0x28040
305 (x) * 0x10)
309 #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT)
311 #define IPTOS_MASK 0xff
313 #define IPPROTO_MASK (0xff << IPPROTO_SHIFT)
321 #define SLICE_NUM_MASK 0x3
323 #define CORE_CFP_MASK_PORT_0 0x280c0
326 (x) * 0x10)
328 #define CORE_ACT_POL_DATA0 0x28140
329 #define VLAN_BYP (1 << 0)
333 #define REASON_CODE_MASK 0x3f
336 #define NEW_TC_MASK 0x7
339 #define DST_MAP_IB_MASK 0x1ff
341 #define CHANGE_FWRD_MAP_IB_MASK 0x3
342 #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT)
347 #define NEW_DSCP_IB_MASK 0x3f
349 #define CORE_ACT_POL_DATA1 0x28150
350 #define CHANGE_DSCP_IB (1 << 0)
352 #define DST_MAP_OB_MASK 0x3ff
354 #define CHANGE_FWRD_MAP_OB_MASK 0x3
356 #define NEW_DSCP_OB_MASK 0x3f
359 #define CHAIN_ID_MASK 0xff
362 #define NEW_COLOR_MASK 0x3
363 #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT)
368 #define CORE_ACT_POL_DATA2 0x28160
369 #define MAC_LIMIT_BYPASS (1 << 0)
372 #define NEW_TC_O_MASK 0x7
377 #define CORE_RATE_METER0 0x28180
378 #define COLOR_MODE (1 << 0)
382 #define POLICER_MODE_MASK 0x3
383 #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT)
388 #define CORE_RATE_METER1 0x28190
389 #define EIR_TK_BKT_MASK 0x7fffff
391 #define CORE_RATE_METER2 0x281a0
392 #define EIR_BKT_SIZE_MASK 0xfffff
394 #define CORE_RATE_METER3 0x281b0
395 #define EIR_REF_CNT_MASK 0x7ffff
397 #define CORE_RATE_METER4 0x281c0
398 #define CIR_TK_BKT_MASK 0x7fffff
400 #define CORE_RATE_METER5 0x281d0
401 #define CIR_BKT_SIZE_MASK 0xfffff
403 #define CORE_RATE_METER6 0x281e0
404 #define CIR_REF_CNT_MASK 0x7ffff
406 #define CORE_STAT_GREEN_CNTR 0x28200
407 #define CORE_STAT_YELLOW_CNTR 0x28210
408 #define CORE_STAT_RED_CNTR 0x28220
410 #define CORE_CFP_CTL_REG 0x28400
411 #define CFP_EN_MAP_MASK 0x1ff
414 #define CORE_UDF_0_A_0_8_PORT_0 0x28440
415 #define CFG_UDF_OFFSET_MASK 0x1f
417 #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT)
422 #define CORE_UDF_0_B_0_8_PORT_0 0x28500
425 #define CORE_UDF_0_D_0_11_PORT_0 0x28680
432 #define UDF_SLICE_OFFSET 0x40